Code

Scope#91

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cindy-q wants to merge 71 commits intoOpenMRI:main-nextOpenMRI/ocra:main-nextfrom cindy-q:feature/scopecindy-q/ocra:feature/scopeCopy head branch name to clipboard

+8,911-34

Commits

Commits on Sep 29, 2023

• receiver to datamover core added

  cindy-q

  committed
  22ca353

Commits on Sep 30, 2023

• bd changes. still need to add axi sniffer, add external clock interface, microseq unpause, external debouncer

  cindy-q

  committed
  e588c38

Commits on Oct 2, 2023

• sniffer

  cindy-q

  committed
  1431bc4

• added all things. need testing

  cindy-q

  committed
  0f18e8e

• removing scope from rp 125_14

  cindy-q

  committed
  6b30daf

Commits on Oct 3, 2023

• Renamed interrupt pin on dma_rx core to avoid vivado's interrupt inference. Makefile change to generate devicetree with overlay. Added a generic UIO interrupt overlay for the dma_rx core. Added bla…

  Show description for 6921711
  cindy-q

  committed
  6921711

• update on devicetree script such that the firmware name will follow the updated project naming scheme

  cindy-q

  committed
  631de96

Commits on Oct 4, 2023

• oops.. forgot to change this one

  cindy-q

  committed
  c19a698

Commits on Oct 7, 2023

• Added an example data transfer project. Fix to DDR address range on the scope project.

  cindy-q

  committed
  64d9658

Commits on Oct 10, 2023

• micro-sequencer:

  Show description for c13aca7
  cindy-q

  committed
  c13aca7

• adding the interrupt connections to the PS

  cindy-q

  committed
  bfd56c1

• Merge branch 'OpenMRI:main' into feature/scope

  cindy-q

  authored
  19d0353

Commits on Dec 7, 2023

• Merge branch 'main' into feature/scope

  cindy-q

  committed
  4e5c86c

Commits on Feb 13, 2024

• Merge branch 'main' into feature/scope

  cindy-q

  committed
  2d52d86

Commits on Feb 14, 2024

• adding sata (s1) input clock, and trigger io moved to the sata s2 input. still need to add 4 channels, update rx tx, and add new board for 4-input RP

  cindy-q

  committed
  4cf0fed

• removing the external clock board. it is similar enough to regular RP with two more optional input pins

  cindy-q

  committed
  0fdb0cd

• syncing rx2 to the latest main. thomas' branch is still incoming

  cindy-q

  committed
  5dcc784

• rp 125 14 4 input board files

  cindy-q

  committed
  ad1335a

• more board updates

  cindy-q

  committed
  709bc8b

Commits on Feb 16, 2024

• adding 4ch support. still need to add SPI configuration and the AXI control

  cindy-q

  committed
  f4c88b5

Commits on Feb 17, 2024

• more things

  cindy-q

  committed
  72a7368

• trigger

  cindy-q

  committed
  9b5a583

Commits on Feb 21, 2024

• reducing rx channel to only 3 as space utilization has been exceeded. will revisit again once the rx and tx chain has been updated. addex fix on core generation to also include systemverilog files

  cindy-q

  committed
  00b068e

Commits on Feb 27, 2024

• - add test pattern validation on the ddr core.

  Show description for 676b67c
  cindy-q

  committed
  676b67c

• address mapping updated from ocra-mri. connected manual spi write control and pattern validation logic added for manual tuning

  cindy-q

  committed
  5b1cf09

• adding modulation option. fix on net typo

  cindy-q

  committed
  234a13d

Commits on Mar 2, 2024

• zynq ddr transfer test added

  cindy-q

  committed
  4d64081

• more files

  cindy-q

  committed
  a95f1b3

Commits on Mar 4, 2024

• irq

  cindy-q

  committed
  91166fc

Commits on Mar 5, 2024

• splitting project to advanced (useq controlled), and simple (width controlled)

  cindy-q

  committed
  2495458

Commits on Mar 6, 2024

• - new simplified scope mode added

  Show description for 2fbf283
  cindy-q

  committed
  2fbf283

• more file to check in

  cindy-q

  committed
  8733f57

Commits on Mar 7, 2024

• corrected a comment and added addressing to the trigger core

  cindy-q

  committed
  65509d3

Commits on Mar 8, 2024

• fifoed window capture

  cindy-q

  committed
  11c4692

• led

  cindy-q

  committed
  a7f9fff

• bugfix

  cindy-q

  committed
  ba5b2dd

• remove fir and fp cores

  cindy-q

  committed
  516558b

• changing nco resolution

  cindy-q

  committed
  2dc750e

Commits on Mar 11, 2024

• rearranging address

  cindy-q

  committed
  5cc8b76

Commits on Mar 13, 2024

• some testing

  cindy-q

  committed
  6a92a7f

Commits on Mar 15, 2024

• bug fix on dropped samples during window transition when the is no delay

  cindy-q

  committed
  e1f8d54

Commits on Mar 19, 2024

• fix in axis dma rx core to break apart big transfers to 4096 words at a time

  cindy-q

  committed
  b48a044

Commits on May 1, 2024

• bugfix on triggering capture at the falling edge of the trigger

  cindy-q

  committed
  e818357

Commits on May 2, 2024

• state readback fix

  cindy-q

  committed
  1a094a8

Commits on May 7, 2024

• adding state register read

  cindy-q

  committed
  ea3e2b1

• dma aggregate read on top level status register

  cindy-q

  committed
  846afd6

Commits on May 30, 2024

• 2ch adc

  cindy-q

  committed
  ec07efe

• rx acquisition with timestamp

  cindy-q

  committed
  d5cf6d8

Commits on May 31, 2024

• microsequencer additions. rx acquisition core. 2ch adc bugfix.

  cindy-q

  committed
  46f534d

• axi write core

  cindy-q

  committed
  68afd6a

• microsequencer v1.1\

  cindy-q

  committed
  7135e41

Commits on Jun 4, 2024

• microsequencer to start on external trigger

  cindy-q

  committed
  60a475a

• irq uio update

  cindy-q

  committed
  cf739f3

Commits on Jun 5, 2024

• Merge branch 'main' into feature/scope

  cindy-q

  committed
  4e2af4e

Commits on Jun 7, 2024

• reduced data event interrupt to one bit. add polling support for data event interrupt. added device id and device version. gradient scope expanded to four channels.

  cindy-q

  committed
  7108771

Commits on Jun 11, 2024

• resizing transmit bram. z10 rf scope is practically full after this point

  cindy-q

  committed
  cacf89b

Commits on Jun 12, 2024

• address change for tx

  cindy-q

  committed
  71a5a96

Commits on Jun 13, 2024

• adding internal trigger. this is to safely stop the microsequencer shall the external trigger stop for any unexpected reason.

  cindy-q

  committed
  6826b4b

Commits on Jun 14, 2024

• acq_trigger core: updated register map info and make gating sensitive only to rising edges

  cindy-q

  committed
  e4ce752

• rx_trigger core: updated register map info and make gating sensitive only to rising edges

  cindy-q

  committed
  5407ce8

• bugfix on aggregate rx irq logic

  cindy-q

  committed
  7105a46

• Changing implementation strategy. Scope RF project utilization is high on Z10 PL.

  cindy-q

  committed
  95fb5d7

Commits on Jun 17, 2024

• oops

  cindy-q

  committed
  40818ac

Commits on Jun 19, 2024

• cli tool to read and write PL registers

  cindy-q

  committed
  65844bd

Commits on Jun 20, 2024

• fixed address cells and size cells to 1

  cindy-q

  committed
  339addd

Commits on Jun 28, 2024

• updating reg_rw gitignore

  cindy-q

  committed
  6f36244

Commits on Jun 29, 2024

• buffer select on fpga

  cindy-q

  committed
  4de5d74

Commits on Jul 19, 2024

• moved trigger to sata s2 port a. version bump at 0x3

  cindy-q

  committed
  cb74cc2

Commits on Jul 24, 2024

• ooops.. forgot to change the IO on the RF scope

  cindy-q

  committed
  660887b

Commits on Jul 26, 2024

• adding queued axi write to the scope project

  cindy-q

  committed
  d4b6d08

• oops

  cindy-q

  committed
  3ca38f1