Improvements to the HDL build

HDL/.gitignore

@@ -3,4 +3,5 @@ uImage
 devicetree.dtb
 *~
 tmp/
-vivado*
+vivado*
+.Xil/

HDL/Makefile

@@ -15,15 +15,15 @@ CORES_PAVEL = axi_axis_reader_v1_0 axi_axis_writer_v1_0 axi_bram_reader_v1_0 \
         axis_zeroer_v1_0 axis_variable_v1_0 axis_interpolator_v1_0 \
         axi_sts_register_v1_0
 
-CORES = micro_sequencer_v1_0 axi_dac_spi_sequencer_v1_1 axi_dac_daisy_spi_sequencer_v1_0 axis_segmented_bram_reader_v1_0 axi_serial_attenuator_v1_0 axi_four_ltc2656_spi_v1_0 axi_trigger_core_v1_0 axis_red_pitaya_adc_v3_0 axi_config_registers_v1_0
+CORES = micro_sequencer_v1_0 axi_dac_spi_sequencer_v1_1 axi_dac_daisy_spi_sequencer_v1_0 axis_segmented_bram_reader_v1_0 axi_serial_attenuator_v1_0 axi_four_ltc2656_spi_v1_0 axi_trigger_core_v1_0 axis_red_pitaya_adc_v3_0 axi_config_registers_v1_0 axis_red_pitaya_dac_v1_1
 
 VIVADO = vivado -nolog -nojournal -mode batch
 HSI = xsct
 RM = rm -rf
 
 VIVADO_VER = $(shell vivado -version | grep "v20" | sed -r 's/.*v(20[0-9]{2}.[0-9]).*/\1/g')
 
-DTREE_TAG = xlnx_rel_v2022.2
+DTREE_TAG = xlnx_rel_v2024.1
 
 DTREE_DIR = tmp/device-tree-xlnx-$(DTREE_TAG)
 DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/
@@ -34,8 +34,10 @@ DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/
 .PHONY: clean all xpr bit dtbo setup
 
 .ONESHELL:
-all: setup tmp/%.bin tmp/%.dtbo
+all: setup tmp/%.bin
 
+.ONESHELL:
+xsa: setup tmp/%.xsa
 
 .ONESHELL:
 xpr: setup tmp/%.xpr

HDL/README.md

@@ -2,11 +2,11 @@
 
 This directory contains all the HDL code of the ocra project. The code is organized in projects, which can be found in subdirectories of the projects folders.
 
-In order to build the HDL code you need to have Xilinx Vitis 2022.2 full edition. We highly recommend that you use Linux, because the build system and other tooling relies on Linux. We are working on and recommend [Ubuntu 22.04 LTS](https://ubuntu.com/download/desktop).
+In order to build the HDL code you need to have at least Xilinx Vitis 2022.2 full edition. This build has been tested up to Vitis 2024.1. We highly recommend that you use Linux, because the build system and other tooling relies on Linux. We are working on and recommend [Ubuntu 22.04 LTS or Ubuntu 24.04 LTS](https://ubuntu.com/download/desktop).
 
 **Basic working knowledge of Linux and bash is more or less required to follow these instructions.**
 
-In order to install Vitis you will need about 110 GB of free disk space, and you will need to register an account with Xilinx website (remember the password, because the installer will also require the same login credentials that you created on the Xilinx website. It is best to download the [Vitis web installer](https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2022.2_1014_8888_Lin64.bin).
+In order to install Vitis you will need about 110 GB of free disk space, and you will need to register an account with Xilinx website (remember the password, because the installer will also require the same login credentials that you created on the Xilinx website. It is best to download the [Vitis web installer](https://account.amd.com/en/forms/downloads/xef.html?filename=FPGAs_AdaptiveSoCs_Unified_2024.1_0522_2023_Lin64.bin).
 
 Vivado (the main tool in the Vitis package) is a bit of a beast and requires a reasonably powerful workstation.
 
@@ -15,15 +15,18 @@ All building of the HDL is done by a [GNU Makefile](https://www.gnu.org/software
 This makes it straightforward to build multiple projects etc. from the command line without having to wrestle the Vivado GUI. This entire setup is based on the [red-pitaya-notes](https://github.com/pavel-demin/red-pitaya-notes) by Pavel Demin, and some of his architecture and cores can also be found in this repository.
 
 This repository makes use of Vivado board files, which requires additional configuration of your Vivado/Vitis setup. In order to make everything work the following configuration steps need to be taken:
-1. Add `source /tools/Xilinx/Vitis/2022.2/settings64.sh` to your `.bash_profile`
+1. Add `source /tools/Xilinx/Vitis/2024.1/settings64.sh` to your `.bash_profile`
 1. Define the environment variable OCRA_DIR in your `.bash_profile` to point to the ocra directory
-2. Include the following in your local Vivado config (i.e. $HOME/.Xilinx/Vivado/2022.2/Vivado_init.tcl):
+2. Include the following in your local Vivado config (i.e. $HOME/.Xilinx/Vivado/2024.1/Vivado_init.tcl):
 ```
 # set up the OCRA project
 set ocra_dir $::env(OCRA_DIR)
 source $ocra_dir/HDL/scripts/Vivado_ocra_init.tcl
 ```
 
+You may need to adjust the path of your Vitis installation as appropriate for this to be correct on your installation.
+
+
 To get a quick start, assuming you have Vitis/Vivado configured in your path, you should be able to build the base_pl project for the snickerdoodle_black
 ```
 cd $OCRA_DIR/HDL
@@ -34,5 +37,17 @@ Similarily, you can build the ocra_mri project for the stemlab_125_14 by calling
 ```
 make NAME=ocra_mri BOARD=stemlab_125_14
 ```
+This will build bitfiles that can be used with on a Linux installation on your Zynq so long it supports the fpga_manager. 
+
+Sometimes you might want to only quickly generate the project file for Vivado, which you make by calling:
+```
+make xpr NAME=ocra_mri BOARD=stemlab_125_14
+```
+
+If you want to build a device tree and the associated files to create your own bootloader etc. you need to run:
+```
+make dtbo NAME=ocra_mri BOARD=stemlab_125_14
+```
+Note that this requires the HSI tool xsct and the device tree compiler dtc.
 
 This is pretty easy, isn't it?

HDL/projects/ocra_mri/block_design.tcl → HDL/blockdesign-projects/ocra_mri/block_design.tcl

@@ -3,6 +3,15 @@ global project_name
 
 set ps_preset boards/${board_name}/ps_${project_name}.xml
 
+# define some variables needed for later
+variable dsp_clk_freq
+
+if {$board_name == "stemlab_122_16"} {
+    set dsp_clk_freq 122.88
+} else {
+    set dsp_clk_freq 125.0
+}
+
 # Create processing_system7
 cell xilinx.com:ip:processing_system7:5.5 ps_0 {
   PCW_IMPORT_BOARD_PRESET $ps_preset
@@ -20,11 +29,14 @@ apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
 # Create proc_sys_reset
 cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
 
+puts "OCRA: DSP_CLK_FREQ:"
+puts $dsp_clk_freq
+
 # Create clk_wiz
 cell xilinx.com:ip:clk_wiz:6.0 pll_0 {
   PRIMITIVE PLL
   PRIM_IN_FREQ.VALUE_SRC USER
-  PRIM_IN_FREQ 125.0
+  PRIM_IN_FREQ $dsp_clk_freq
   PRIM_SOURCE Differential_clock_capable_pin
   CLKOUT1_USED true
   CLKOUT1_REQUESTED_OUT_FREQ 125.0
@@ -36,33 +48,12 @@ cell xilinx.com:ip:clk_wiz:6.0 pll_0 {
   clk_in1_p adc_clk_p_i
   clk_in1_n adc_clk_n_i
 }
+
 cell open-mri:user:axi_config_registers:1.0 cfg8 {
     AXI_ADDR_WIDTH 5
     AXI_DATA_WIDTH 32
 }
 
-# Create slice with the TX configuration, which uses the bottom 32 bits
-cell xilinx.com:ip:xlslice:1.0 txinterpolator_slice_0 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_0
-}
-
-# Create slice with the RX configuration and NCO configuration
-# RX seems to use the bottom 16 bit of the upper 32 bit
-# NCO uses the bottom 32 bit
-cell xilinx.com:ip:xlslice:1.0 nco_slice_0 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_1
-}
-
-cell xilinx.com:ip:xlslice:1.0 rx_slice_0 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_2
-}
-
 # ADC switch slice
 cell xilinx.com:ip:xlslice:1.0 cfg_adc_switch {
   DIN_WIDTH 32 DIN_FROM 1 DIN_TO 0 DOUT_WIDTH 2
@@ -81,12 +72,6 @@ cell xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 {
 set_property CONFIG.CDC_TYPE {xpm_cdc_array_single} [get_bd_cells xpm_cdc_gen_0]
 set_property CONFIG.WIDTH {2} [get_bd_cells xpm_cdc_gen_0]
 
-# Create another slice with data for the TX, which is another 32 bit
-cell xilinx.com:ip:xlslice:1.0 cfg_slice_1 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_3
-}
 # ADC
 
 # Create axis_red_pitaya_adc
@@ -99,7 +84,7 @@ cell open-mri:user:axis_red_pitaya_adc:3.0 adc_0 {} {
 }
 
 # Create axis_red_pitaya_dac
-cell pavel-demin:user:axis_red_pitaya_dac:1.0 dac_0 {} {
+cell open-mri:user:axis_red_pitaya_dac:1.1 dac_0 {} {
   aclk pll_0/clk_out1
   ddr_clk pll_0/clk_out2
   locked pll_0/locked
@@ -110,36 +95,35 @@ cell pavel-demin:user:axis_red_pitaya_dac:1.0 dac_0 {} {
   dac_dat dac_dat_o
 }
 
-
 # Create xlconstant
 cell xilinx.com:ip:xlconstant:1.1 const_0
 
 # Removed this connection from rx:
 # slice_0/Din rst_slice_0/Dout
 module rx_0 {
-  source projects/ocra_mri/rx2.tcl
+  source blockdesign-projects/ocra_mri/rx2.tcl
 } {
-  rate_slice/Din rx_slice_0/Dout
+  rate_slice/Din cfg8/config_2
   fifo_0/S_AXIS adc_0/M_AXIS
   fifo_0/s_axis_aclk pll_0/clk_out1
   fifo_0/s_axis_aresetn const_0/dout
 }
 
-#  axis_interpolator_0/cfg_data txinterpolator_slice_0/Dout  
+#  axis_interpolator_0/cfg_data cfg8/config_0  
 module tx_0 {
-  source projects/ocra_mri/tx6.tcl
+  source blockdesign-projects/ocra_mri/tx6.tcl
 } {
-  slice_1/Din cfg_slice_1/Dout
-  axis_interpolator_0/cfg_data txinterpolator_slice_0/Dout
+  slice_1/Din cfg8/config_3
+  axis_interpolator_0/cfg_data cfg8/config_0
   fifo_1/M_AXIS dac_0/S_AXIS
   fifo_1/m_axis_aclk pll_0/clk_out1
   fifo_1/m_axis_aresetn const_0/dout
 }
 
 module nco_0 {
-    source projects/ocra_mri/nco.tcl
+    source blockdesign-projects/ocra_mri/nco.tcl
 } {
-  slice_1/Din nco_slice_0/Dout
+  slice_1/Din cfg8/config_1
   bcast_nco/M00_AXIS rx_0/mult_0/S_AXIS_B
   bcast_nco/M01_AXIS tx_0/mult_0/S_AXIS_B
 }
@@ -362,7 +346,7 @@ set_property RANGE 8K [get_bd_addr_segs ps_0/Data/SEG_gradient_writerz2_reg0]
 set_property OFFSET 0x40008000 [get_bd_addr_segs ps_0/Data/SEG_gradient_writerz2_reg0]
 
 module gradient_dac_0 {
-    source projects/ocra_mri/gradient_dacs.tcl
+    source blockdesign-projects/ocra_mri/gradient_dacs.tcl
 } {
     spi_sequencer_0/BRAM_PORTX gradient_memoryx/BRAM_PORTB
     spi_sequencer_0/BRAM_PORTY gradient_memoryy/BRAM_PORTB
@@ -415,16 +399,6 @@ set_property -dict [list CONFIG.Register_PortB_Output_of_Memory_Primitives {true
 #
 # try to connect the bottom 8 bits of the pulse output of the sequencer to the positive gpoi
 #
-# Delete input/output port
-delete_bd_objs [get_bd_ports exp_p_tri_io]
-delete_bd_objs [get_bd_ports exp_n_tri_io]
-
-# Create newoutput port
-create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
-#connect_bd_net [get_bd_pins exp_p_tri_io] [get_bd_pins trigger_slice_0/Dout]
-
-# Create output port for the SPI stuff
-create_bd_port -dir O -from 7 -to 0 exp_n_tri_io
 
 # 09/2019: For the new board we are doing this differently. The SPI bus will use seven pins on the n side of the header
 #          and the txgate will use the eight' pin on the n side

HDL/projects/ocra_mri/nco.tcl → HDL/blockdesign-projects/ocra_mri/nco.tcl

@@ -3,6 +3,8 @@
 # 2017 by Thomas Witzel
 # block design for the NCO 
 
+global dsp_clk_freq
+
 # Create xlslice
 cell xilinx.com:ip:xlslice:1.0 slice_1 {
   DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
@@ -18,7 +20,7 @@ cell pavel-demin:user:axis_constant:1.0 phase_nco {
 
 # Create dds_compiler
 cell xilinx.com:ip:dds_compiler:6.0 dds_nco {
-  DDS_CLOCK_RATE 125
+  DDS_CLOCK_RATE $dsp_clk_freq
   SPURIOUS_FREE_DYNAMIC_RANGE 138
   FREQUENCY_RESOLUTION 0.2
   PHASE_INCREMENT Streaming

HDL/projects/ocra_mri/rx2.tcl → HDL/blockdesign-projects/ocra_mri/rx2.tcl

@@ -1,3 +1,5 @@
+global dsp_clk_freq
+
 # Create xlslice
 # Trigger slice on Bit 1 (RX pulse)
 cell xilinx.com:ip:xlslice:1.0 slice_0 {
@@ -27,15 +29,15 @@ cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create cmpy
+# The top 24 bits is the most we need, 16 would probably be fine as well
 cell xilinx.com:ip:cmpy:6.0 mult_0 {
   FLOWCONTROL Blocking
   APORTWIDTH.VALUE_SRC USER
   BPORTWIDTH.VALUE_SRC USER
   APORTWIDTH 16
   BPORTWIDTH 24
   ROUNDMODE Random_Rounding
-  OUTPUTWIDTH 26
+  OUTPUTWIDTH 24
 } {
   S_AXIS_A fifo_0/M_AXIS
   S_AXIS_CTRL lfsr_0/M_AXIS
@@ -46,10 +48,10 @@ cell xilinx.com:ip:cmpy:6.0 mult_0 {
 cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
   S_TDATA_NUM_BYTES.VALUE_SRC USER
   M_TDATA_NUM_BYTES.VALUE_SRC USER
-  S_TDATA_NUM_BYTES 8
+  S_TDATA_NUM_BYTES 6
   M_TDATA_NUM_BYTES 3
   M00_TDATA_REMAP {tdata[23:0]}
-  M01_TDATA_REMAP {tdata[55:32]}
+  M01_TDATA_REMAP {tdata[47:24]}
 } {
   S_AXIS mult_0/M_AXIS_DOUT
   aclk /ps_0/FCLK_CLK0
@@ -83,7 +85,7 @@ cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
   MINIMUM_RATE 25
   MAXIMUM_RATE 8192
   FIXED_OR_INITIAL_RATE 625
-  INPUT_SAMPLE_FREQUENCY 125
+  INPUT_SAMPLE_FREQUENCY $dsp_clk_freq
   CLOCK_FREQUENCY 125
   INPUT_DATA_WIDTH 24
   QUANTIZATION Truncation
@@ -107,7 +109,7 @@ cell xilinx.com:ip:cic_compiler:4.0 cic_1 {
   MINIMUM_RATE 25
   MAXIMUM_RATE 8192
   FIXED_OR_INITIAL_RATE 625
-  INPUT_SAMPLE_FREQUENCY 125
+  INPUT_SAMPLE_FREQUENCY $dsp_clk_freq
   CLOCK_FREQUENCY 125
   INPUT_DATA_WIDTH 24
   QUANTIZATION Truncation
@@ -159,7 +161,7 @@ cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
   SAMPLE_FREQUENCY 5.0
   CLOCK_FREQUENCY 125
   OUTPUT_ROUNDING_MODE Convergent_Rounding_to_Even
-  OUTPUT_WIDTH 26
+  OUTPUT_WIDTH 32
   M_DATA_HAS_TREADY true
   HAS_ARESETN true
 } {
@@ -168,43 +170,13 @@ cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create axis_subset_converter
-cell xilinx.com:ip:axis_subset_converter:1.1 subset_0 {
-  S_TDATA_NUM_BYTES.VALUE_SRC USER
-  M_TDATA_NUM_BYTES.VALUE_SRC USER
-  S_TDATA_NUM_BYTES 4
-  M_TDATA_NUM_BYTES 3
-  TDATA_REMAP {tdata[23:0]}
-} {
-  S_AXIS fir_0/M_AXIS_DATA
-  aclk /ps_0/FCLK_CLK0
-  aresetn /rst_0/peripheral_aresetn
-}
-
-# Create floating_point
-cell xilinx.com:ip:floating_point:7.1 fp_0 {
-  OPERATION_TYPE Fixed_to_float
-  A_PRECISION_TYPE.VALUE_SRC USER
-  C_A_EXPONENT_WIDTH.VALUE_SRC USER
-  C_A_FRACTION_WIDTH.VALUE_SRC USER
-  A_PRECISION_TYPE Custom
-  C_A_EXPONENT_WIDTH 2
-  C_A_FRACTION_WIDTH 22
-  RESULT_PRECISION_TYPE Single
-  HAS_ARESETN true
-} {
-  S_AXIS_A subset_0/M_AXIS
-  aclk /ps_0/FCLK_CLK0
-  aresetn /rst_0/peripheral_aresetn
-}
-
-# Create axis_dwidth_converter
+# Convert the 64 bit wide complex word into sequential 32 bit words of real and imag
 cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_1 {
   S_TDATA_NUM_BYTES.VALUE_SRC USER
   S_TDATA_NUM_BYTES 4
   M_TDATA_NUM_BYTES 8
 } {
-  S_AXIS fp_0/M_AXIS_RESULT
+  S_AXIS fir_0/M_AXIS_DATA
   aclk /ps_0/FCLK_CLK0
   aresetn /rst_0/peripheral_aresetn
 }