Open-Everything FPGA in Skywater130 (672x LUTs, 7x DSPs, 7x BRAMs)

Demonstration of the fully open FABulous eFPGA using the OpenLane flow.

This repo experiments an implementation of an eFPGA from RTL to GDS with the open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 672x LUT4s (14x6 CLBs), 56x LUT5s (14x1 RegFiles), 7x DSPs and 7x BRAMs (7x1KB) with dual-ported memory blocks for register files and FIFOs. This version supports configuration over an embedded UART, a custom bitbang protocol and the wishbone bus.

The individual macros and the fabric were fully implemented using the OpenLane flow and integrated into efabless caravel_user_project wrapper.

Project structure

The most important directories are described below:

• dependencies: Dependencies like the PDK.
• doc: Documentation, not changed compared to the template.
• gds: gds files of the macros and the top level design.
• lef: lef file of the top level design. Describes the physical layout in ASCII format.
• lib: lib file of the top level design. Describes the timing characteristics of the design.
• lvs: The config for the LVS of the top level design.
• mag: mag file of the top level design. Output of magic.
• maglef: maglef file of the top level design. Output of magic.
• openlane: The configuration and source files of all macros and the top level design.
• scripts: Python and Bash scripts that helped during the design process.
• sdc: Constraints file for the top level design. Created by the write_sdc command.
• verilog: The Verilog source files used in the design.