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Dave edited this page Mar 11, 2016 · 2 revisions

Welcome to the nysa-verilog wiki!

The verilog is broken down into different groups.

  • Generic: Verilog cores that are not related to any buses (such as Wishbone or AXI) Often times these cores are used multiple times in various cores.
  • Wishbone : Wishbone Bus cores
  • AXI: AXI Bus cors
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