-
Notifications
You must be signed in to change notification settings - Fork 0
Tutorial: FPGA Programming
This tutorial shows how to do basic FPGA programming with Cloud V.
Currently, the following FPGA boards are supported:
- Lattice iCEStick Evaluation Kit
- Lattice iCE40-HX8K Breakout Board
- NANDLand GoBoard (Untested)
- Olimex iCE40HX1K-EVB (Untested)
Cloud V runs the open source icestorm toolchain under the hood.
To synthesize an FPGA bitstream on Cloud V, you need:
- A valid Verilog top module
- A pin constraints file
In the Workspace, create a new Verilog module and set it as a top module by right clicking your module from the drop down list in the Verilog file:
Here is the code for the example top module shown here:
module LightUp (clk, ledArray);
input clk;
output [7:0] ledArray;
reg [31:0] counter = 32'b0;
assign ledArray[7:0] = counter[25:18];
always @ (posedge clk) begin
counter <= counter + 1;
end
endmodule
Luckily, icestorm supports initialization in the manner shown above, so there is no need for a reset signal. You can also use an initial begin block if that's your cup of tea.
Next, you need to create a pin constraints file. You need a pinout of the board for this:
- For the iCEStick, the lovely people over at pighixxx.com have already mapped a pinout here.
- For the Breakout Board, conveniently, the names on the board are the names you want! The LEDs, however, do share pins with the GPIO (from left to right):
B5, B4, A2, A1, C5, C4, B3, C3
. Oh, and the clock is atJ3
.
Creating the file is straightforward. First you pick your board...
...then you specify the pins.
And voila. Your project is ready.
From the top menu, Project > Generate Bitstream.
From here, you can pick a constraints file (you could have multiple per project for multiple boards or whatever the case may be) and just press generate.
In the "build (read-only)" folder of your repository, a file called .bin should have been generated. Right click it and download it.
(In progress.)