-
Notifications
You must be signed in to change notification settings - Fork 0
/
VectorProcessor.qsf
94 lines (92 loc) · 5.36 KB
/
VectorProcessor.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
# Date created = 20:16:45 May 29, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# VectorProcessor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY Mem_tb
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:16:45 MAY 29, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/WB_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/DataMem_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/Mem_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/Exec_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/Decode_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/Fetch_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/ControlUnit_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PC_Register.sv
set_global_assignment -name SYSTEMVERILOG_FILE Instr_Mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE Fetch_Adder.sv
set_global_assignment -name SYSTEMVERILOG_FILE Testbench/VectorProcessor_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE MUX_WB.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALUe/ADDER_VV.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALUe/ALU_VE.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALUe/MUX_ALU.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALUe/ALU.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU_Control.sv
set_global_assignment -name SYSTEMVERILOG_FILE Pipes/MEM_WB.sv
set_global_assignment -name SYSTEMVERILOG_FILE Pipes/IF_ID.sv
set_global_assignment -name SYSTEMVERILOG_FILE Pipes/ID_EX.sv
set_global_assignment -name SYSTEMVERILOG_FILE Pipes/EX_MEM.sv
set_global_assignment -name SYSTEMVERILOG_FILE extendZero.sv
set_global_assignment -name SYSTEMVERILOG_FILE File_Register.sv
set_global_assignment -name SYSTEMVERILOG_FILE Control_Unit.sv
set_global_assignment -name SYSTEMVERILOG_FILE WB_Stage.sv
set_global_assignment -name SYSTEMVERILOG_FILE MEM_Stage.sv
set_global_assignment -name SYSTEMVERILOG_FILE Fetch_Stage.sv
set_global_assignment -name SYSTEMVERILOG_FILE EXEC_Stage.sv
set_global_assignment -name SYSTEMVERILOG_FILE Decode_Stage.sv
set_global_assignment -name SYSTEMVERILOG_FILE Data_Mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE VectorProcessor.sv
set_global_assignment -name SYSTEMVERILOG_FILE MUX_MEM.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top