controlVGA.sv.bak

module controlVGA #(parameter N)(v_enable, clk, reset, horiz_count, vert_count, R, G, B, horiz_sync, vert_sync, vga_blank, vga_sync, clkVGA);
	input logic clk, reset;
	output logic [7:0] R, G, B;
	output logic horiz_sync, vert_sync;
	output logic clkVGA;
	output logic [N:0] horiz_count, vert_count;
	output logic vga_blank, vga_sync;
	output logic v_enable;
	
	// Variables locales
	logic selector;
	logic [23:0] blank, color, display;
	
	assign blank = 0;
	assign color [7:0] = 8'hF;
	assign color [15:8] = 8'hF;
	assign color [23:16] = 8'hF;
	
	// Divisor de clk
	clockDivider clkDIV(clk, reset, clkVGA);
	 
	// Contadores
	counterH #(N) cont_h (clkVGA, v_enable, horiz_count);
	counterV #(N) cont_v (clkVGA, v_enable, vert_count);
	
	// Comparadores
	comparatorH #(N) comp_h (horiz_count, horiz_sync);
	comparatorV #(N) comp_v (vert_count, vert_sync);
	comparator_display #(N)  comp_display (horiz_count, vert_count, vga_blank, vga_sync, selector);
	
	// Mux
	mux_color muxColor(clkVGA, blank, color, selector, display);
	
	always @(posedge clkVGA)  begin
		R = display [7:0];
		G = display [15:8];
		B = display [23:16];
	end
endmodule