From e11a507fe67b8fe007a79bf0e973f8529ecb006b Mon Sep 17 00:00:00 2001 From: Zihao Yu Date: Wed, 1 Feb 2023 17:33:38 +0800 Subject: [PATCH] util: fix errors during FIRRTL pass --- src/main/scala/util/HellaQueue.scala | 1 + src/main/scala/util/ResetCatchAndSync.scala | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/util/HellaQueue.scala b/src/main/scala/util/HellaQueue.scala index 39df57f9333..b05cde563de 100644 --- a/src/main/scala/util/HellaQueue.scala +++ b/src/main/scala/util/HellaQueue.scala @@ -47,6 +47,7 @@ class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module { val fq = Module(new HellaFlowQueue(entries)(data)) fq.io.enq <> io.enq io.deq <> Queue(fq.io.deq, 1, pipe = true) + io.count := fq.io.count } object HellaQueue { diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index 70fd447a1c3..82e0bef077d 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -23,7 +23,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { // those flops) and on the output of the synchronizer circuit (to control // reset to any flops this circuit drives). - val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset) + val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool) withReset(post_psd_reset) { io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset, ~AsyncResetSynchronizerShiftReg(true.B, sync))