diff --git a/README.md b/README.md
index c389284c..f8a2cbe2 100644
--- a/README.md
+++ b/README.md
@@ -80,8 +80,8 @@ It can generate Intel HEX or Motorola S-Record output.
          i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
          TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
          HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-         MC68010 TMS9900 TMS9980 TMS9995 TMS99105 Z8001 Z8002 NS32032 MN1610
-         MN1613 MN1613A J11 T11
+         MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
+         MN1610 MN1613 MN1613A J11 T11
       -o <output>       : output file
       -l <list>         : list file
       -S[<bytes>]       : output Motorola S-Record format
@@ -122,8 +122,8 @@ It can read Intel HEX or Motorola S-Record input.
          i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
          TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
          HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-         MC68010 TMS9900 TMS9980 TMS9995 TMS99105 Z8001 Z8002 NS32032 MN1610
-         MN1613 MN1613A J11 T11
+         MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
+         MN1610 MN1613 MN1613A J11 T11
       -o <output>      : output file
       -l <list>        : list file
       <input>          : file can be Motorola S-Record or Intel HEX format
diff --git a/README_.adoc b/README_.adoc
index 81da7013..100c6bd4 100644
--- a/README_.adoc
+++ b/README_.adoc
@@ -84,8 +84,8 @@ usage: asm [-o <output>] [-l <list>] <input>
      i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
      TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
      HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-     MC68010 TMS9900 TMS9980 TMS9995 TMS99105 Z8001 Z8002 NS32032 MN1610
-     MN1613 MN1613A J11 T11
+     MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
+     MN1610 MN1613 MN1613A J11 T11
   -o <output>       : output file
   -l <list>         : list file
   -S[<bytes>]       : output Motorola S-Record format
@@ -128,8 +128,8 @@ usage: dis -C <CPU> [-o <output>] [-l <list>] <input>
      i80C48 MSM80C39 MSM80C48 i8051 i8080 i8085 V30EMU Z80 Z8 Z86C Z88
      TLCS90 INS8060 INS8070 CDP1802 CDP1804 CDP1804A SCN2650 F3850 IM6100
      HD6120 TMS7000 TMS32010 TMS32015 i8086 i80186 V30 i8096 MC68000
-     MC68010 TMS9900 TMS9980 TMS9995 TMS99105 Z8001 Z8002 NS32032 MN1610
-     MN1613 MN1613A J11 T11
+     MC68010 TMS9900 TMS9980 TMS9995 TMS99105 TMS99110 Z8001 Z8002 NS32032
+     MN1610 MN1613 MN1613A J11 T11
   -o <output>      : output file
   -l <list>        : list file
   <input>          : file can be Motorola S-Record or Intel HEX format
diff --git a/src/Makefile.arch b/src/Makefile.arch
index eff0776c..27110838 100644
--- a/src/Makefile.arch
+++ b/src/Makefile.arch
@@ -71,7 +71,7 @@ TGT_scn2650  = scn2650
 TGT_tlcs90   = tlcs90
 TGT_tms32010 = tms32010
 TGT_tms7000  = tms7000
-TGT_tms9900  = tms9900 tms9980 tms9995 tms99105
+TGT_tms9900  = tms9900 tms9980 tms9995 tms99105 tms99110
 TGT_z8000    = z8001 z8002 z8k1 z8k2
 TGT_z80      = z80 i8080_z80syn i8085_z80syn v30emu_z80syn
 TGT_z8       = z8 z86c z88
@@ -126,6 +126,7 @@ CPU_tms32010 = 32010
 CPU_tms7000  = TMS7000
 CPU_tms9900  = TMS9900
 CPU_tms99105 = TMS99105
+CPU_tms99110 = TMS99110
 CPU_tms9980  = TMS9980
 CPU_tms9995  = TMS9995
 CPU_v30emu   = V30EMU
diff --git a/src/asm_tms9900.cpp b/src/asm_tms9900.cpp
index 7bfd6c34..48563a43 100644
--- a/src/asm_tms9900.cpp
+++ b/src/asm_tms9900.cpp
@@ -69,7 +69,7 @@ void AsmTms9900::encodeCruOffset(AsmInsn &insn, const Operand &op) const {
 }
 
 void AsmTms9900::encodeModeReg(AsmInsn &insn, const Operand &op, AddrMode mode) const {
-    if (mode == M_SRC2 && insn.dst() == M_BIT2 && op.mode == M_INCR)
+    if (mode == M_SRC2 && insn.dst() == M_BIT0 && op.mode == M_INCR)
         insn.setErrorIf(op, OPERAND_NOT_ALLOWED);
     auto opc = encodeRegNumber(op.reg);
     switch (op.mode) {
@@ -83,7 +83,6 @@ void AsmTms9900::encodeModeReg(AsmInsn &insn, const Operand &op, AddrMode mode)
         break;
     case M_SYBL:
         opc = (2 << 4);
-        //       if (op.getError() != UNDEFINED_SYMBOL)
         insn.setErrorIf(op, checkAddr(op.val.getUnsigned(), !insn.byteOp()));
         insn.emitOperand16(op.val.getUnsigned());
         break;
@@ -123,9 +122,10 @@ void AsmTms9900::encodeOperand(AsmInsn &insn, const Operand &op, AddrMode mode)
     case M_DREG:
         insn.embed(encodeRegNumber(op.reg) << 6);
         break;
-    case M_DST2:
+    case M_DST4:
         insn.embedPostfix(0x4000);
         /* Fall-through */
+    case M_DST0:
     case M_SRC:
     case M_SRC2:
     case M_DST:
@@ -164,7 +164,7 @@ void AsmTms9900::encodeOperand(AsmInsn &insn, const Operand &op, AddrMode mode)
         }
         insn.embed((val16 & 0xF) << 4);
         break;
-    case M_CNT2:
+    case M_CNT4:
         insn.embedPostfix(0x4000);
         if (op.mode == M_REG) {
             if (op.reg != REG_R0)
@@ -174,7 +174,7 @@ void AsmTms9900::encodeOperand(AsmInsn &insn, const Operand &op, AddrMode mode)
         if (op.val.isZero())
             insn.setErrorIf(op, OPERAND_NOT_ALLOWED);
         /* Fall-through */
-    case M_BIT2:
+    case M_BIT0:
         if (op.val.overflow(15))
             insn.setErrorIf(op, OVERFLOW_RANGE);
         insn.embedPostfix((val16 & 0xF) << 6);
diff --git a/src/config_tms9900.h b/src/config_tms9900.h
index 9ecc1bd2..230e5288 100644
--- a/src/config_tms9900.h
+++ b/src/config_tms9900.h
@@ -27,6 +27,7 @@ enum CpuType : uint8_t {
     TMS9980,
     TMS9995,
     TMS99105,
+    TMS99110,
 };
 
 struct Config : ConfigImpl<CpuType, ADDRESS_16BIT, ADDRESS_BYTE, OPCODE_16BIT, ENDIAN_BIG, 8, 4> {
diff --git a/src/dis_tms9900.cpp b/src/dis_tms9900.cpp
index 2380b78f..d6ecac9c 100644
--- a/src/dis_tms9900.cpp
+++ b/src/dis_tms9900.cpp
@@ -37,15 +37,19 @@ Error DisTms9900::checkPostWord(DisInsn &insn) const {
     const auto post = insn.postfix();
     const auto src = (post >> 4 & 3);
     switch (insn.dst()) {
-    case M_DST2:
+    case M_DST0:
+        if ((post & 0xF000) != 0x0000)
+            insn.setErrorIf(UNKNOWN_POSTBYTE);
+        break;
+    case M_DST4:
         if ((post & 0xF000) != 0x4000)
             insn.setErrorIf(UNKNOWN_POSTBYTE);
         break;
-    case M_CNT2:
+    case M_CNT4:
         if ((post & 0xFC00) != 0x4000)
             insn.setErrorIf(UNKNOWN_POSTBYTE);
         break;
-    case M_BIT2:
+    case M_BIT0:
         // no auto increment mode.
         if ((post & 0xFC00) != 0x0000 || src == 3)
             insn.setErrorIf(UNKNOWN_POSTBYTE);
@@ -98,21 +102,22 @@ void DisTms9900::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) con
     case M_DREG:
         outRegName(out, opc >> 6);
         break;
-    case M_SRC2:
     case M_SRC:
+    case M_SRC2:
         val8 = (mode == M_SRC) ? opc : post;
         decodeModeReg(insn, out, val8);
         break;
-    case M_DST2:
     case M_DST:
+    case M_DST0:
+    case M_DST4:
         val8 = ((mode == M_DST) ? opc : post) >> 6;
         decodeModeReg(insn, out, val8);
         break;
-    case M_CNT2:
+    case M_CNT4:
     case M_XOP:
     case M_CNT:
-        val8 = (((mode == M_CNT2) ? post : opc) >> 6) & 0xF;
-        if (mode == M_CNT2 && val8 == 0) {
+        val8 = (((mode == M_CNT4) ? post : opc) >> 6) & 0xF;
+        if (mode == M_CNT4 && val8 == 0) {
             outRegName(out, REG_R0);
             break;
         }
@@ -120,7 +125,7 @@ void DisTms9900::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode) con
             val8 = 16;
         outDec(out, val8, 5);
         break;
-    case M_BIT2:
+    case M_BIT0:
         val8 = (post >> 6) & 0xF;
         outDec(out, val8, 4);
         break;
diff --git a/src/entry_tms9900.h b/src/entry_tms9900.h
index 0789f80f..458743a1 100644
--- a/src/entry_tms9900.h
+++ b/src/entry_tms9900.h
@@ -38,10 +38,11 @@ enum AddrMode : uint8_t {
     M_REL = 10,   // ---- ---- nnnn nnnn
     M_CRU = 11,   // ---- ---- nnnn nnnn
     M_RTWP = 12,  // ---- ---- ---- -nnn RTWP mode
-    M_DST2 = 13,  // 0100 DDdd dd-- ---- in 2nd word
-    M_CNT2 = 14,  // 0100 00cc cc-- ---- in 2nd word
-    M_BIT2 = 15,  // 0000 00bb bb-- ---- in 2nd word
-    M_SRC2 = 16,  // ---- ---- --SS ssss in 2nd word
+    M_SRC2 = 13,  // ---- ---- --SS ssss in 2nd word
+    M_DST0 = 14,  // 0000 DDdd dd-- ---- in 2nd word
+    M_DST4 = 15,  // 0100 DDdd dd-- ---- in 2nd word
+    M_BIT0 = 16,  // 0000 00bb bb-- ---- in 2nd word
+    M_CNT4 = 17,  // 0100 00cc cc-- ---- in 2nd word
     // Only for assembler.
     M_IREG = 17,  // Work Register Indirect Addressing: *Rn
     M_INCR = 18,  // Work Register Indirect Auto Increment Addressing: *Rn+
diff --git a/src/table_tms9900.cpp b/src/table_tms9900.cpp
index 43f6db27..88428f01 100644
--- a/src/table_tms9900.cpp
+++ b/src/table_tms9900.cpp
@@ -192,15 +192,15 @@ static constexpr uint8_t INDEX_TMS9995[] PROGMEM = {
 };
 
 static constexpr Entry TABLE_TMS99105[] PROGMEM = {
-    E2(0x001C, TEXT_SRAM, M_SRC2, M_CNT2),
-    E2(0x001D, TEXT_SLAM, M_SRC2, M_CNT2),
-    E2(0x0029, TEXT_SM,   M_SRC2, M_DST2),
-    E2(0x002A, TEXT_AM,   M_SRC2, M_DST2),
+    E2(0x001C, TEXT_SRAM, M_SRC2, M_CNT4),
+    E2(0x001D, TEXT_SLAM, M_SRC2, M_CNT4),
+    E2(0x0029, TEXT_SM,   M_SRC2, M_DST4),
+    E2(0x002A, TEXT_AM,   M_SRC2, M_DST4),
     E2(0x00B0, TEXT_BLSK, M_REG,  M_IMM),
     E1(0x0140, TEXT_BIND, M_SRC),
-    E2(0x0C09, TEXT_TMB,  M_SRC2, M_BIT2),
-    E2(0x0C0A, TEXT_TCMB, M_SRC2, M_BIT2),
-    E2(0x0C0B, TEXT_TSMB, M_SRC2, M_BIT2),
+    E2(0x0C09, TEXT_TMB,  M_SRC2, M_BIT0),
+    E2(0x0C0A, TEXT_TCMB, M_SRC2, M_BIT0),
+    E2(0x0C0B, TEXT_TSMB, M_SRC2, M_BIT0),
     E1(0x0100, TEXT_EVAD, M_SRC),
     E1(0x0380, TEXT_RTWP, M_RTWP),
     // Extra
@@ -222,6 +222,43 @@ static constexpr uint8_t INDEX_TMS99105[] PROGMEM = {
       6,  // TEXT_TMB
       8,  // TEXT_TSMB
 };
+
+static constexpr Entry TABLE_TMS99110[] PROGMEM = {
+    E0(0x0780, TEXT_LDS),
+    E0(0x07C0, TEXT_LDD),
+    E0(0x0C00, TEXT_CRI),
+    E0(0x0C02, TEXT_NEGR),
+    E0(0x0C04, TEXT_CRE),
+    E0(0x0C06, TEXT_CER),
+    E1(0x0C40, TEXT_AR,  M_SRC),
+    E1(0x0C80, TEXT_CIR, M_SRC),
+    E1(0x0CC0, TEXT_SR,  M_SRC),
+    E1(0x0D00, TEXT_MR,  M_SRC),
+    E1(0x0D40, TEXT_DR,  M_SRC),
+    E1(0x0D80, TEXT_LR,  M_SRC),
+    E1(0x0DC0, TEXT_STR, M_SRC),
+    E2(0x0301, TEXT_CR,  M_SRC2, M_DST0),
+    E2(0x0302, TEXT_MM,  M_SRC2, M_DST0),
+};
+
+static constexpr uint8_t INDEX_TMS99110[] PROGMEM = {
+      6,  // TEXT_AR
+      5,  // TEXT_CER
+      7,  // TEXT_CIR
+     13,  // TEXT_CR
+      4,  // TEXT_CRE
+      2,  // TEXT_CRI
+     10,  // TEXT_DR
+      1,  // TEXT_LDD
+      0,  // TEXT_LDS
+     11,  // TEXT_LR
+     14,  // TEXT_MM
+      9,  // TEXT_MR
+      3,  // TEXT_NEGR
+      8,  // TEXT_SR
+     12,  // TEXT_STR
+};
+
 // clang-format on
 
 using EntryPage = entry::TableBase<Entry>;
@@ -241,6 +278,13 @@ static constexpr EntryPage TMS99105_PAGES[] PROGMEM = {
         {ARRAY_RANGE(TABLE_TMS9995), ARRAY_RANGE(INDEX_TMS9995)},
 };
 
+static constexpr EntryPage TMS99110_PAGES[] PROGMEM = {
+        {ARRAY_RANGE(TABLE_TMS99105), ARRAY_RANGE(INDEX_TMS99105)},
+        {ARRAY_RANGE(TABLE_TMS9900), ARRAY_RANGE(INDEX_TMS9900)},
+        {ARRAY_RANGE(TABLE_TMS9995), ARRAY_RANGE(INDEX_TMS9995)},
+        {ARRAY_RANGE(TABLE_TMS99110), ARRAY_RANGE(INDEX_TMS99110)},
+};
+
 using Cpu = entry::CpuBase<CpuType, EntryPage>;
 
 static constexpr Cpu CPU_TABLE[] PROGMEM = {
@@ -248,6 +292,7 @@ static constexpr Cpu CPU_TABLE[] PROGMEM = {
         {TMS9980, TEXT_CPU_9980, ARRAY_RANGE(TMS9900_PAGES)},
         {TMS9995, TEXT_CPU_9995, ARRAY_RANGE(TMS9995_PAGES)},
         {TMS99105, TEXT_CPU_99105, ARRAY_RANGE(TMS99105_PAGES)},
+        {TMS99110, TEXT_CPU_99110, ARRAY_RANGE(TMS99110_PAGES)},
 };
 
 static const Cpu *cpu(CpuType cpuType) {
@@ -269,13 +314,14 @@ static bool acceptMode(AddrMode opr, AddrMode table) {
     if (opr == table)
         return true;
     if (opr == M_IREG || opr == M_INCR || opr == M_SYBL || opr == M_INDX)
-        return table == M_SRC || table == M_DST || table == M_SRC2 || table == M_DST2;
+        return table == M_SRC || table == M_DST || table == M_SRC2 || table == M_DST0 ||
+               table == M_DST4;
     if (opr == M_REG)
-        return table == M_SRC || table == M_DST || table == M_SRC2 || table == M_DST2 ||
-               table == M_DREG || table == M_SCNT || table == M_CNT2;
+        return table == M_SRC || table == M_DST || table == M_SRC2 || table == M_DST0 ||
+               table == M_DST4 || table == M_DREG || table == M_SCNT || table == M_CNT4;
     if (opr == M_IMM)
-        return table == M_REL || table == M_SCNT || table == M_CNT || table == M_CNT2 ||
-               table == M_CRU || table == M_BIT2 || table == M_XOP || table == M_RTWP;
+        return table == M_REL || table == M_SCNT || table == M_CNT || table == M_CNT4 ||
+               table == M_CRU || table == M_BIT0 || table == M_XOP || table == M_RTWP;
     return false;
 }
 
diff --git a/src/text_tms9900.cpp b/src/text_tms9900.cpp
index a8a41676..9ea2f966 100644
--- a/src/text_tms9900.cpp
+++ b/src/text_tms9900.cpp
@@ -21,11 +21,12 @@ namespace text {
 namespace tms9900 {
 
 // clang-format off
-constexpr char TEXT_TMS9900_LIST[] PROGMEM = "TMS9900, TMS9980, TMS9995, TMS99105";
+constexpr char TEXT_TMS9900_LIST[] PROGMEM = "TMS9900, TMS9980, TMS9995, TMS99105, TMS99110";
 constexpr char TEXT_CPU_9900[]  PROGMEM = "9900";
 constexpr char TEXT_CPU_9980[]  PROGMEM = "9980";
 constexpr char TEXT_CPU_9995[]  PROGMEM = "9995";
 constexpr char TEXT_CPU_99105[] PROGMEM = "99105";
+constexpr char TEXT_CPU_99110[] PROGMEM = "99110";
 
 // TMS9900
 // constexpr char TEXT_A[]    PROGMEM = "A";
@@ -115,8 +116,25 @@ constexpr char TEXT_SRAM[] PROGMEM = "SRAM";
 constexpr char TEXT_TCMB[] PROGMEM = "TCMB";
 constexpr char TEXT_TMB[]  PROGMEM = "TMB";
 constexpr char TEXT_TSMB[] PROGMEM = "TSMB";
-// clang-format on
 
+// TMS99110
+constexpr char TEXT_AR[]   PROGMEM = "AR";
+constexpr char TEXT_CER[]  PROGMEM = "CER";
+constexpr char TEXT_CIR[]  PROGMEM = "CIR";
+constexpr char TEXT_CR[]   PROGMEM = "CR";
+constexpr char TEXT_CRE[]  PROGMEM = "CRE";
+constexpr char TEXT_CRI[]  PROGMEM = "CRI";
+constexpr char TEXT_DR[]   PROGMEM = "DR";
+// constexpr char TEXT_LDD[]  PROGMEM = "LDD";
+// constexpr char TEXT_LDS[]  PROGMEM = "LDS";
+// constexpr char TEXT_LR[]   PROGMEM = "LR";
+constexpr char TEXT_MM[]   PROGMEM = "MM";
+constexpr char TEXT_MR[]   PROGMEM = "MR";
+constexpr char TEXT_NEGR[] PROGMEM = "NEGR";
+// constexpr char TEXT_SR[]   PROGMEM = "SR";
+// constexpr char TEXT_STR[]  PROGMEM = "STR";
+
+// clang-format on
 }  // namespace tms9900
 }  // namespace text
 }  // namespace libasm
diff --git a/src/text_tms9900.h b/src/text_tms9900.h
index 7795066f..58ce0a03 100644
--- a/src/text_tms9900.h
+++ b/src/text_tms9900.h
@@ -29,6 +29,7 @@ extern const char TEXT_CPU_9900[]  PROGMEM;
 extern const char TEXT_CPU_9980[]  PROGMEM;
 extern const char TEXT_CPU_9995[]  PROGMEM;
 extern const char TEXT_CPU_99105[] PROGMEM;
+extern const char TEXT_CPU_99110[] PROGMEM;
 
 // TMS9900
 using common::TEXT_A;
@@ -118,8 +119,25 @@ extern const char TEXT_SRAM[] PROGMEM;
 extern const char TEXT_TCMB[] PROGMEM;
 extern const char TEXT_TMB[]  PROGMEM;
 extern const char TEXT_TSMB[] PROGMEM;
-// clang-format on
 
+// TMS99110
+extern const char TEXT_AR[]   PROGMEM;
+extern const char TEXT_CER[]  PROGMEM;
+extern const char TEXT_CIR[]  PROGMEM;
+extern const char TEXT_CR[]   PROGMEM;
+extern const char TEXT_CRE[]  PROGMEM;
+extern const char TEXT_CRI[]  PROGMEM;
+extern const char TEXT_DR[]   PROGMEM;
+using common::TEXT_LDD;
+using common::TEXT_LDS;
+using common::TEXT_LR;
+extern const char TEXT_MM[]   PROGMEM;
+extern const char TEXT_MR[]   PROGMEM;
+extern const char TEXT_NEGR[] PROGMEM;
+using common::TEXT_SR;
+using common::TEXT_STR;
+
+// clang-format on
 }  // namespace tms9900
 }  // namespace text
 }  // namespace libasm
diff --git a/test/autogen/gen_tms99110.asm b/test/autogen/gen_tms99110.asm
new file mode 100644
index 00000000..3291574b
--- /dev/null
+++ b/test/autogen/gen_tms99110.asm
@@ -0,0 +1,679 @@
+;;; AUTO GENERATED FILE
+;;; generated by: gen_tms9900 -u -C TMS99110 -o gen_tms99110.asm -l gen_tms99110.lst
+      CPU   TMS99110
+      ORG   0100H
+      SRAM  R0, R0
+      SRAM  *R0, R0
+      SRAM  @4122H, R0
+      SRAM  @4122H(R1), R0
+      SRAM  *R0+, R0
+      SRAM  R0, 1
+      SRAM  *R0, 1
+      SRAM  @4162H, 1
+      SRAM  @4162H(R1), 1
+      SRAM  *R0+, 1
+      SLAM  R0, R0
+      SLAM  *R0, R0
+      SLAM  @4122H, R0
+      SLAM  @4122H(R1), R0
+      SLAM  *R0+, R0
+      SLAM  R0, 1
+      SLAM  *R0, 1
+      SLAM  @4162H, 1
+      SLAM  @4162H(R1), 1
+      SLAM  *R0+, 1
+      SM    R0, R0
+      SM    *R0, R0
+      SM    @4122H, R0
+      SM    @4122H(R1), R0
+      SM    *R0+, R0
+      SM    R0, *R0
+      SM    *R0, *R0
+      SM    @4522H, *R0
+      SM    @4522H(R1), *R0
+      SM    *R0+, *R0
+      SM    R0, @4902H
+      SM    *R0, @4912H
+      SM    @4922H, @4A24H
+      SM    @4922H(R1), @4A24H
+      SM    *R0+, @4932H
+      SM    R0, @4941H(R1)
+      SM    *R0, @4951H(R1)
+      SM    @4962H, @4A63H(R1)
+      SM    @4962H(R1), @4A63H(R1)
+      SM    *R0+, @4971H(R1)
+      SM    R0, *R0+
+      SM    *R0, *R0+
+      SM    @4D22H, *R0+
+      SM    @4D22H(R1), *R0+
+      SM    *R0+, *R0+
+      AM    R0, R0
+      AM    *R0, R0
+      AM    @4122H, R0
+      AM    @4122H(R1), R0
+      AM    *R0+, R0
+      AM    R0, *R0
+      AM    *R0, *R0
+      AM    @4522H, *R0
+      AM    @4522H(R1), *R0
+      AM    *R0+, *R0
+      AM    R0, @4902H
+      AM    *R0, @4912H
+      AM    @4922H, @4A24H
+      AM    @4922H(R1), @4A24H
+      AM    *R0+, @4932H
+      AM    R0, @4941H(R1)
+      AM    *R0, @4951H(R1)
+      AM    @4962H, @4A63H(R1)
+      AM    @4962H(R1), @4A63H(R1)
+      AM    *R0+, @4971H(R1)
+      AM    R0, *R0+
+      AM    *R0, *R0+
+      AM    @4D22H, *R0+
+      AM    @4D22H(R1), *R0+
+      AM    *R0+, *R0+
+      LST   R0
+      LWP   R0
+      BLSK  R0, 01B1H
+      EVAD  R0
+      EVAD  *R0
+      EVAD  @0222H
+      EVAD  @0222H(R1)
+      EVAD  *R0+
+      BIND  R0
+      BIND  *R0
+      BIND  @0262H
+      BIND  @0262H(R1)
+      BIND  *R0+
+      DIVS  R0
+      DIVS  *R0
+      DIVS  @02A2H
+      DIVS  @02A2H(R1)
+      DIVS  *R0+
+      MPYS  R0
+      MPYS  *R0
+      MPYS  @02E2H
+      MPYS  @02E2H(R1)
+      MPYS  *R0+
+      LI    R0, 0301H
+      AI    R0, 0321H
+      ANDI  R0, 0341H
+      ORI   R0, 0361H
+      CI    R0, 0381H
+      STWP  R0
+      STST  R0
+      LWPI  03E1H
+      LIMI  0401H
+      CR    R2, *R0
+      CR    *R0, *R0
+      CR    @0522H, *R0
+      CR    @0522H(R1), *R0
+      CR    *R0+, *R0
+      CR    R0, @0902H
+      CR    *R0, @0912H
+      CR    @0922H, @0A24H
+      CR    @0922H(R1), @0A24H
+      CR    *R0+, @0932H
+      CR    R0, @0941H(R1)
+      CR    *R0, @0951H(R1)
+      CR    @0962H, @0A63H(R1)
+      CR    @0962H(R1), @0A63H(R1)
+      CR    *R0+, @0971H(R1)
+      CR    R0, *R0+
+      CR    *R0, *R0+
+      CR    @0D22H, *R0+
+      CR    @0D22H(R1), *R0+
+      CR    *R0+, *R0+
+      CR    R0, R0
+      CR    *R0, R0
+      CR    @0122H, R0
+      CR    @0122H(R1), R0
+      CR    *R0+, R0
+      MM    R3, *R0
+      MM    *R0, *R0
+      MM    @0522H, *R0
+      MM    @0522H(R1), *R0
+      MM    *R0+, *R0
+      MM    R0, @0902H
+      MM    *R0, @0912H
+      MM    @0922H, @0A24H
+      MM    @0922H(R1), @0A24H
+      MM    *R0+, @0932H
+      MM    R0, @0941H(R1)
+      MM    *R0, @0951H(R1)
+      MM    @0962H, @0A63H(R1)
+      MM    @0962H(R1), @0A63H(R1)
+      MM    *R0+, @0971H(R1)
+      MM    R0, *R0+
+      MM    *R0, *R0+
+      MM    @0D22H, *R0+
+      MM    @0D22H(R1), *R0+
+      MM    *R0+, *R0+
+      MM    R0, R0
+      MM    *R0, R0
+      MM    @0122H, R0
+      MM    @0122H(R1), R0
+      MM    *R0+, R0
+      IDLE
+      RSET
+      RTWP
+      RTWP  1
+      CKON
+      CKOF
+      LREX
+      BLWP  R0
+      BLWP  *R0
+      BLWP  @0522H
+      BLWP  @0522H(R1)
+      BLWP  *R0+
+      B     R0
+      B     *R0
+      B     @0562H
+      B     @0562H(R1)
+      B     *R0+
+      X     R0
+      X     *R0
+      X     @05A2H
+      X     @05A2H(R1)
+      X     *R0+
+      CLR   R0
+      CLR   *R0
+      CLR   @05E2H
+      CLR   @05E2H(R1)
+      CLR   *R0+
+      NEG   R0
+      NEG   *R0
+      NEG   @0622H
+      NEG   @0622H(R1)
+      NEG   *R0+
+      INV   R0
+      INV   *R0
+      INV   @0662H
+      INV   @0662H(R1)
+      INV   *R0+
+      INC   R0
+      INC   *R0
+      INC   @06A2H
+      INC   @06A2H(R1)
+      INC   *R0+
+      INCT  R0
+      INCT  *R0
+      INCT  @06E2H
+      INCT  @06E2H(R1)
+      INCT  *R0+
+      DEC   R0
+      DEC   *R0
+      DEC   @0722H
+      DEC   @0722H(R1)
+      DEC   *R0+
+      DECT  R0
+      DECT  *R0
+      DECT  @0762H
+      DECT  @0762H(R1)
+      DECT  *R0+
+      BL    R0
+      BL    *R0
+      BL    @07A2H
+      BL    @07A2H(R1)
+      BL    *R0+
+      SWPB  R0
+      SWPB  *R0
+      SWPB  @07E2H
+      SWPB  @07E2H(R1)
+      SWPB  *R0+
+      SETO  R0
+      SETO  *R0
+      SETO  @0822H
+      SETO  @0822H(R1)
+      SETO  *R0+
+      ABS   R0
+      ABS   *R0
+      ABS   @0862H
+      ABS   @0862H(R1)
+      ABS   *R0+
+      LDS
+      LDD
+      SRA   R0, R0
+      SRA   R0, 1
+      SRL   R0, R0
+      SRL   R0, 1
+      SLA   R0, R0
+      SLA   R0, 1
+      SRC   R0, R0
+      SRC   R0, 1
+      CRI
+      NEGR
+      CRE
+      CER
+      TMB   R0, 0
+      TMB   *R0, 0
+      TMB   @0122H, 0
+      TMB   @0122H(R1), 0
+      TCMB  R0, 0
+      TCMB  *R0, 0
+      TCMB  @0122H, 0
+      TCMB  @0122H(R1), 0
+      TSMB  R0, 0
+      TSMB  *R0, 0
+      TSMB  @0122H, 0
+      TSMB  @0122H(R1), 0
+      AR    R0
+      AR    *R0
+      AR    @0D62H
+      AR    @0D62H(R1)
+      AR    *R0+
+      CIR   R0
+      CIR   *R0
+      CIR   @0DA2H
+      CIR   @0DA2H(R1)
+      CIR   *R0+
+      SR    R0
+      SR    *R0
+      SR    @0DE2H
+      SR    @0DE2H(R1)
+      SR    *R0+
+      MR    R0
+      MR    *R0
+      MR    @0E22H
+      MR    @0E22H(R1)
+      MR    *R0+
+      DR    R0
+      DR    *R0
+      DR    @0E62H
+      DR    @0E62H(R1)
+      DR    *R0+
+      LR    R0
+      LR    *R0
+      LR    @0EA2H
+      LR    @0EA2H(R1)
+      LR    *R0+
+      STR   R0
+      STR   *R0
+      STR   @0EE2H
+      STR   @0EE2H(R1)
+      STR   *R0+
+      JMP   $+2
+      JMP   $-254
+      JMP   $
+      JLT   $+2
+      JLT   $-254
+      JLT   $
+      JLE   $+2
+      JLE   $-254
+      JLE   $
+      JEQ   $+2
+      JEQ   $-254
+      JEQ   $
+      JHE   $+2
+      JHE   $-254
+      JHE   $
+      JGT   $+2
+      JGT   $-254
+      JGT   $
+      JNE   $+2
+      JNE   $-254
+      JNE   $
+      JNC   $+2
+      JNC   $-254
+      JNC   $
+      JOC   $+2
+      JOC   $-254
+      JOC   $
+      JNO   $+2
+      JNO   $-254
+      JNO   $
+      JL    $+2
+      JL    $-254
+      JL    $
+      JH    $+2
+      JH    $-254
+      JH    $
+      JOP   $+2
+      JOP   $-254
+      JOP   $
+      SBO   0
+      SBO   -128
+      SBZ   0
+      SBZ   -128
+      TB    0
+      TB    -128
+      COC   R0, R0
+      COC   *R0, R0
+      COC   @2122H, R0
+      COC   @2122H(R1), R0
+      COC   *R0+, R0
+      CZC   R0, R0
+      CZC   *R0, R0
+      CZC   @2522H, R0
+      CZC   @2522H(R1), R0
+      CZC   *R0+, R0
+      XOR   R0, R0
+      XOR   *R0, R0
+      XOR   @2922H, R0
+      XOR   @2922H(R1), R0
+      XOR   *R0+, R0
+      XOP   R0, 0
+      XOP   *R0, 0
+      XOP   @2D22H, 0
+      XOP   @2D22H(R1), 0
+      XOP   *R0+, 0
+      LDCR  R0, 16
+      LDCR  *R0, 16
+      LDCR  @3122H, 16
+      LDCR  @3122H(R1), 16
+      LDCR  *R0+, 16
+      STCR  R0, 16
+      STCR  *R0, 16
+      STCR  @3522H, 16
+      STCR  @3522H(R1), 16
+      STCR  *R0+, 16
+      MPY   R0, R0
+      MPY   *R0, R0
+      MPY   @3922H, R0
+      MPY   @3922H(R1), R0
+      MPY   *R0+, R0
+      DIV   R0, R0
+      DIV   *R0, R0
+      DIV   @3D22H, R0
+      DIV   @3D22H(R1), R0
+      DIV   *R0+, R0
+      SZC   R0, R0
+      SZC   *R0, R0
+      SZC   @4122H, R0
+      SZC   @4122H(R1), R0
+      SZC   *R0+, R0
+      SZC   R0, *R0
+      SZC   *R0, *R0
+      SZC   @4522H, *R0
+      SZC   @4522H(R1), *R0
+      SZC   *R0+, *R0
+      SZC   R0, @4902H
+      SZC   *R0, @4912H
+      SZC   @4922H, @4A24H
+      SZC   @4922H(R1), @4A24H
+      SZC   *R0+, @4932H
+      SZC   R0, @4941H(R1)
+      SZC   *R0, @4951H(R1)
+      SZC   @4962H, @4A63H(R1)
+      SZC   @4962H(R1), @4A63H(R1)
+      SZC   *R0+, @4971H(R1)
+      SZC   R0, *R0+
+      SZC   *R0, *R0+
+      SZC   @4D22H, *R0+
+      SZC   @4D22H(R1), *R0+
+      SZC   *R0+, *R0+
+      SZCB  R0, R0
+      SZCB  *R0, R0
+      SZCB  @5121H, R0
+      SZCB  @5122H(R1), R0
+      SZCB  *R0+, R0
+      SZCB  R0, *R0
+      SZCB  *R0, *R0
+      SZCB  @5521H, *R0
+      SZCB  @5522H(R1), *R0
+      SZCB  *R0+, *R0
+      SZCB  R0, @5901H
+      SZCB  *R0, @5911H
+      SZCB  @5921H, @5A22H
+      SZCB  @5922H(R1), @5A23H
+      SZCB  *R0+, @5931H
+      SZCB  R0, @5941H(R1)
+      SZCB  *R0, @5951H(R1)
+      SZCB  @5961H, @5A62H(R1)
+      SZCB  @5962H(R1), @5A63H(R1)
+      SZCB  *R0+, @5971H(R1)
+      SZCB  R0, *R0+
+      SZCB  *R0, *R0+
+      SZCB  @5D21H, *R0+
+      SZCB  @5D22H(R1), *R0+
+      SZCB  *R0+, *R0+
+      S     R0, R0
+      S     *R0, R0
+      S     @6122H, R0
+      S     @6122H(R1), R0
+      S     *R0+, R0
+      S     R0, *R0
+      S     *R0, *R0
+      S     @6522H, *R0
+      S     @6522H(R1), *R0
+      S     *R0+, *R0
+      S     R0, @6902H
+      S     *R0, @6912H
+      S     @6922H, @6A24H
+      S     @6922H(R1), @6A24H
+      S     *R0+, @6932H
+      S     R0, @6941H(R1)
+      S     *R0, @6951H(R1)
+      S     @6962H, @6A63H(R1)
+      S     @6962H(R1), @6A63H(R1)
+      S     *R0+, @6971H(R1)
+      S     R0, *R0+
+      S     *R0, *R0+
+      S     @6D22H, *R0+
+      S     @6D22H(R1), *R0+
+      S     *R0+, *R0+
+      SB    R0, R0
+      SB    *R0, R0
+      SB    @7121H, R0
+      SB    @7122H(R1), R0
+      SB    *R0+, R0
+      SB    R0, *R0
+      SB    *R0, *R0
+      SB    @7521H, *R0
+      SB    @7522H(R1), *R0
+      SB    *R0+, *R0
+      SB    R0, @7901H
+      SB    *R0, @7911H
+      SB    @7921H, @7A22H
+      SB    @7922H(R1), @7A23H
+      SB    *R0+, @7931H
+      SB    R0, @7941H(R1)
+      SB    *R0, @7951H(R1)
+      SB    @7961H, @7A62H(R1)
+      SB    @7962H(R1), @7A63H(R1)
+      SB    *R0+, @7971H(R1)
+      SB    R0, *R0+
+      SB    *R0, *R0+
+      SB    @7D21H, *R0+
+      SB    @7D22H(R1), *R0+
+      SB    *R0+, *R0+
+      C     R0, R0
+      C     *R0, R0
+      C     @8122H, R0
+      C     @8122H(R1), R0
+      C     *R0+, R0
+      C     R0, *R0
+      C     *R0, *R0
+      C     @8522H, *R0
+      C     @8522H(R1), *R0
+      C     *R0+, *R0
+      C     R0, @8902H
+      C     *R0, @8912H
+      C     @8922H, @8A24H
+      C     @8922H(R1), @8A24H
+      C     *R0+, @8932H
+      C     R0, @8941H(R1)
+      C     *R0, @8951H(R1)
+      C     @8962H, @8A63H(R1)
+      C     @8962H(R1), @8A63H(R1)
+      C     *R0+, @8971H(R1)
+      C     R0, *R0+
+      C     *R0, *R0+
+      C     @8D22H, *R0+
+      C     @8D22H(R1), *R0+
+      C     *R0+, *R0+
+      CB    R0, R0
+      CB    *R0, R0
+      CB    @9121H, R0
+      CB    @9122H(R1), R0
+      CB    *R0+, R0
+      CB    R0, *R0
+      CB    *R0, *R0
+      CB    @9521H, *R0
+      CB    @9522H(R1), *R0
+      CB    *R0+, *R0
+      CB    R0, @9901H
+      CB    *R0, @9911H
+      CB    @9921H, @9A22H
+      CB    @9922H(R1), @9A23H
+      CB    *R0+, @9931H
+      CB    R0, @9941H(R1)
+      CB    *R0, @9951H(R1)
+      CB    @9961H, @9A62H(R1)
+      CB    @9962H(R1), @9A63H(R1)
+      CB    *R0+, @9971H(R1)
+      CB    R0, *R0+
+      CB    *R0, *R0+
+      CB    @9D21H, *R0+
+      CB    @9D22H(R1), *R0+
+      CB    *R0+, *R0+
+      A     R0, R0
+      A     *R0, R0
+      A     @0A122H, R0
+      A     @0A122H(R1), R0
+      A     *R0+, R0
+      A     R0, *R0
+      A     *R0, *R0
+      A     @0A522H, *R0
+      A     @0A522H(R1), *R0
+      A     *R0+, *R0
+      A     R0, @0A902H
+      A     *R0, @0A912H
+      A     @0A922H, @0AA24H
+      A     @0A922H(R1), @0AA24H
+      A     *R0+, @0A932H
+      A     R0, @0A941H(R1)
+      A     *R0, @0A951H(R1)
+      A     @0A962H, @0AA63H(R1)
+      A     @0A962H(R1), @0AA63H(R1)
+      A     *R0+, @0A971H(R1)
+      A     R0, *R0+
+      A     *R0, *R0+
+      A     @0AD22H, *R0+
+      A     @0AD22H(R1), *R0+
+      A     *R0+, *R0+
+      AB    R0, R0
+      AB    *R0, R0
+      AB    @0B121H, R0
+      AB    @0B122H(R1), R0
+      AB    *R0+, R0
+      AB    R0, *R0
+      AB    *R0, *R0
+      AB    @0B521H, *R0
+      AB    @0B522H(R1), *R0
+      AB    *R0+, *R0
+      AB    R0, @0B901H
+      AB    *R0, @0B911H
+      AB    @0B921H, @0BA22H
+      AB    @0B922H(R1), @0BA23H
+      AB    *R0+, @0B931H
+      AB    R0, @0B941H(R1)
+      AB    *R0, @0B951H(R1)
+      AB    @0B961H, @0BA62H(R1)
+      AB    @0B962H(R1), @0BA63H(R1)
+      AB    *R0+, @0B971H(R1)
+      AB    R0, *R0+
+      AB    *R0, *R0+
+      AB    @0BD21H, *R0+
+      AB    @0BD22H(R1), *R0+
+      AB    *R0+, *R0+
+      MOV   R0, R0
+      MOV   *R0, R0
+      MOV   @0C122H, R0
+      MOV   @0C122H(R1), R0
+      MOV   *R0+, R0
+      MOV   R0, *R0
+      MOV   *R0, *R0
+      MOV   @0C522H, *R0
+      MOV   @0C522H(R1), *R0
+      MOV   *R0+, *R0
+      MOV   R0, @0C902H
+      MOV   *R0, @0C912H
+      MOV   @0C922H, @0CA24H
+      MOV   @0C922H(R1), @0CA24H
+      MOV   *R0+, @0C932H
+      MOV   R0, @0C941H(R1)
+      MOV   *R0, @0C951H(R1)
+      MOV   @0C962H, @0CA63H(R1)
+      MOV   @0C962H(R1), @0CA63H(R1)
+      MOV   *R0+, @0C971H(R1)
+      MOV   R0, *R0+
+      MOV   *R0, *R0+
+      MOV   @0CD22H, *R0+
+      MOV   @0CD22H(R1), *R0+
+      MOV   *R0+, *R0+
+      MOVB  R0, R0
+      MOVB  *R0, R0
+      MOVB  @0D121H, R0
+      MOVB  @0D122H(R1), R0
+      MOVB  *R0+, R0
+      MOVB  R0, *R0
+      MOVB  *R0, *R0
+      MOVB  @0D521H, *R0
+      MOVB  @0D522H(R1), *R0
+      MOVB  *R0+, *R0
+      MOVB  R0, @0D901H
+      MOVB  *R0, @0D911H
+      MOVB  @0D921H, @0DA22H
+      MOVB  @0D922H(R1), @0DA23H
+      MOVB  *R0+, @0D931H
+      MOVB  R0, @0D941H(R1)
+      MOVB  *R0, @0D951H(R1)
+      MOVB  @0D961H, @0DA62H(R1)
+      MOVB  @0D962H(R1), @0DA63H(R1)
+      MOVB  *R0+, @0D971H(R1)
+      MOVB  R0, *R0+
+      MOVB  *R0, *R0+
+      MOVB  @0DD21H, *R0+
+      MOVB  @0DD22H(R1), *R0+
+      MOVB  *R0+, *R0+
+      SOC   R0, R0
+      SOC   *R0, R0
+      SOC   @0E122H, R0
+      SOC   @0E122H(R1), R0
+      SOC   *R0+, R0
+      SOC   R0, *R0
+      SOC   *R0, *R0
+      SOC   @0E522H, *R0
+      SOC   @0E522H(R1), *R0
+      SOC   *R0+, *R0
+      SOC   R0, @0E902H
+      SOC   *R0, @0E912H
+      SOC   @0E922H, @0EA24H
+      SOC   @0E922H(R1), @0EA24H
+      SOC   *R0+, @0E932H
+      SOC   R0, @0E941H(R1)
+      SOC   *R0, @0E951H(R1)
+      SOC   @0E962H, @0EA63H(R1)
+      SOC   @0E962H(R1), @0EA63H(R1)
+      SOC   *R0+, @0E971H(R1)
+      SOC   R0, *R0+
+      SOC   *R0, *R0+
+      SOC   @0ED22H, *R0+
+      SOC   @0ED22H(R1), *R0+
+      SOC   *R0+, *R0+
+      SOCB  R0, R0
+      SOCB  *R0, R0
+      SOCB  @0F121H, R0
+      SOCB  @0F122H(R1), R0
+      SOCB  *R0+, R0
+      SOCB  R0, *R0
+      SOCB  *R0, *R0
+      SOCB  @0F521H, *R0
+      SOCB  @0F522H(R1), *R0
+      SOCB  *R0+, *R0
+      SOCB  R0, @0F901H
+      SOCB  *R0, @0F911H
+      SOCB  @0F921H, @0FA22H
+      SOCB  @0F922H(R1), @0FA23H
+      SOCB  *R0+, @0F931H
+      SOCB  R0, @0F941H(R1)
+      SOCB  *R0, @0F951H(R1)
+      SOCB  @0F961H, @0FA62H(R1)
+      SOCB  @0F962H(R1), @0FA63H(R1)
+      SOCB  *R0+, @0F971H(R1)
+      SOCB  R0, *R0+
+      SOCB  *R0, *R0+
+      SOCB  @0FD21H, *R0+
+      SOCB  @0FD22H(R1), *R0+
+      SOCB  *R0+, *R0+
diff --git a/test/reference/test_tms99110.asm b/test/reference/test_tms99110.asm
new file mode 100644
index 00000000..29cb7997
--- /dev/null
+++ b/test/reference/test_tms99110.asm
@@ -0,0 +1,29 @@
+;;; Copyright 2024 Tadashi G. Takaoka
+;;;
+;;; Licensed under the Apache License, Version 2.0 (the "License");
+;;; you may not use this file except in compliance with the License.
+;;; You may obtain a copy of the License at
+;;;
+;;;     http://www.apache.org/licenses/LICENSE-2.0
+;;;
+;;; Unless required by applicable law or agreed to in writing, software
+;;; distributed under the License is distributed on an "AS IS" BASIS,
+;;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;;; See the License for the specific language governing permissions and
+;;; limitations under the License.
+
+        cpu     TMS99110
+        org     0100h
+        include "test_tms9900.inc"
+        align   32
+        include "test_tms9995.inc"
+        align   32
+        include "test_tms99105.inc"
+        align   32
+        include "test_tms99110.inc"
+        end
+
+;;; Local Variables:
+;;; mode: asm
+;;; End:
+;;; vim: set ft=asm:
diff --git a/test/reference/test_tms99110.hex b/test/reference/test_tms99110.hex
new file mode 100644
index 00000000..13c51fc2
--- /dev/null
+++ b/test/reference/test_tms99110.hex
@@ -0,0 +1,21 @@
+:100100000203040502220333024402550266027709
+:100110000288029902E002F002AA02CC0300032046
+:1001200003400360038003A003C003E0040504440C
+:10013000048804CC05060544058805CC060706445A
+:10014000068806CC07080744080909AB0ABC0BCD92
+:10015000101111121213131414151516161717185F
+:100160001819191A1A1B1B1C1C1D1D1E1E1F1F20CF
+:10017000202122232425262728292A2B2C2D2E2F07
+:100180003031343538393C3D456789AB567867891D
+:10019000789ABCDE89ABCDEF01239ABCDEF0ABCD03
+:0E01A000EF01BCDECDEF0123DEF0EF01F01227
+:0801C00000880099018801CCC0
+:1001E000001C43EF0123001D400B00294D74002A21
+:1001F0004AEF0123CDEF00B34567016122230105DA
+:100200000381038203840C0901EF01230C0A00001F
+:040210000C0B03D2FE
+:100220000301096D123434560302096D1234345639
+:100230000780C13307C0C585078007C0CD330C00D8
+:100240000C020C040C060C420C930CE012340D242E
+:0802500012340D750D860DD767
+:00000001FF
diff --git a/test/reference/test_tms99110.inc b/test/reference/test_tms99110.inc
new file mode 100644
index 00000000..a83d62c5
--- /dev/null
+++ b/test/reference/test_tms99110.inc
@@ -0,0 +1,42 @@
+;;; Copyright 2024 Tadashi G. Takaoka
+;;;
+;;; Licensed under the Apache License, Version 2.0 (the "License");
+;;; you may not use this file except in compliance with the License.
+;;; You may obtain a copy of the License at
+;;;
+;;;     http://www.apache.org/licenses/LICENSE-2.0
+;;;
+;;; Unless required by applicable law or agreed to in writing, software
+;;; distributed under the License is distributed on an "AS IS" BASIS,
+;;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;;; See the License for the specific language governing permissions and
+;;; limitations under the License.
+
+        cr      @1234h(r13), @3456h(r5)
+        mm      @1234h(r13), @3456h(r5)
+
+        lds
+        mov     *r3+, r4
+        ldd
+        mov     r5, *r6
+        lds
+        ldd
+        mov     *r3+, *r4+
+
+        cri
+        negr
+        cre
+        cer
+
+        ar      r2
+        cir     *r3
+        sr      @1234h
+        mr      @1234h(r4)
+        dr      *r5+
+        lr      r6
+        str     *r7
+
+;;; Local Variables:
+;;; mode: asm
+;;; End:
+;;; vim: set ft=asm:
diff --git a/test/test_asm_tms9900.cpp b/test/test_asm_tms9900.cpp
index cc5c3d01..00f44a5d 100644
--- a/test/test_asm_tms9900.cpp
+++ b/test/test_asm_tms9900.cpp
@@ -24,12 +24,16 @@ using namespace libasm::test;
 AsmTms9900 as9900;
 Assembler &assembler(as9900);
 
-static bool is99105() {
-    return strcmp_P("99105", assembler.config().cpu_P()) == 0;
+static bool is99110() {
+    return strcmp_P("99110", assembler.config().cpu_P()) == 0;
+}
+
+static bool is991xx() {
+    return strcmp_P("99105", assembler.config().cpu_P()) == 0 || is99110();
 }
 
 static bool is9995() {
-    return strcmp_P("9995", assembler.config().cpu_P()) == 0 || is99105();
+    return strcmp_P("9995", assembler.config().cpu_P()) == 0 || is991xx();
 }
 
 static bool is9980() {
@@ -79,8 +83,8 @@ static void test_inh() {
     TEST("CKOF", 0x03C0);
     TEST("LREX", 0x03E0);
 
-    if (is99105()) {
-        // TMS99105
+    if (is991xx()) {
+        // TMS99105, TMS99110
         TEST("RTWP 0", 0x0380);
         TEST("RTWP 1", 0x0381);
         TEST("RTWP 2", 0x0382);
@@ -90,6 +94,21 @@ static void test_inh() {
         COMM("RTWP 0", "0", 0x0380);
         COMM("RTWP 1", "1", 0x0380);
     }
+    if (is99110()) {
+        TEST("LDS",  0x0780);
+        TEST("LDD",  0x07C0);
+        TEST("CRI",  0x0C00);
+        TEST("NEGR", 0x0C02);
+        TEST("CRE",  0x0C04);
+        TEST("CER",  0x0C06);
+    } else {
+        ERUI("LDS");
+        ERUI("LDD");
+        ERUI("CRI");
+        ERUI("NEGR");
+        ERUI("CRE");
+        ERUI("CER");
+    }
 }
 
 static void test_imm() {
@@ -108,7 +127,7 @@ static void test_reg() {
     TEST("STST R15", 0x02CF);
 
     if (is9995()) {
-        // TMS9995
+        // TMS9995, TMS99105, TMS99110
         TEST("LST R0", 0x0080);
         TEST("LWP R1", 0x0091);
     } else {
@@ -132,8 +151,8 @@ static void test_reg_imm() {
 
     TEST("LI R2,sym1234", 0x0202, 0x1234);
 
-    if (is99105()) {
-        // TMS99105
+    if (is991xx()) {
+        // TMS99105, TMS99110
         TEST("BLSK R3,>4567",   0x00B3, 0x4567);
         TEST("BLSK R3,sym1234", 0x00B3, 0x1234);
     } else {
@@ -176,7 +195,7 @@ static void test_src() {
     ERRT("ABS  @8(R0)", REGISTER_NOT_ALLOWED, "R0)");
 
     if (is9995()) {
-        // TMS9995
+        // TMS9995, TMS99105, TMS99110
         TEST("DIVS R2",         0x0182);
         TEST("DIVS *R3",        0x0193);
         TEST("DIVS @>1234",     0x01A0, 0x1234);
@@ -190,8 +209,8 @@ static void test_src() {
         ERUI("MPYS R0");
     }
 
-    if (is99105()) {
-        // TMS99105
+    if (is991xx()) {
+        // TMS99105, TMS99110
         TEST("TMB  @>0123(R15),7", 0x0C09, 0x01EF, 0x0123);
         TEST("TCMB R0,0",          0x0C0A, 0x0000);
         TEST("TSMB *R2,15",        0x0C0B, 0x03D2);
@@ -208,6 +227,24 @@ static void test_src() {
         ERUI("EVAD R5");
     }
 
+    if (is99110()) {
+        TEST("AR  R2",         0x0C42);
+        TEST("CIR *R3",        0x0C93);
+        TEST("SR  @>1234",     0x0CE0, 0x1234);
+        TEST("MR  @>1234(R5)", 0x0D25, 0x1234);
+        TEST("DR  *R6+",       0x0D76);
+        TEST("LR  R2",         0x0D82);
+        TEST("STR *R3",        0x0DD3);
+    } else {
+        ERUI("AR  R2");
+        ERUI("CIR *R3");
+        ERUI("SR  @>1234");
+        ERUI("MR  @>1234(R5)");
+        ERUI("DR  *R6+");
+        ERUI("LR  R2");
+        ERUI("STR *R3");
+    }
+
     symtab.intern(-2, "neg2");
     symtab.intern(0x1000, "sym1000");
     symtab.intern(0x1234, "sym1234");
@@ -217,13 +254,13 @@ static void test_src() {
     TEST("DEC  @neg2(R7)",    0x0627, 0xFFFE);
 
     if (is9995()) {
-        // TMS9995
+        // TMS9995, TMS99105, TMS99110
         TEST("DIVS @sym1234",     0x01A0, 0x1234);
         TEST("DIVS @sym1000(R4)", 0x01A4, 0x1000);
     }
 
-    if (is99105()) {
-        // TMS99105
+    if (is991xx()) {
+        // TMS99105, TMS99110
         TEST("BIND @sym1000(R1)", 0x0161, 0x1000);
     }
 }
@@ -255,8 +292,8 @@ static void test_cnt_src() {
     TEST("STCR @offset2(R4),16",    0x3424, 0x0002);
     TEST("STCR @>1000(R4),size7",   0x35E4, 0x1000);
 
-    if (is99105()) {
-        // TMS99105
+    if (is991xx()) {
+        // TMS99105, TMS99110
         TEST("SRAM @offset2(R4),15", 0x001C, 0x43E4, 0x0002);
         TEST("SLAM R11,R0",          0x001D, 0x400B);
         TEST("SLAM *R13+,1",         0x001D, 0x407D);
@@ -317,8 +354,8 @@ static void test_dst_src() {
     TEST("SOC  @sym1234,@sym2345(R11)", 0xEAE0, 0x1234, 0x2345);
     TEST("SOCB @sym1234(R10),@sym2345", 0xF82A, 0x1234, 0x2345);
 
-    if (is99105()) {
-        // TMS99105
+    if (is991xx()) {
+        // TMS99105, TMS99110
         TEST("SM @sym2345(R10),@sym4000(R11)", 0x0029, 0x4AEA, 0x2345, 0x4000);
         TEST("SM @sym1234,@sym4000",           0x0029, 0x4820, 0x1234, 0x4000);
         TEST("SM R10,@sym4000(R11)",           0x0029, 0x4ACA, 0x4000);
@@ -329,6 +366,18 @@ static void test_dst_src() {
         ERUI("SM R10,@sym4000(R11)");
         ERUI("AM @zero(R10),@1(R11)");
     }
+
+    if (is99110()) {
+        TEST("CR @>1234(R10), @>5678(R11)", 0x0301, 0x0AEA, 0x1234, 0x5678);
+        TEST("CR @>1234, @>5678",           0x0301, 0x0820, 0x1234, 0x5678);
+        TEST("CR R10, @>4000(R11)",         0x0301, 0x0ACA, 0x4000);
+        TEST("MM @0(R10), @1(R11)",    0x0302, 0x0AEA, 0x0000, 0x0001);
+        TEST("MM @>1234, @>5678(R11)", 0x0302, 0x0AE0, 0x1234, 0x5678);
+        TEST("MM @>1234(R10), @>5678", 0x0302, 0x082A, 0x1234, 0x5678);
+    } else {
+        ERUI("CR R10, @>4000(R11)");
+        ERUI("MM @0(R10), @1(R11)");
+    }
 }
 
 static void test_rel() {
diff --git a/test/test_dis_tms9900.cpp b/test/test_dis_tms9900.cpp
index 855365bf..0b8d289d 100644
--- a/test/test_dis_tms9900.cpp
+++ b/test/test_dis_tms9900.cpp
@@ -25,21 +25,24 @@ using namespace libasm::test;
 DisTms9900 dis9900;
 Disassembler &disassembler(dis9900);
 
-static bool is9900() {
-    return strcmp_P("9900", disassembler.config().cpu_P()) == 0 ||
-           strcmp_P("9980", disassembler.config().cpu_P()) == 0;
+static bool is99110() {
+    return strcmp_P("99110", disassembler.config().cpu_P()) == 0;
+}
+
+static bool is99105() {
+    return strcmp_P("99105", disassembler.config().cpu_P()) == 0;
 }
 
 static bool is9980() {
     return strcmp_P("9980", disassembler.config().cpu_P()) == 0;
 }
 
-static bool is9995() {
-    return strcmp_P("9995", disassembler.config().cpu_P()) == 0;
+static bool is9900() {
+    return strcmp_P("9900", disassembler.config().cpu_P()) == 0 || is9980();
 }
 
-static bool is99105() {
-    return strcmp_P("99105", disassembler.config().cpu_P()) == 0;
+static bool is9995() {
+    return strcmp_P("9995", disassembler.config().cpu_P()) == 0;
 }
 
 static void set_up() {
@@ -86,7 +89,7 @@ static void test_inh() {
     TEST("CKOF", "", 0x03C0);
     TEST("LREX", "", 0x03E0);
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("RTWP", "1", 0x0381);
         TEST("RTWP", "2", 0x0382);
         TEST("RTWP", "4", 0x0384);
@@ -95,6 +98,21 @@ static void test_inh() {
         UNKN(0x0382);
         UNKN(0x0384);
     }
+    if (is99110()) {
+        TEST("LDS",  "", 0x0780);
+        TEST("LDD",  "", 0x07C0);
+        TEST("CRI",  "", 0x0C00);
+        TEST("NEGR", "", 0x0C02);
+        TEST("CRE",  "", 0x0C04);
+        TEST("CER",  "", 0x0C06);
+    } else {
+        UNKN(0x0780);
+        UNKN(0x07C0);
+        UNKN(0x0C00);
+        UNKN(0x0C02);
+        UNKN(0x0C04);
+        UNKN(0x0C06);
+    }
 }
 
 static void test_imm() {
@@ -135,7 +153,7 @@ static void test_reg_imm() {
 
     TEST("LI",   "R2, sym1234", 0x0202, 0x1234);
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("BLSK", "R3, >4567",   0x00B3, 0x4567);
         TEST("BLSK", "R3, sym1234", 0x00B3, 0x1234);
     } else {
@@ -178,7 +196,7 @@ static void test_src() {
         UNKN(0x01E8);
         UNKN(0x01FF);
     } else {
-        // TMS9995, TMS99105
+        // TMS9995, TMS99105, TMS99110
         TEST("DIVS", "R2",         0x0182);
         TEST("DIVS", "*R3",        0x0193);
         TEST("DIVS", "@>1234",     0x01A0, 0x1234);
@@ -189,7 +207,7 @@ static void test_src() {
         TEST("MPYS", "*R15+",      0x01FF);
     }
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("TMB",  "@>0123(R15), 7",          0x0C09, 0x01EF, 0x0123);
         NMEM("TMB",  "@0(R15), 7", "0(R15), 7", 0x0C09, 0x01EF);
         NMEM("TMB",  "",           "",          0x0C09);
@@ -205,6 +223,24 @@ static void test_src() {
         UNKN(0x0105);
     }
 
+    if (is99110()) {
+        TEST("AR",  "R2",         0x0C42);
+        TEST("CIR", "*R3",        0x0C93);
+        TEST("SR",  "@>1234",     0x0CE0, 0x1234);
+        TEST("MR",  "@>1234(R5)", 0x0D25, 0x1234);
+        TEST("DR",  "*R6+",       0x0D76);
+        TEST("LR",  "R2",         0x0D82);
+        TEST("STR", "*R3",        0x0DD3);
+    } else {
+        UNKN(0x0C42);
+        UNKN(0x0C93);
+        UNKN(0x0CE0);
+        UNKN(0x0D25);
+        UNKN(0x0D76);
+        UNKN(0x0D82);
+        UNKN(0x0DD3);
+    }
+
     symtab.intern(-2, "neg2");
     symtab.intern(0x1000, "sym1000");
     symtab.intern(0x1234, "sym1234");
@@ -213,12 +249,12 @@ static void test_src() {
     TEST("BLWP", "@sym3876",     0x0420, 0x3876);
     TEST("DEC",  "@neg2(R7)",    0x0627, 0xFFFE);
 
-    if (is9995() || is99105()) {
+    if (is9995() || is99105() || is99110()) {
         TEST("DIVS", "@sym1234",     0x01A0, 0x1234);
         TEST("DIVS", "@sym1000(R4)", 0x01A4, 0x1000);
     }
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("BIND", "@sym1000(R1)", 0x0161, 0x1000);
     }
 }
@@ -241,7 +277,7 @@ static void test_cnt_src() {
     TEST("LDCR", "*R13+, 16",  0x303D);
     TEST("STCR", "@2(R4), 15", 0x37E4, 0x0002);
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("SRAM", "@2(R4), 15",              0x001C, 0x43E4, 0x0002);
         NMEM("SRAM", "@0(R4), 15", "0(R4), 15", 0x001C, 0x43E4);
         NMEM("SRAM", "",           "",          0x001C);
@@ -256,7 +292,7 @@ static void test_cnt_src() {
     TEST("STCR", "@offset2(R4), 16",    0x3424, 0x0002);
     TEST("STCR", "@>1000(R4), size7",   0x35E4, 0x1000);
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("SRAM", "@offset2(R4), 15", 0x001C, 0x43E4, 0x0002);
         TEST("SLAM", "R11, R0",          0x001D, 0x400B);
         TEST("SLAM", "*R13+, 1",         0x001D, 0x407D);
@@ -303,7 +339,7 @@ static void test_dst_src() {
         TEST("AB", "R10, @>3FFF",                               0xB80A, 0x3FFF);
         ERRT("AB", "R10, @>4000", OVERFLOW_RANGE, ">4000",      0xB80A, 0x4000);
     }
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("SM", "@>1234(R10), @>5678(R11)",            0x0029, 0x4AEA, 0x1234, 0x5678);
         NMEM("SM", "@>1234(R10), @0(R11)",      "0(R11)", 0x0029, 0x4AEA, 0x1234);
         NMEM("SM", "@0(R10), @0(R11)", "0(R10), @0(R11)", 0x0029, 0x4AEA);
@@ -313,6 +349,24 @@ static void test_dst_src() {
         TEST("AM", "@0(R10), @1(R11)",    0x002A, 0x4AEA, 0x0000, 0x0001);
         TEST("AM", "@>1234, @>5678(R11)", 0x002A, 0x4AE0, 0x1234, 0x5678);
         TEST("AM", "@>1234(R10), @>5678", 0x002A, 0x482A, 0x1234, 0x5678);
+    } else {
+        UNKN(0x0029);
+        UNKN(0x002A);
+    }
+
+    if (is99110()) {
+        TEST("CR", "@>1234(R10), @>5678(R11)",            0x0301, 0x0AEA, 0x1234, 0x5678);
+        NMEM("CR", "@>1234(R10), @0(R11)",      "0(R11)", 0x0301, 0x0AEA, 0x1234);
+        NMEM("CR", "@0(R10), @0(R11)", "0(R10), @0(R11)", 0x0301, 0x0AEA);
+        NMEM("CR", "",                 "",                0x0301);
+        TEST("CR", "@>1234, @>5678",      0x0301, 0x0820, 0x1234, 0x5678);
+        TEST("CR", "R10, @>4000(R11)",    0x0301, 0x0ACA, 0x4000);
+        TEST("MM", "@0(R10), @1(R11)",    0x0302, 0x0AEA, 0x0000, 0x0001);
+        TEST("MM", "@>1234, @>5678(R11)", 0x0302, 0x0AE0, 0x1234, 0x5678);
+        TEST("MM", "@>1234(R10), @>5678", 0x0302, 0x082A, 0x1234, 0x5678);
+    } else {
+        UNKN(0x0301);
+        UNKN(0x0302);
     }
 
     symtab.intern(0x0000, "zero");
@@ -328,16 +382,13 @@ static void test_dst_src() {
     TEST("SOC",  "@sym1234, @sym5678(R11)",      0xEAE0, 0x1234, 0x5678);
     TEST("SOCB", "@sym1234(R10), @sym3456",      0xF82A, 0x1234, 0x3456);
 
-    if (is99105()) {
+    if (is99105() || is99110()) {
         TEST("SM", "@sym1234(R10), @sym5678(R11)", 0x0029, 0x4AEA, 0x1234, 0x5678);
         TEST("SM", "@sym1234, @sym5678",           0x0029, 0x4820, 0x1234, 0x5678);
         TEST("SM", "R10, @sym4000(R11)",           0x0029, 0x4ACA, 0x4000);
         TEST("AM", "@zero(R10), @1(R11)",          0x002A, 0x4AEA, 0x0000, 0x0001);
         TEST("AM", "@sym1234, @sym5678(R11)",      0x002A, 0x4AE0, 0x1234, 0x5678);
         TEST("AM", "@sym1234(R10), @sym5678",      0x002A, 0x482A, 0x1234, 0x5678);
-    } else {
-        UNKN(0x0029);
-        UNKN(0x002A);
     }
 }
 
@@ -435,8 +486,8 @@ static void test_illegal_tms9995() {
 
 static void test_illegal_tms99105() {
     static constexpr illegal_range mids[] = {
-        { 0x0000, 0x001B }, { 0x001E, 0x0028 }, { 0x002B, 0x007f }, { 0x00A0, 0x00AF },
-        { 0x00C0, 0x00FF },
+        { 0x0000, 0x001b }, { 0x001e, 0x0028 }, { 0x002b, 0x007f }, { 0x00a0, 0x00af },
+        { 0x00c0, 0x00ff },
         { 0x0210, 0x021f }, { 0x0230, 0x023f }, { 0x0250, 0x025f }, { 0x0270, 0x027f },
         { 0x0290, 0x029f }, { 0x02b0, 0x02bf }, { 0x02d0, 0x02df }, { 0x02e1, 0x02ff },
         { 0x0301, 0x033f }, { 0x0341, 0x035f }, { 0x0361, 0x037f }, { 0x0383, 0x0383 },
@@ -469,6 +520,44 @@ static void test_illegal_tms99105() {
         }
     }
 }
+
+static void test_illegal_tms99110() {
+    static constexpr illegal_range mids[] = {
+        { 0x0000, 0x001b }, { 0x001e, 0x0028 }, { 0x002b, 0x007f }, { 0x00a0, 0x00af },
+        { 0x00c0, 0x00ff },
+        { 0x0210, 0x021f }, { 0x0230, 0x023f }, { 0x0250, 0x025f }, { 0x0270, 0x027f },
+        { 0x0290, 0x029f }, { 0x02b0, 0x02bf }, { 0x02d0, 0x02df }, { 0x02e1, 0x02ff },
+        { 0x0303, 0x033f }, { 0x0341, 0x035f }, { 0x0361, 0x037f }, { 0x0383, 0x0383 },
+        { 0x0385, 0x039f }, { 0x03a1, 0x03bf }, { 0x03c1, 0x03df }, { 0x03e1, 0x03ff },
+        { 0x0781, 0x07bf }, { 0x07c1, 0x07ff }, { 0x0c01, 0x0c01 }, { 0x0c03, 0x0c03 },
+        { 0x0c05, 0x0c05 }, { 0x0c07, 0x0c08 }, { 0x0e00, 0x0fff },
+   };
+    for (const auto &r : mids) {
+        for (auto opc = r.start; opc <= r.end; opc++) {
+            UNKN(opc);
+        }
+    }
+
+    for (auto post = 0; post < 0x10000; post++) {
+        const Config::opcode_t opc = post;
+        const auto hi4 = (post >> 12);
+        if (hi4 != 4) {
+            ERRT("SM", "", UNKNOWN_POSTBYTE, "", SM, opc);
+            ERRT("AM", "", UNKNOWN_POSTBYTE, "", AM, opc);
+        }
+        const auto hi6 = (post >> 10);
+        if (hi6 != 0x10) {
+            ERRT("SRAM", "", UNKNOWN_POSTBYTE, "", SRAM, opc);
+            ERRT("SLAM", "", UNKNOWN_POSTBYTE, "", SLAM, opc);
+        }
+        const auto ts = (post >> 4) & 3;
+        if (hi6 || ts == 3) {
+            ERRT("TMB",  "", UNKNOWN_POSTBYTE, "", TMB,  opc);
+            ERRT("TCMB", "", UNKNOWN_POSTBYTE, "", TCMB, opc);
+            ERRT("TSMB", "", UNKNOWN_POSTBYTE, "", TSMB, opc);
+        }
+    }
+}
 // clang-format on
 
 void run_tests(const char *cpu) {
@@ -491,6 +580,8 @@ void run_tests(const char *cpu) {
         RUN_TEST(test_illegal_tms9995);
     if (is99105())
         RUN_TEST(test_illegal_tms99105);
+    if (is99110())
+        RUN_TEST(test_illegal_tms99110);
 }
 
 // Local Variables: