From 4f55f01ffa4e99421af1b71b5bbbf867faf692bf Mon Sep 17 00:00:00 2001 From: Luca Colagrande Date: Thu, 1 Aug 2024 15:04:55 +0200 Subject: [PATCH] `gen_trace.py`: Represent SIMD operands as vectors (#115) Co-authored-by: Viviane Potocnik --- docs/rm/trace/gen_trace.md | 1 + docs/ug/trace_analysis.md | 4 +- mkdocs.yml | 3 + util/trace/gen_trace.py | 194 ++++++-- util/trace/opcodes-flt-occamy_CUSTOM.csv | 555 +++++++++++++++++++++++ 5 files changed, 718 insertions(+), 39 deletions(-) create mode 100644 docs/rm/trace/gen_trace.md create mode 100644 util/trace/opcodes-flt-occamy_CUSTOM.csv diff --git a/docs/rm/trace/gen_trace.md b/docs/rm/trace/gen_trace.md new file mode 100644 index 000000000..c15c297be --- /dev/null +++ b/docs/rm/trace/gen_trace.md @@ -0,0 +1 @@ +::: gen_trace diff --git a/docs/ug/trace_analysis.md b/docs/ug/trace_analysis.md index d1eddf633..0fefb2dfd 100644 --- a/docs/ug/trace_analysis.md +++ b/docs/ug/trace_analysis.md @@ -2,9 +2,9 @@ ## Trace generation -During RTL simulation, the Snitch core complex (CC) dumps a wide set of information to the `logs/trace_hart_XXXXX.dasm` file (see [snitch_cc.sv](../../hw/snitch_cluster/src/snitch_cc.sv)), `XXXXX` denoting the index of the Snitch core in the system. +During RTL simulation, the Snitch core complex (CC) dumps a wide set of information to the `logs/trace_hart_XXXXX.dasm` file (see [snitch_cc.sv](https://github.com/pulp-platform/snitch_cluster/blob/main/hw/snitch_cluster/src/snitch_cc.sv)), `XXXXX` denoting the index of the Snitch core in the system. -The [gen_trace.py](../../util/trace/gen_trace.py) script can be used to elaborate this information into a human-readable form, and is invoked by the `make traces` target to generate `logs/trace_hart_XXXXX.txt`. +The [gen_trace.py](../rm/trace/gen_trace.md) script can be used to elaborate this information into a human-readable form, and is invoked by the `make traces` target to generate `logs/trace_hart_XXXXX.txt`. ## Trace walkthrough diff --git a/mkdocs.yml b/mkdocs.yml index e0a8db8f2..61e4494a9 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -27,6 +27,7 @@ plugins: python: paths: - util/sim + - util/trace - target/snitch_cluster/util - macros: on_error_fail: true @@ -64,6 +65,8 @@ nav: - rm/sim/Simulation.md - rm/sim/Simulator.md - rm/sim/Elf.md + - Trace Utilities: + - gen_trace.py: rm/trace/gen_trace.md - Snitch Target Utilities: - run.py: rm/snitch_target_utils/run.md - build.py: rm/snitch_target_utils/build.md diff --git a/util/trace/gen_trace.py b/util/trace/gen_trace.py index e552d5069..fb3351ed2 100755 --- a/util/trace/gen_trace.py +++ b/util/trace/gen_trace.py @@ -2,22 +2,26 @@ # Copyright 2020 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# This script takes a trace generated for a Snitch hart and transforms the -# additional decode stage info into meaningful annotation. It also counts -# and computes various performance metrics up to each mcycle CSR read. - +# # Author: Paul Scheffler +# Luca Colagrande +"""Human-readable Snitch trace generator script. + +This script takes a trace generated for a Snitch hart and transforms the +additional decode stage info into meaningful annotation. It also counts +and computes various performance metrics up to each mcycle CSR read. +""" # TODO: OPER_TYPES and FPU_OPER_TYPES could break: optimization might alter enum mapping # TODO: We annotate all FP16 LSU values as IEEE, not FP16ALT... can we do better? import sys import re -import math import argparse import json from ctypes import c_int32, c_uint32 from collections import deque, defaultdict +import pathlib EXTRA_WB_WARN = 'WARNING: {} transactions still in flight for {}.' @@ -309,22 +313,116 @@ # -------------------- FPU helpers -------------------- -def flt_oper(extras: dict, port: int) -> (str, str): +_cached_opcodes = None + + +def load_opcodes(): + global _cached_opcodes + opcode_file_name = 'opcodes-flt-occamy_CUSTOM.csv' + opcode_file_path = pathlib.Path(__file__).parent.absolute() / opcode_file_name + + _cached_opcodes = {} + with open(opcode_file_path, 'r') as f: + for line in f: + fields = line.strip().split(',') + insn_name = fields[0] + vec_params = fields[1:5] + _cached_opcodes[insn_name] = vec_params + + +def flt_op_vlen(insn: str, op_type: str) -> int: + """Get the vector length of a floating-point instruction operand. + + Args: + insn: Instruction as extracted from the trace line. + op_type: One of the operand types defined in `FPU_OPER_TYPES`. + Returns: + The vector length of the operand, greater than one if SIMD. + """ + global _cached_opcodes + if _cached_opcodes is None: + load_opcodes() + + # Cut the instruction after the first space to get the instruction name + insn = insn.split(' ')[0] + + # Check if operand is a source or a destination + is_rd = (op_type == 'rd') + + # Get operand parameters from the instruction + op_params = _cached_opcodes.get(insn, None) + + # Get vector length of operand + if op_params is not None and op_params != ([''] * 4): + vlen = int(op_params[3]) if is_rd else int(op_params[1]) + else: + vlen = 1 + return vlen + + +def flt_op_fmt(extras: dict, port: int) -> int: + """Extracts the floating-point format of an instruction operand. + + Args: + extras: The dictionary containing the instruction's extra + information. + port: The index of the floating-point operand. + """ op_sel = extras['op_sel_{}'.format(port)] oper_type = FPU_OPER_TYPES[op_sel] - if oper_type == 'acc': - return 'ac{}'.format(port + 1), int_lit( - extras['acc_qdata_{}'.format(port)], extras['int_fmt']) - elif oper_type == 'NONE': - return oper_type, None + if extras['is_store']: + return LS_TO_FLOAT[extras['ls_size']] else: - fmt = LS_TO_FLOAT[ - extras['ls_size']] if extras['is_store'] else extras['src_fmt'] - return REG_ABI_NAMES_F[extras[oper_type]], flt_lit( - extras['op_{}'.format(port)], fmt) + if oper_type == 'rd': + return extras['dst_fmt'] + else: + return extras['src_fmt'] + + +def flt_oper(insn: str, extras: dict, port: int) -> (str, str): + """Extracts details on the floating-point operand of an instruction. + + Args: + insn: The current instruction mnemonic. + extras: The dictionary containing the instruction's extra + information. + port: The index of the floating-point operand. + Returns: + A tuple containing the operand's register name and a string + literal representing the floating-point value. + """ + op_sel = extras['op_sel_{}'.format(port)] + oper_type = FPU_OPER_TYPES[op_sel] + + # Assign default return values + reg = oper_type + lit = None + + # If operand comes from accelerator interface, format as integer. + if oper_type == 'acc': + reg = 'ac{}'.format(port + 1) + lit = int_lit(extras['acc_qdata_{}'.format(port)], extras['int_fmt']) + # If operand is not unspecified, format as floating-point. + elif oper_type != 'NONE': + # Get operand vector length, FP format and integer encoding + vlen = flt_op_vlen(insn, oper_type) + fmt = flt_op_fmt(extras, port) + enc = extras['op_{}'.format(port)] + # Return register name and floating-point literal + return REG_ABI_NAMES_F[extras[oper_type]], flt_lit(enc, fmt, vlen=vlen) + return reg, lit def flt_decode(val: int, fmt: int) -> float: + """Interprets the binary encoding of an integer as a FP value. + + Args: + val: The integer encoding of the FP variable to decode. + fmt: The floating point number format, as an index into the + `FLOAT_FMTS` array. + Returns: + The floating point value represented by the input integer. + """ # get format and bit vector w_exp, w_mnt = FLOAT_FMTS[fmt] width = 1 + w_exp + w_mnt @@ -349,17 +447,16 @@ def flt_decode(val: int, fmt: int) -> float: return float(sgn * bse * (2**exp)) -def flt_fmt(flt: float, width: int = 7) -> str: - # If default literal shorter: use it - default_str = str(flt) - if len(default_str) - 1 <= width: - return default_str - # Else: fix significant digits, using exponential if needed - exp, _ = math.frexp(flt) - fmt = '{:1.' + str(width - 3) + 'e}' - if not math.isnan(exp) and -1 < exp <= width: - exp = int(exp) - fmt = '{:' + str(exp) + '.' + str(width - exp) + 'f}' +def flt_fmt(flt: float, width: int = 6) -> str: + """Formats a floating-point number rounding to a certain decimal precision. + + Args: + flt: The floating-point number to format. + width: The number of significant decimal digits to round to. + Returns: + The formatted floating-point number as a string. + """ + fmt = '{:.' + str(width) + '}' return fmt.format(flt) @@ -377,8 +474,27 @@ def int_lit(num: int, size: int = 2, force_hex: bool = False) -> str: return str(num_signed) -def flt_lit(num: int, fmt: int, width: int = 7) -> str: - return flt_fmt(flt_decode(num, fmt), width) +def flt_lit(num: int, fmt: int, width: int = 6, vlen: int = 1) -> str: + """Formats an integer encoding into a floating-point literal. + + Args: + num: The integer encoding of the floating-point number(s). + fmt: The floating point number format, as an index into the + `FLOAT_FMTS` array. + width: The bitwidth of the floating-point type. + vlen: The number of floating-point numbers packed in the encoding, + >1 for SIMD vectors. + """ + # Divide the binary encoding into individual encodings for each number in the SIMD vector. + bitwidth = 1 + FLOAT_FMTS[fmt][0] + FLOAT_FMTS[fmt][1] + vec = [num >> (bitwidth * i) & (2**bitwidth - 1) for i in reversed(range(vlen))] + # Format each individual float encoding to a string. + floats = [flt_fmt(flt_decode(val, fmt), width) for val in vec] + # Represent the encodings as a vector if SIMD. + if len(floats) > 1: + return '[{}]'.format(', '.join(floats)) + else: + return floats[0] # -------------------- FPU Sequencer -------------------- @@ -554,6 +670,7 @@ def annotate_snitch(extras: dict, def annotate_fpu( extras: dict, + insn: str, cycle: int, fpr_wb_info: dict, perf_metrics: list, @@ -564,14 +681,16 @@ def annotate_fpu( ret = [] # On issuing of instruction if extras['acc_q_hs']: - # If computation initiated: remember FPU destination format + # If computation initiated: remember FPU destination format and vector length if extras['use_fpu'] and not extras['fpu_in_acc']: + vlen = flt_op_vlen(insn, 'rd') fpr_wb_info[extras['fpu_in_rd']].appendleft( - (extras['dst_fmt'], cycle)) + (extras['dst_fmt'], vlen, cycle)) # Operands: omit on store if not extras['is_store']: for i_op in range(3): - oper_name, val = flt_oper(extras, i_op) + # operand name and its value + oper_name, val = flt_oper(insn, extras, i_op) if oper_name != 'NONE': ret.append('{:<4} = {}'.format(oper_name, val)) # Load / Store requests @@ -580,13 +699,14 @@ def annotate_fpu( if extras['is_load']: perf_metrics[curr_sec]['fpss_loads'] += 1 # Load initiated: remember LSU destination format - fpr_wb_info[extras['rd']].appendleft((LS_TO_FLOAT[s], cycle)) + vlen = 1 + fpr_wb_info[extras['rd']].appendleft((LS_TO_FLOAT[s], vlen, cycle)) ret.append('{:<4} <~~ {}[{}]'.format( REG_ABI_NAMES_F[extras['rd']], LS_SIZES[s], int_lit(extras['lsu_qaddr'], force_hex=force_hex_addr))) if extras['is_store']: perf_metrics[curr_sec]['fpss_stores'] += 1 - _, val = flt_oper(extras, 1) + _, val = flt_oper(insn, extras, 1) ret.append('{} ~~> {}[{}]'.format( val, LS_SIZES[s], int_lit(extras['lsu_qaddr'], force_hex=force_hex_addr))) @@ -601,7 +721,7 @@ def annotate_fpu( fmt = 0 # accelerator bus format is 0 for regular float32 if writer == 'fpu' or writer == 'lsu': try: - fmt, start_time = fpr_wb_info[extras['fpr_waddr']].pop() + fmt, vlen, start_time = fpr_wb_info[extras['fpr_waddr']].pop() if writer == 'lsu': perf_metrics[curr_sec][ 'fpss_load_latency'] += cycle - start_time @@ -618,7 +738,7 @@ def annotate_fpu( sys.exit(1) ret.append('(f:{}) {:<4} <-- {}'.format( writer, REG_ABI_NAMES_F[extras['fpr_waddr']], - flt_lit(extras['fpr_wdata'], fmt))) + flt_lit(extras['fpr_wdata'], fmt, vlen=vlen))) return ', '.join(ret) @@ -698,7 +818,7 @@ def annotate_insn( annot_list.append('[{} {}:{}]'.format( fseq_pc_str[-4:], *fseq_annot)) annot_list.append( - annotate_fpu(extras, time_info[1], fpr_wb_info, perf_metrics, + annotate_fpu(extras, insn, time_info[1], fpr_wb_info, perf_metrics, fseq_info['curr_sec'], force_hex_addr, permissive)) annot = ', '.join(annot_list) @@ -882,7 +1002,7 @@ def main(): warn_trip = True sys.stderr.write( EXTRA_WB_WARN.format(len(que), REG_ABI_NAMES_F[fpr]) + '\n') - for gpr, que in fpr_wb_info.items(): + for gpr, que in gpr_wb_info.items(): if len(que) != 0: warn_trip = True sys.stderr.write( diff --git a/util/trace/opcodes-flt-occamy_CUSTOM.csv b/util/trace/opcodes-flt-occamy_CUSTOM.csv new file mode 100644 index 000000000..00766424a --- /dev/null +++ b/util/trace/opcodes-flt-occamy_CUSTOM.csv @@ -0,0 +1,555 @@ +instruction,source_width,source_vec_len,destination_width,destination_vec_len +fadd.d,64,1,64,1 +fsub.d,64,1,64,1 +fmul.d,64,1,64,1 +fdiv.d,64,1,64,1 +fsgnj.d,64,1,64,1 +fsgnjn.d,64,1,64,1 +fsgnjx.d,64,1,64,1 +fmin.d,64,1,64,1 +fmax.d,64,1,64,1 +fcvt.s.d,64,1,64,1 +fcvt.d.s,64,1,64,1 +fsqrt.d,64,1,64,1 +fle.d,64,1,64,1 +flt.d,64,1,64,1 +feq.d,64,1,64,1 +fcvt.w.d,,,, +fcvt.wu.d,,,, +fclass.d,,,, +fcvt.d.w,,,, +fcvt.d.wu,,,, +fld,64,1,64,1 +fsd,64,1,64,1 +fmadd.d,64,1,64,1 +fmsub.d,64,1,64,1 +fnmsub.d,64,1,64,1 +fnmadd.d,64,1,64,1 +fadd.s,32,1,32,1 +fsub.s,32,1,32,1 +fmul.s,32,1,32,1 +fdiv.s,32,1,32,1 +fsgnj.s,32,1,32,1 +fsgnjn.s,32,1,32,1 +fsgnjx.s,32,1,32,1 +fmin.s,32,1,32,1 +fmax.s,32,1,32,1 +fsqrt.s,32,1,32,1 +fle.s,32,1,32,1 +flt.s,32,1,32,1 +feq.s,32,1,32,1 +fcvt.w.s,32,1,32,1 +fcvt.wu.s,32,1,32,1 +fmv.x.w,32,1,32,1 +fclass.s,32,1,32,1 +fcvt.s.w,32,1,32,1 +fcvt.s.wu,32,1,32,1 +fmv.w.x,32,1,32,1 +flw,32,1,32,1 +fsw,32,1,32,1 +fmadd.s,32,1,32,1 +fmsub.s,32,1,32,1 +fnmsub.s,32,1,32,1 +fnmadd.s,32,1,32,1 +flh,16,1,16,1 +fsh,16,1,16,1 +fadd.s,32,1,32,1 +fsub.s,32,1,32,1 +fmadd.h,16,1,16,1 +fmsub.h,16,1,16,1 +fnmsub.h,16,1,16,1 +fnmadd.h,16,1,16,1 +fadd.h,16,1,16,1 +fsub.h,16,1,16,1 +fmul.h,16,1,16,1 +fdiv.h,16,1,16,1 +fsqrt.h,16,1,16,1 +fsgnj.h,16,1,16,1 +fsgnjn.h,16,1,16,1 +fsgnjx.h,16,1,16,1 +fmin.h,16,1,16,1 +fmax.h,16,1,16,1 +feq.h,16,1,16,1 +flt.h,16,1,16,1 +fle.h,16,1,16,1 +fcvt.w.h,16,1,32,1 +fcvt.wu.h,,,, +fcvt.h.w,32,1,16,1 +fcvt.h.wu,,,, +fmv.x.h,,,, +fclass.h,,,, +fmv.h.x,,,, +fcvt.l.h,16,1,64,1 +fcvt.lu.h,,,, +fcvt.h.l,64,1,16,1 +fcvt.h.lu,,,, +fcvt.s.h,16,1,32,1 +fcvt.h.s,32,1,16,1 +fcvt.d.h,16,1,64,1 +fcvt.h.d,64,1,16,1 +flah,16,1,16,1 +fsah,16,1,16,1 +fmadd.ah,16,1,16,1 +fmsub.ah,16,1,16,1 +fnmsub.ah,16,1,16,1 +fnmadd.ah,16,1,16,1 +fadd.ah,16,1,16,1 +fsub.ah,16,1,16,1 +fmul.ah,16,1,16,1 +fdiv.ah,16,1,16,1 +fsqrt.ah,16,1,16,1 +fsgnj.ah,16,1,16,1 +fsgnjn.ah,16,1,16,1 +fsgnjx.ah,16,1,16,1 +fmin.ah,16,1,16,1 +fmax.ah,16,1,16,1 +feq.ah,16,1,16,1 +flt.ah,16,1,16,1 +fle.ah,16,1,16,1 +fcvt.w.ah,16,1,32,1 +fcvt.wu.ah,,,, +fcvt.ah.w,32,1,16,1 +fcvt.ah.wu,,,, +fmv.x.ah,,,, +fclass.ah,,,, +fmv.ah.x,,,, +fcvt.l.ah,16,1,64,1 +fcvt.lu.ah,,,, +fcvt.ah.l,64,1,16,1 +fcvt.ah.lu,,,, +fcvt.s.ah,16,1,32,1 +fcvt.ah.s,32,1,16,1 +fcvt.d.ah,16,1,64,1 +fcvt.ah.d,64,1,16,1 +fcvt.h.h,16,1,16,1 +fcvt.ah.h,16,1,16,1 +fcvt.h.ah,16,1,16,1 +fcvt.ah.ah,16,1,16,1 +flb,8,1,8,1 +fsb,8,1,8,1 +fmadd.b,8,1,8,1 +fmsub.b,8,1,8,1 +fnmsub.b,8,1,8,1 +fnmadd.b,8,1,8,1 +fadd.b,8,1,8,1 +fsub.b,8,1,8,1 +fmul.b,8,1,8,1 +fdiv.b,8,1,8,1 +fsqrt.b,8,1,8,1 +fsgnj.b,8,1,8,1 +fsgnjn.b,8,1,8,1 +fsgnjx.b,8,1,8,1 +fmin.b,8,1,8,1 +fmax.b,8,1,8,1 +feq.b,8,1,8,1 +flt.b,8,1,8,1 +fle.b,8,1,8,1 +fcvt.w.b,8,1,32,1 +fcvt.wu.b,,,, +fcvt.b.w,32,1,8,1 +fcvt.b.wu,,,, +fmv.x.b,,,, +fclass.b,,,, +fmv.b.x,,,, +fcvt.l.b,8,1,64,1 +fcvt.lu.b,,,, +fcvt.b.l,64,1,8,1 +fcvt.b.lu,,,, +fcvt.s.b,8,1,32,1 +fcvt.b.s,32,1,8,1 +fcvt.d.b,8,1,64,1 +fcvt.b.d,64,1,8,1 +fcvt.h.b,8,1,16,1 +fcvt.b.h,16,1,8,1 +fcvt.ah.b,8,1,16,1 +fcvt.b.ah,16,1,8,1 +flab,8,1,8,1 +fsab,8,1,8,1 +fmadd.ab,8,1,8,1 +fmsub.ab,8,1,8,1 +fnmsub.ab,8,1,8,1 +fnmadd.ab,8,1,8,1 +fadd.ab,8,1,8,1 +fsub.ab,8,1,8,1 +fmul.ab,8,1,8,1 +fdiv.ab,8,1,8,1 +fsqrt.ab,8,1,8,1 +fsgnj.ab,8,1,8,1 +fsgnjn.ab,8,1,8,1 +fsgnjx.ab,8,1,8,1 +fmin.ab,8,1,8,1 +fmax.ab,8,1,8,1 +feq.ab,8,1,8,1 +flt.ab,8,1,8,1 +fle.ab,8,1,8,1 +fcvt.w.ab,8,1,32,1 +fcvt.wu.ab,,,, +fcvt.ab.w,32,1,8,1 +fcvt.ab.wu,,,, +fmv.x.ab,,,, +fclass.ab,,,, +fmv.ab.x,,,, +fcvt.l.ab,,,, +fcvt.lu.ab,,,, +fcvt.ab.l,,,, +fcvt.ab.lu,,,, +fcvt.s.ab,,,, +fcvt.ab.s,,,, +fcvt.d.ab,,,, +fcvt.ab.d,,,, +fcvt.h.ab,,,, +fcvt.ab.h,,,, +fcvt.ah.ab,,,, +fcvt.ab.ah,,,, +fcvt.b.b,,,, +fcvt.ab.b,,,, +fcvt.b.ab,,,, +fcvt.ab.ab,,,, +vfadd.s,32,2,32,2 +vfadd.r.s,32,2,32,2 +vfsub.s,32,2,32,2 +vfsub.r.s,32,2,32,2 +vfmul.s,32,2,32,2 +vfmul.r.s,32,2,32,2 +vfdiv.s,32,2,32,2 +vfdiv.r.s,32,2,32,2 +vfmin.s,32,2,32,2 +vfmin.r.s,32,2,32,2 +vfmax.s,32,2,32,2 +vfmax.r.s,32,2,32,2 +vfsqrt.s,32,2,32,2 +vfmac.s,32,2,32,2 +vfmac.r.s,32,2,32,2 +vfmre.s,32,2,32,2 +vfmre.r.s,32,2,32,2 +vfclass.s,,,, +vfsgnj.s,32,2,32,2 +vfsgnj.r.s,32,2,32,2 +vfsgnjn.s,32,2,32,2 +vfsgnjn.r.s,32,2,32,2 +vfsgnjx.s,32,2,32,2 +vfsgnjx.r.s,32,2,32,2 +vfeq.s,32,2,32,2 +vfeq.r.s,32,2,32,2 +vfne.s,32,2,32,2 +vfne.r.s,32,2,32,2 +vflt.s,32,2,32,2 +vflt.r.s,32,2,32,2 +vfge.s,32,2,32,2 +vfge.r.s,32,2,32,2 +vfle.s,32,2,32,2 +vfle.r.s,32,2,32,2 +vfgt.s,32,2,32,2 +vfgt.r.s,32,2,32,2 +vfmv.x.s,,,, +vfmv.s.x,,,, +vfcvt.x.s,,,, +vfcvt.xu.s,,,, +vfcvt.s.x,,,, +vfcvt.s.xu,,,, +vfcpka.s.s,32,1,32,2 +vfcpkb.s.s,32,1,32,2 +vfcpkc.s.s,32,1,32,2 +vfcpkd.s.s,32,1,32,2 +vfcpka.s.d,64,1,32,2 +vfcpkb.s.d,64,1,32,2 +vfcpkc.s.d,64,1,32,2 +vfcpkd.s.d,64,1,32,2 +vfcvt.h.h,16,4,16,4 +vfcvt.h.ah,16,4,16,4 +vfcvt.ah.h,16,4,16,4 +vfcvtu.h.h,,,, +vfcvtu.h.ah,,,, +vfcvtu.ah.h,,,, +vfadd.h,16,4,16,4 +vfadd.r.h,16,4,16,4 +vfsub.h,16,4,16,4 +vfsub.r.h,16,4,16,4 +vfmul.h,16,4,16,4 +vfmul.r.h,16,4,16,4 +vfdiv.h,16,4,16,4 +vfdiv.r.h,16,4,16,4 +vfmin.h,16,4,16,4 +vfmin.r.h,16,4,16,4 +vfmax.h,16,4,16,4 +vfmax.r.h,16,4,16,4 +vfsqrt.h,16,4,16,4 +vfmac.h,16,4,16,4 +vfmac.r.h,16,4,16,4 +vfmre.h,16,4,16,4 +vfmre.r.h,16,4,16,4 +vfclass.h,16,4,16,4 +vfsgnj.h,16,4,16,4 +vfsgnj.r.h,16,4,16,4 +vfsgnjn.h,16,4,16,4 +vfsgnjn.r.h,16,4,16,4 +vfsgnjx.h,16,4,16,4 +vfsgnjx.r.h,16,4,16,4 +vfeq.h,16,4,16,4 +vfeq.r.h,16,4,16,4 +vfne.h,16,4,16,4 +vfne.r.h,16,4,16,4 +vflt.h,16,4,16,4 +vflt.r.h,16,4,16,4 +vfge.h,16,4,16,4 +vfge.r.h,16,4,16,4 +vfle.h,16,4,16,4 +vfle.r.h,16,4,16,4 +vfgt.h,16,4,16,4 +vfgt.r.h,16,4,16,4 +vfmv.x.h,,,, +vfmv.h.x,,,, +vfcvt.x.h,,,, +vfcvt.xu.h,,,, +vfcvt.h.x,,,, +vfcvt.h.xu,,,, +vfcpka.h.s,32,1,16,4 +vfcpkb.h.s,32,1,16,4 +vfcpkc.h.s,32,1,16,4 +vfcpkd.h.s,32,1,16,4 +vfcpka.h.d,64,1,16,4 +vfcpkb.h.d,64,1,16,4 +vfcpkc.h.d,64,1,16,4 +vfcpkd.h.d,64,1,16,4 +vfcvt.s.h,16,4,32,2 +vfcvtu.s.h,,,, +vfcvt.h.s,32,2,16,4 +vfcvtu.h.s,,,, +vfadd.ah,16,4,16,4 +vfadd.r.ah,16,4,16,4 +vfsub.ah,16,4,16,4 +vfsub.r.ah,16,4,16,4 +vfmul.ah,16,4,16,4 +vfmul.r.ah,16,4,16,4 +vfdiv.ah,16,4,16,4 +vfdiv.r.ah,16,4,16,4 +vfmin.ah,16,4,16,4 +vfmin.r.ah,16,4,16,4 +vfmax.ah,16,4,16,4 +vfmax.r.ah,16,4,16,4 +vfsqrt.ah,16,4,16,4 +vfmac.ah,16,4,16,4 +vfmac.r.ah,16,4,16,4 +vfmre.ah,16,4,16,4 +vfmre.r.ah,16,4,16,4 +vfclass.ah,16,4,16,4 +vfsgnj.ah,16,4,16,4 +vfsgnj.r.ah,16,4,16,4 +vfsgnjn.ah,16,4,16,4 +vfsgnjn.r.ah,16,4,16,4 +vfsgnjx.ah,16,4,16,4 +vfsgnjx.r.ah,16,4,16,4 +vfeq.ah,16,4,16,4 +vfeq.r.ah,16,4,16,4 +vfne.ah,16,4,16,4 +vfne.r.ah,16,4,16,4 +vflt.ah,16,4,16,4 +vflt.r.ah,16,4,16,4 +vfge.ah,16,4,16,4 +vfge.r.ah,16,4,16,4 +vfle.ah,16,4,16,4 +vfle.r.ah,16,4,16,4 +vfgt.ah,16,4,16,4 +vfgt.r.ah,16,4,16,4 +vfmv.x.ah,,,, +vfmv.ah.x,,,, +vfcvt.x.ah,,,, +vfcvt.xu.ah,,,, +vfcvt.ah.x,,,, +vfcvt.ah.xu,,,, +vfcpka.ah.s,32,1,16,4 +vfcpkb.ah.s,32,1,16,4 +vfcpkc.ah.s,32,1,16,4 +vfcpkd.ah.s,32,1,16,4 +vfcpka.ah.d,64,1,16,4 +vfcpkb.ah.d,64,1,16,4 +vfcpkc.ah.d,64,1,16,4 +vfcpkd.ah.d,64,1,16,4 +vfcvt.s.ah,16,4,32,2 +vfcvtu.s.ah,,,, +vfcvt.ah.s,32,2,16,4 +vfcvtu.ah.s,,,, +vfadd.b,8,8,8,8 +vfadd.r.b,8,8,8,8 +vfsub.b,8,8,8,8 +vfsub.r.b,8,8,8,8 +vfmul.b,8,8,8,8 +vfmul.r.b,8,8,8,8 +vfdiv.b,8,8,8,8 +vfdiv.r.b,8,8,8,8 +vfmin.b,8,8,8,8 +vfmin.r.b,8,8,8,8 +vfmax.b,8,8,8,8 +vfmax.r.b,8,8,8,8 +vfsqrt.b,8,8,8,8 +vfmac.b,8,8,8,8 +vfmac.r.b,8,8,8,8 +vfmre.b,8,8,8,8 +vfmre.r.b,8,8,8,8 +vfsgnj.b,8,8,8,8 +vfsgnj.r.b,8,8,8,8 +vfsgnjn.b,8,8,8,8 +vfsgnjn.r.b,8,8,8,8 +vfsgnjx.b,8,8,8,8 +vfsgnjx.r.b,8,8,8,8 +vfeq.b,8,8,8,8 +vfeq.r.b,8,8,8,8 +vfne.b,8,8,8,8 +vfne.r.b,8,8,8,8 +vflt.b,8,8,8,8 +vflt.r.b,8,8,8,8 +vfge.b,8,8,8,8 +vfge.r.b,8,8,8,8 +vfle.b,8,8,8,8 +vfle.r.b,8,8,8,8 +vfgt.b,8,8,8,8 +vfgt.r.b,8,8,8,8 +vfmv.x.b,,,, +vfmv.b.x,,,, +vfclass.b,8,8,8,8 +vfcvt.x.b,,,, +vfcvt.xu.b,,,, +vfcvt.b.x,,,, +vfcvt.b.xu,,,, +vfcpka.b.s,32,1,8,8 +vfcpkb.b.s,32,1,8,8 +vfcpkc.b.s,32,1,8,8 +vfcpkd.b.s,32,1,8,8 +vfcpka.b.d,64,1,8,8 +vfcpkb.b.d,64,1,8,8 +vfcpkc.b.d,64,1,8,8 +vfcpkd.b.d,64,1,8,8 +vfcvt.s.b,8,8,32,4 +vfcvtu.s.b,,,, +vfcvt.b.s,32,2,8,8 +vfcvtu.b.s,,,, +vfcvt.h.b,8,8,16,4 +vfcvtu.h.b,,,, +vfcvt.b.h,16,4,8,8 +vfcvtu.b.h,,,, +vfcvt.ah.b,8,8,16,4 +vfcvtu.ah.b,,,, +vfcvt.b.ah,16,4,8,8 +vfcvtu.b.ah,,,, +vfcvt.b.b,8,8,8,8 +vfcvt.ab.b,8,8,8,8 +vfcvt.b.ab,8,8,8,8 +vfcvtu.b.b,,,, +vfcvtu.ab.b,,,, +vfcvtu.b.ab,,,, +vfadd.ab,8,8,8,8 +vfadd.r.ab,8,8,8,8 +vfsub.ab,8,8,8,8 +vfsub.r.ab,8,8,8,8 +vfmul.ab,8,8,8,8 +vfmul.r.ab,8,8,8,8 +vfdiv.ab,8,8,8,8 +vfdiv.r.ab,8,8,8,8 +vfmin.ab,8,8,8,8 +vfmin.r.ab,8,8,8,8 +vfmax.ab,8,8,8,8 +vfmax.r.ab,8,8,8,8 +vfsqrt.ab,8,8,8,8 +vfmac.ab,8,8,8,8 +vfmac.r.ab,8,8,8,8 +vfmre.ab,8,8,8,8 +vfmre.r.ab,8,8,8,8 +vfsgnj.ab,8,8,8,8 +vfsgnj.r.ab,8,8,8,8 +vfsgnjn.ab,8,8,8,8 +vfsgnjn.r.ab,8,8,8,8 +vfsgnjx.ab,8,8,8,8 +vfsgnjx.r.ab,8,8,8,8 +vfeq.ab,8,8,8,8 +vfeq.r.ab,8,8,8,8 +vfne.ab,8,8,8,8 +vfne.r.ab,8,8,8,8 +vflt.ab,8,8,8,8 +vflt.r.ab,8,8,8,8 +vfge.ab,8,8,8,8 +vfge.r.ab,8,8,8,8 +vfle.ab,8,8,8,8 +vfle.r.ab,8,8,8,8 +vfgt.ab,8,8,8,8 +vfgt.r.ab,8,8,8,8 +vfmv.x.ab,,,, +vfmv.ab.x,,,, +vfclass.ab,8,8,8,8 +vfcvt.x.ab,,,, +vfcvt.xu.ab,,,, +vfcvt.ab.x,,,, +vfcvt.ab.xu,,,, +vfcpka.ab.s,32,1,8,8 +vfcpkb.ab.s,32,1,8,8 +vfcpkc.ab.s,32,1,8,8 +vfcpkd.ab.s,32,1,8,8 +vfcpka.ab.d,64,1,8,8 +vfcpkb.ab.d,64,1,8,8 +vfcpkc.ab.d,64,1,8,8 +vfcpkd.ab.d,64,1,8,8 +vfcvt.s.ab,8,8,32,4 +vfcvtu.s.ab,,,, +vfcvt.ab.s,32,2,8,8 +vfcvtu.ab.s,,,, +vfcvt.h.ab,8,8,16,4 +vfcvtu.h.ab,,,, +vfcvt.ab.h,16,4,8,8 +vfcvtu.ab.h,,,, +vfcvt.ah.ab,8,8,16,4 +vfcvtu.ah.ab,,,, +vfcvt.ab.ah,16,4,8,8 +vfcvtu.ab.ah,,,, +fmulex.s.h,16,4,32,2 +fmacex.s.h,16,4,32,2 +fmulex.s.ah,16,4,32,2 +fmacex.s.ah,16,4,32,2 +fmulex.s.b,8,8,32,2 +fmacex.s.b,8,8,32,2 +fmulex.s.ab,8,8,32,2 +fmacex.s.ab,8,8,32,2 +vfsum.s,32,2,32,1 +vfnsum.s,32,2,32,1 +vfsum.h,16,4,16,1 +vfnsum.h,16,4,16,1 +vfsum.ah,16,4,16,1 +vfnsum.ah,16,4,16,1 +vfsum.b,8,8,8,8 +vfnsum.b,8,8,8,8 +vfsum.ab,8,8,8,8 +vfnsum.ab,8,8,8,8 +vfsumex.s.h,16,4,32,2 +vfnsumex.s.h,16,4,32,2 +vfdotpex.s.h,16,4,32,2 +vfdotpex.s.r.h,16,4,32,2 +vfndotpex.s.h,16,4,32,2 +vfndotpex.s.r.h,16,4,32,2 +vfsumex.s.ah,16,4,32,2 +vfnsumex.s.ah,16,4,32,2 +vfdotpex.s.ah,16,4,32,2 +vfdotpex.s.r.ah,16,4,32,2 +vfndotpex.s.ah,16,4,32,2 +vfndotpex.s.r.ah,16,4,32,2 +vfsumex.h.b,8,8,16,4 +vfnsumex.h.b,8,8,16,4 +vfdotpex.h.b,8,8,16,4 +vfdotpex.h.r.b,8,8,16,4 +vfndotpex.h.b,8,8,16,4 +vfndotpex.h.r.b,8,8,16,4 +vfsumex.ah.b,8,8,16,4 +vfnsumex.ah.b,8,8,16,4 +vfdotpex.ah.b,8,8,16,4 +vfdotpex.ah.r.b,8,8,16,4 +vfndotpex.ah.b,8,8,16,4 +vfndotpex.ah.r.b,8,8,16,4 +vfsumex.h.ab,8,8,16,4 +vfnsumex.h.ab,8,8,16,4 +vfdotpex.h.ab,8,8,16,4 +vfdotpex.h.r.ab,8,8,16,4 +vfndotpex.h.ab,8,8,16,4 +vfndotpex.h.r.ab,8,8,16,4 +vfsumex.ah.ab,8,8,16,4 +vfnsumex.ah.ab,8,8,16,4 +vfdotpex.ah.ab,8,8,16,4 +vfdotpex.ah.r.ab,8,8,16,4 +vfndotpex.ah.ab,8,8,16,4 +vfndotpex.ah.r.ab,8,8,16,4