From c3d5d63ee9f17233daf62d459395a18d41f42c86 Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Thu, 7 Dec 2023 17:16:02 +0100
Subject: [PATCH] [tests] Add zfinx and zhinx hardware tests

---
 software/Makefile                             | 10 +-
 software/riscv-tests/isa/Makefile             |  9 +-
 .../isa/macros/scalar/test_macros.h           | 13 +++
 software/riscv-tests/isa/rv32ud/Makefrag      | 13 ---
 software/riscv-tests/isa/rv32uf/Makefrag      | 14 ---
 software/riscv-tests/isa/rv32uzfinx/Makefrag  | 16 ++++
 software/riscv-tests/isa/rv32uzfinx/fadd.S    | 41 ++++++++
 software/riscv-tests/isa/rv32uzfinx/fdiv.S    | 35 +++++++
 software/riscv-tests/isa/rv32uzfinx/fmadd.S   | 45 +++++++++
 software/riscv-tests/isa/rv32uzfinx/fmin.S    | 43 +++++++++
 software/riscv-tests/isa/rv32uzfinx/fsgnj.S   | 41 ++++++++
 software/riscv-tests/isa/rv32uzhinx/Makefrag  | 16 ++++
 software/riscv-tests/isa/rv32uzhinx/fadd_h.S  | 41 ++++++++
 software/riscv-tests/isa/rv32uzhinx/fdiv_h.S  | 35 +++++++
 software/riscv-tests/isa/rv32uzhinx/fmadd_h.S | 45 +++++++++
 software/riscv-tests/isa/rv32uzhinx/fmin_h.S  | 43 +++++++++
 software/riscv-tests/isa/rv32uzhinx/fsgnj_h.S | 41 ++++++++
 software/riscv-tests/isa/snitch_isa.mk        | 93 +++++++++++--------
 software/runtime/runtime.mk                   |  7 +-
 19 files changed, 528 insertions(+), 73 deletions(-)
 create mode 100644 software/riscv-tests/isa/rv32uzfinx/Makefrag
 create mode 100644 software/riscv-tests/isa/rv32uzfinx/fadd.S
 create mode 100644 software/riscv-tests/isa/rv32uzfinx/fdiv.S
 create mode 100644 software/riscv-tests/isa/rv32uzfinx/fmadd.S
 create mode 100644 software/riscv-tests/isa/rv32uzfinx/fmin.S
 create mode 100644 software/riscv-tests/isa/rv32uzfinx/fsgnj.S
 create mode 100644 software/riscv-tests/isa/rv32uzhinx/Makefrag
 create mode 100644 software/riscv-tests/isa/rv32uzhinx/fadd_h.S
 create mode 100644 software/riscv-tests/isa/rv32uzhinx/fdiv_h.S
 create mode 100644 software/riscv-tests/isa/rv32uzhinx/fmadd_h.S
 create mode 100644 software/riscv-tests/isa/rv32uzhinx/fmin_h.S
 create mode 100644 software/riscv-tests/isa/rv32uzhinx/fsgnj_h.S

diff --git a/software/Makefile b/software/Makefile
index 68d894491..f83402daa 100644
--- a/software/Makefile
+++ b/software/Makefile
@@ -35,7 +35,6 @@ clean-halide-apps:
 TESTS := $(addprefix bin/,$(rtl_mempool_tests))
 
 define rtl_mempool_tests_template
-
 TESTS_$(1) := $(addprefix bin/,$($(1)_mempool_tests))
 
 $$(TESTS_$(1)): bin/$(1)-mempool-%: $(TESTS_DIR)/$(1)/%.S $(LINKER_SCRIPT)
@@ -43,13 +42,20 @@ $$(TESTS_$(1)): bin/$(1)-mempool-%: $(TESTS_DIR)/$(1)/%.S $(LINKER_SCRIPT)
 	$$(RISCV_CC) $$(RISCV_CCFLAGS_TESTS) -T$$(RUNTIME_DIR)/link.ld $$< -o $$@
 	$$(RISCV_STRIP) $$@ -g -S -d --strip-debug
 	$$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $$@ > $$@.dump
-
 endef
 
+ifeq ($(COMPILER), llvm)
+$(eval $(call rtl_mempool_tests_template,rv32ui))
+$(eval $(call rtl_mempool_tests_template,rv32um))
+$(eval $(call rtl_mempool_tests_template,rv32ua))
+$(eval $(call rtl_mempool_tests_template,rv32uzfinx))
+$(eval $(call rtl_mempool_tests_template,rv32uzhinx))
+else
 $(eval $(call rtl_mempool_tests_template,rv32ui))
 $(eval $(call rtl_mempool_tests_template,rv32um))
 $(eval $(call rtl_mempool_tests_template,rv32ua))
 $(eval $(call rtl_mempool_tests_template,rv32uxpulpimg))
+endif
 
 test: update_opcodes $(TESTS)
 
diff --git a/software/riscv-tests/isa/Makefile b/software/riscv-tests/isa/Makefile
index 1a48c1048..2939c36a8 100644
--- a/software/riscv-tests/isa/Makefile
+++ b/software/riscv-tests/isa/Makefile
@@ -26,6 +26,8 @@ include $(src_dir)/rv32um/Makefrag
 include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32ud/Makefrag
+include $(src_dir)/rv32uzfinx/Makefrag
+include $(src_dir)/rv32uzhinx/Makefrag
 ifneq ($(COMPILER), llvm)
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
@@ -52,7 +54,7 @@ ifeq ($(COMPILER), llvm)
 	RISCV_TARGET ?= riscv$(XLEN)-unknown-elf
 	RISCV_LLVM_TARGET  ?= --target=$(RISCV_TARGET) --sysroot=$(GCC_INSTALL_DIR)/$(RISCV_TARGET) --gcc-toolchain=$(GCC_INSTALL_DIR)
 	RISCV_CC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RISCV_LLVM_TARGET)
-	RISCV_OBJDUMP_FLAGS += --mattr=+m,+a,+xpulpmacsi,+xpulppostmod,+xpulpvect,+xpulpvectshufflepack,+f
+	RISCV_OBJDUMP_FLAGS += --mattr=+m,+a,+f,+zfinx,+xpulpmacsi,+xpulppostmod,+xpulpvect,+xpulpvectshufflepack
 	RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump $(RISCV_OBJDUMP_FLAGS) --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
 else
 	# Default compilation with GCC
@@ -123,7 +125,10 @@ $(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
-RISCV_ARCH ?= rv$(XLEN)ima_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool
+RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zexpauxvechalfinx
+RISCV_ARCH := $(RISCV_ARCH)_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool
+$(eval $(call compile_template,rv32uzfinx,-march=$(RISCV_ARCH) -mabi=ilp32))
+$(eval $(call compile_template,rv32uzhinx,-march=$(RISCV_ARCH) -mabi=ilp32))
 $(eval $(call compile_template,rv32uxpulpimg,-march=$(RISCV_ARCH) -mabi=ilp32))
 else
 $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))
diff --git a/software/riscv-tests/isa/macros/scalar/test_macros.h b/software/riscv-tests/isa/macros/scalar/test_macros.h
index 90c897036..3cba7aaf8 100644
--- a/software/riscv-tests/isa/macros/scalar/test_macros.h
+++ b/software/riscv-tests/isa/macros/scalar/test_macros.h
@@ -496,6 +496,19 @@ test_ ## testnum: \
       inst x0, x1, x2; \
     )
 
+#-----------------------------------------------------------------------
+# Tests for instructions with 3 register operands & 1 dst register
+#-----------------------------------------------------------------------
+
+#define TEST_RRR_PLUSD_OP( testnum, inst, result, val1, val2, val3) \
+    TEST_CASE( testnum, x14, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      li x14, MASK_XLEN(val3); \
+      inst x14, x1, x2, x14; \
+    )
+
+
 #-----------------------------------------------------------------------
 # Tests for Xpulpimg instructions with 2 register operands (rd and rs1)
 # and a 6-bit unsigned immediate input
diff --git a/software/riscv-tests/isa/rv32ud/Makefrag b/software/riscv-tests/isa/rv32ud/Makefrag
index 3eb73e803..28b00f091 100644
--- a/software/riscv-tests/isa/rv32ud/Makefrag
+++ b/software/riscv-tests/isa/rv32ud/Makefrag
@@ -2,7 +2,6 @@
 # Makefrag for rv32ud tests
 #-----------------------------------------------------------------------
 
-ifeq ($(COMPILER), llvm)
 rv32ud_sc_tests = fadd \
                   fdiv \
                   fclass \
@@ -13,18 +12,6 @@ rv32ud_sc_tests = fadd \
                   fmin \
                   ldst \
                   recoding
-else
-rv32ud_sc_tests = fadd \
-                  fdiv \
-                  fclass \
-                  fcmp \
-                  fcvt \
-                  fcvt_w \
-                  fmadd \
-                  fmin \
-                  ldst \
-                  recoding
-endif
 
 # TODO: use this line instead of the last of the previous once move and structural tests have been implemented
 #        ldst move structural recoding \
diff --git a/software/riscv-tests/isa/rv32uf/Makefrag b/software/riscv-tests/isa/rv32uf/Makefrag
index 1548a1c37..bdf218d2b 100644
--- a/software/riscv-tests/isa/rv32uf/Makefrag
+++ b/software/riscv-tests/isa/rv32uf/Makefrag
@@ -2,19 +2,6 @@
 # Makefrag for rv32uf tests
 #-----------------------------------------------------------------------
 
-ifeq ($(COMPILER), llvm)
-rv32uf_sc_tests = fadd \
-                  fdiv \
-                  fclass \
-                  fcmp \
-                  fcvt \
-                  fcvt_w \
-                  fmadd \
-                  fmin \
-                  ldst \
-                  move \
-                  recoding
-else
 rv32uf_sc_tests = fadd \
                   fdiv \
                   fclass \
@@ -26,7 +13,6 @@ rv32uf_sc_tests = fadd \
                   ldst \
                   move \
                   recoding
-endif
 
 rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
 rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
diff --git a/software/riscv-tests/isa/rv32uzfinx/Makefrag b/software/riscv-tests/isa/rv32uzfinx/Makefrag
new file mode 100644
index 000000000..c1983f410
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzfinx/Makefrag
@@ -0,0 +1,16 @@
+#=======================================================================
+# Makefrag for rv32uzfinx tests
+#-----------------------------------------------------------------------
+
+ifeq ($(COMPILER), llvm)
+rv32uzfinx_sc_tests = \
+                      fadd \
+                      fdiv \
+                      fmadd \
+                      fmin \
+                      fsgnj
+endif
+
+rv32uzfinx_p_tests = $(addprefix rv32uzfinx-p-, $(rv32uzfinx_sc_tests))
+
+# Zfinx extensions are not tested on Spike
diff --git a/software/riscv-tests/isa/rv32uzfinx/fadd.S b/software/riscv-tests/isa/rv32uzfinx/fadd.S
new file mode 100644
index 000000000..89b6a99ea
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzfinx/fadd.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fadd.s, 0x40600000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 3,  fadd.s, 0xC49A4000, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 4,  fadd.s, 0x40490FDB, 0x40490FDB, 0x322BCC77 );
+
+  TEST_RR_OP( 5,  fsub.s, 0x3FC00000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 6,  fsub.s, 0xC49A4000, 0xC49A6333, 0xBF8CCCCD );
+  TEST_RR_OP( 7,  fsub.s, 0x40490FDB, 0x40490FDB, 0x322BCC77 );
+
+  TEST_RR_OP( 8,  fmul.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 9,  fmul.s, 0x44A9D385, 0xC49A6333, 0xBF8CCCCD );
+  TEST_RR_OP(10,  fmul.s, 0x3306EE2D, 0x40490FDB, 0x322BCC77 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzfinx/fdiv.S b/software/riscv-tests/isa/rv32uzfinx/fdiv.S
new file mode 100644
index 000000000..ceec8b049
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzfinx/fdiv.S
@@ -0,0 +1,35 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fdiv.s, 0x3F93EEE0, 0x40490FDB, 0x402DF854 );
+  TEST_RR_OP( 3,  fdiv.s, 0xBF7FC5A2, 0xC49A4000, 0x449A6333 );
+  TEST_RR_OP( 4,  fdiv.s, 0x40490FDB, 0x40490FDB, 0x3F800000 );
+
+  TEST_R_OP( 5,  fsqrt.s, 0x3FE2DFC5, 0x40490FDB );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzfinx/fmadd.S b/software/riscv-tests/isa/rv32uzfinx/fmadd.S
new file mode 100644
index 000000000..9e55ace44
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzfinx/fmadd.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RRR_PLUSD_OP( 2,  fmadd.s, 0x40600000, 0x3F800000, 0x40200000, 0x3F800000 ); #   3.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 3,  fmadd.s, 0x449A8666, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); #1236.2, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 4,  fmadd.s, 0xC1400000, 0x40000000, 0xC0A00000, 0xC0000000 ); # -12.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 5,  fnmadd.s, 0xC0600000, 0x3F800000, 0x40200000, 0x3F800000 ); #   -3.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 6,  fnmadd.s, 0xC49A8666, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); #-1236.2, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 7,  fnmadd.s, 0x41400000, 0x40000000, 0xC0A00000, 0xC0000000 ); #   12.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 8,  fmsub.s, 0x3FC00000, 0x3F800000, 0x40200000, 0x3F800000 ); #   -1.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 9,  fmsub.s, 0x449A4000, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); # 1234.0, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 10,  fmsub.s, 0xC1000000, 0x40000000, 0xC0A00000, 0xC0000000 ); #   -8.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 11,  fnmsub.s, 0xBFC00000, 0x3F800000, 0x40200000, 0x3F800000 ); #   -1.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 12,  fnmsub.s, 0xC49A4000, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); #-1234.0, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 13,  fnmsub.s, 0x41000000, 0x40000000, 0xC0A00000, 0xC0000000 ); #    8.0,  2.0,    -5.0, -2.0
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzfinx/fmin.S b/software/riscv-tests/isa/rv32uzfinx/fmin.S
new file mode 100644
index 000000000..a9106a4da
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzfinx/fmin.S
@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fmin.s, 0x3F800000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 3,  fmin.s, 0xC49A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 4,  fmin.s, 0xC49A6333, 0x3F8CCCCD, 0xC49A6333 );
+  TEST_RR_OP( 5,  fmin.s, 0xC49A6333, 0x7FC00000, 0xC49A6333 );
+  TEST_RR_OP( 6,  fmin.s, 0x322BCC77, 0x40490FDB, 0x322BCC77 );
+  TEST_RR_OP( 7,  fmin.s, 0xC0000000, 0xBF800000, 0xC0000000 );
+
+  TEST_RR_OP( 8,  fmax.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 9,  fmax.s, 0x3F8CCCCD, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP(10,  fmax.s, 0x3F8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+  TEST_RR_OP(11,  fmax.s, 0xC49A6333, 0x7FC00000, 0xC49A6333 );
+  TEST_RR_OP(12,  fmax.s, 0x40490FDB, 0x40490FDB, 0x322BCC77 );
+  TEST_RR_OP(13,  fmax.s, 0xBF800000, 0xBF800000, 0xC0000000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzfinx/fsgnj.S b/software/riscv-tests/isa/rv32uzfinx/fsgnj.S
new file mode 100644
index 000000000..d751f680c
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzfinx/fsgnj.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fsgnj.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fsgnj.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 3,  fsgnj.s, 0x449A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 4,  fsgnj.s, 0xBF8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+
+  TEST_RR_OP( 5,  fsgnjn.s, 0xC0200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 6,  fsgnjn.s, 0xC49A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 7,  fsgnjn.s, 0x3F8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+
+  TEST_RR_OP( 8,  fsgnjx.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 9,  fsgnjx.s, 0xC49A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP(10,  fsgnjx.s, 0xBF8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzhinx/Makefrag b/software/riscv-tests/isa/rv32uzhinx/Makefrag
new file mode 100644
index 000000000..30a6a9141
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzhinx/Makefrag
@@ -0,0 +1,16 @@
+#=======================================================================
+# Makefrag for rv32uzfinx tests
+#-----------------------------------------------------------------------
+
+ifeq ($(COMPILER), llvm)
+rv32uzhinx_sc_tests = \
+                      fadd_h \
+                      fdiv_h \
+                      fmadd_h \
+                      fmin_h \
+                      fsgnj_h
+endif
+
+rv32uzhinx_p_tests = $(addprefix rv32uzhinx-p-, $(rv32uzhinx_sc_tests))
+
+# Zhinx extensions are not tested on Spike
diff --git a/software/riscv-tests/isa/rv32uzhinx/fadd_h.S b/software/riscv-tests/isa/rv32uzhinx/fadd_h.S
new file mode 100644
index 000000000..7c502c0ac
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzhinx/fadd_h.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fadd.h, 0xFFFF4300, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 3,  fadd.h, 0xFFFFE4D2, 0xFFFFE4D3, 0xFFFF3C66 );
+  TEST_RR_OP( 4,  fadd.h, 0xFFFF4248, 0xFFFF4248, 0xFFFF0000 );
+
+  TEST_RR_OP( 5,  fsub.h, 0xFFFF3E00, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 6,  fsub.h, 0xFFFFE4D2, 0xFFFFE4D3, 0xFFFFBC66 );
+  TEST_RR_OP( 7,  fsub.h, 0xFFFF4248, 0xFFFF4248, 0xFFFF0000 );
+
+  TEST_RR_OP( 8,  fmul.h, 0xFFFF4100, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 9,  fmul.h, 0xFFFF654E, 0xFFFFE4D3, 0xFFFFBC66 );
+  TEST_RR_OP(10,  fmul.h, 0xFFFF0000, 0xFFFF4248, 0xFFFF0000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzhinx/fdiv_h.S b/software/riscv-tests/isa/rv32uzhinx/fdiv_h.S
new file mode 100644
index 000000000..0ecf0a986
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzhinx/fdiv_h.S
@@ -0,0 +1,35 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  #TEST_RR_OP( 2,  fdiv.h, 0xFFFF3C9F, 0xFFFF4248, 0xFFFF416F );
+  TEST_RR_OP( 3,  fdiv.h, 0xFFFFBBFE, 0xFFFFE4D2, 0xFFFF64D3 );
+  TEST_RR_OP( 4,  fdiv.h, 0xFFFF4248, 0xFFFF4248, 0xFFFF3C00 );
+
+  TEST_R_OP( 5,  fsqrt.h, 0xFFFF4700, 0xFFFF5220 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzhinx/fmadd_h.S b/software/riscv-tests/isa/rv32uzhinx/fmadd_h.S
new file mode 100644
index 000000000..98ed9e08e
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzhinx/fmadd_h.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RRR_PLUSD_OP( 2,  fmadd.h, 0xFFFF4300, 0xFFFF3C00, 0xFFFF4100, 0xFFFF3C00 ); #   3.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 3,  fmadd.h, 0xFFFF64D4, 0xFFFFBC00, 0xFFFFE4D3, 0xFFFF3C66 ); #1236.2, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 4,  fmadd.h, 0xFFFFCA00, 0xFFFF4000, 0xFFFFC500, 0xFFFFC000 ); # -12.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 5,  fnmadd.h, 0xFFFFC300, 0xFFFF3C00, 0xFFFF4100, 0xFFFF3C00 ); #   -3.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 6,  fnmadd.h, 0xFFFFE4D4, 0xFFFFBC00, 0xFFFFE4D3, 0xFFFF3C66 ); #-1236.2, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 7,  fnmadd.h, 0xFFFF4A00, 0xFFFF4000, 0xFFFFC500, 0xFFFFC000 ); #   12.0,  2.0,    -5.0, -2.0
+
+  #TEST_RRR_PLUSD_OP( 8,  fmsub.h, 0xFFFFBE00, 0xFFFF3C00, 0xFFFF4100, 0xFFFF3C00 ); #   -1.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 9,  fmsub.h, 0xFFFF64D2, 0xFFFFBC00, 0xFFFFE4D3, 0xFFFF3C66 ); # 1234.0, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP(10,  fmsub.h, 0xFFFFC800, 0xFFFF4000, 0xFFFFC500, 0xFFFFC000 ); #   -8.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP(11,  fnmsub.h, 0xFFFFBE00, 0xFFFF3C00, 0xFFFF4100, 0xFFFF3C00 ); #   -1.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP(12,  fnmsub.h, 0xFFFFE4D2, 0xFFFFBC00, 0xFFFFE4D3, 0xFFFF3C66 ); #-1234.0, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP(13,  fnmsub.h, 0xFFFF4800, 0xFFFF4000, 0xFFFFC500, 0xFFFFC000 ); #    8.0,  2.0,    -5.0, -2.0
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzhinx/fmin_h.S b/software/riscv-tests/isa/rv32uzhinx/fmin_h.S
new file mode 100644
index 000000000..c06cddcf8
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzhinx/fmin_h.S
@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fmin.h, 0xFFFF3C00, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 3,  fmin.h, 0xFFFFE4D3, 0xFFFFE4D3, 0xFFFF3C66 );
+  TEST_RR_OP( 4,  fmin.h, 0xFFFFE4D3, 0xFFFF3C66, 0xFFFFE4D3 );
+  TEST_RR_OP( 5,  fmin.h, 0xFFFFE4D3, 0xFFFF7E00, 0xFFFFE4D3 );
+  TEST_RR_OP( 6,  fmin.h, 0xFFFF0000, 0xFFFF4248, 0xFFFF0000 );
+  TEST_RR_OP( 7,  fmin.h, 0xFFFFC000, 0xFFFFBC00, 0xFFFFC000 );
+
+  TEST_RR_OP( 8,  fmax.h, 0xFFFF4100, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 9,  fmax.h, 0xFFFF3C66, 0xFFFFE4D3, 0xFFFF3C66 );
+  TEST_RR_OP(10,  fmax.h, 0xFFFF3C66, 0xFFFF3C66, 0xFFFFE4D3 );
+  TEST_RR_OP(11,  fmax.h, 0xFFFFE4D3, 0xFFFF7E00, 0xFFFFE4D3 );
+  TEST_RR_OP(12,  fmax.h, 0xFFFF4248, 0xFFFF4248, 0xFFFF0000 );
+  TEST_RR_OP(13,  fmax.h, 0xFFFFBC00, 0xFFFFBC00, 0xFFFFC000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/rv32uzhinx/fsgnj_h.S b/software/riscv-tests/isa/rv32uzhinx/fsgnj_h.S
new file mode 100644
index 000000000..a186e2a35
--- /dev/null
+++ b/software/riscv-tests/isa/rv32uzhinx/fsgnj_h.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fsgnj.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fsgnj.h, 0xFFFF4100, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 3,  fsgnj.h, 0xFFFF64D3, 0xFFFFE4D3, 0xFFFF3C66 );
+  TEST_RR_OP( 4,  fsgnj.h, 0xFFFFBC66, 0xFFFF3C66, 0xFFFFE4D3 );
+
+  TEST_RR_OP( 5,  fsgnjn.h, 0xFFFFC100, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 6,  fsgnjn.h, 0xFFFFE4D3, 0xFFFFE4D3, 0xFFFF3C66 );
+  TEST_RR_OP( 7,  fsgnjn.h, 0xFFFF3C66, 0xFFFF3C66, 0xFFFFE4D3 );
+
+  TEST_RR_OP( 8,  fsgnjx.h, 0xFFFF4100, 0xFFFF4100, 0xFFFF3C00 );
+  TEST_RR_OP( 9,  fsgnjx.h, 0xFFFFE4D3, 0xFFFFE4D3, 0xFFFF3C66 );
+  TEST_RR_OP(10,  fsgnjx.h, 0xFFFFBC66, 0xFFFF3C66, 0xFFFFE4D3 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/software/riscv-tests/isa/snitch_isa.mk b/software/riscv-tests/isa/snitch_isa.mk
index 072d9cae5..3bd7cb8bb 100644
--- a/software/riscv-tests/isa/snitch_isa.mk
+++ b/software/riscv-tests/isa/snitch_isa.mk
@@ -29,6 +29,38 @@ rv32um_snitch_sc_tests = \
 	mul mulh mulhsu mulhu \
 	rem remu \
 
+# rv32si_snitch_sc_tests = \
+# 	csr \
+# 	dirty \
+# 	ma_fetch \
+# 	scall \
+# 	sbreak \
+# 	wfi \
+
+# rv32mi_snitch_sc_tests = \
+# 	breakpoint \
+# 	csr \
+# 	mcsr \
+# 	illegal \
+# 	ma_fetch \
+# 	ma_addr \
+# 	scall \
+# 	sbreak \
+# 	shamt \
+
+rv32ui_mempool_tests = $(addprefix rv32ui-mempool-, $(rv32ui_snitch_sc_tests))
+rv32ua_mempool_tests = $(addprefix rv32ua-mempool-, $(rv32ua_snitch_sc_tests))
+rv32um_mempool_tests = $(addprefix rv32um-mempool-, $(rv32um_snitch_sc_tests))
+# rv32si_mempool_tests = $(addprefix rv32si-mempool-, $(rv32si_snitch_sc_tests))
+# rv32mi_mempool_tests = $(addprefix rv32mi-mempool-, $(rv32mi_snitch_sc_tests))
+
+rtl_mempool_tests = $(rv32ui_mempool_tests)
+rtl_mempool_tests += $(rv32ua_mempool_tests)
+rtl_mempool_tests += $(rv32um_mempool_tests)
+#rtl_mempool_tests += $(rv32si_mempool_tests)
+#rtl_mempool_tests += $(rv32mi_mempool_tests)
+
+ifneq ($(COMPILER), llvm)
 ifeq ($(xpulpimg),1)
 
 	rv32uxpulpimg_snitch_sc_tests = \
@@ -70,49 +102,32 @@ ifeq ($(xpulpimg),1)
 		pv_sdotsp \
 		pv_shuffle2 \
 		pv_pack \
-		pv_pack_h \
+		pv_pack_h
+	rv32uxpulpimg_mempool_tests = $(addprefix rv32uxpulpimg-mempool-, $(rv32uxpulpimg_snitch_sc_tests))
+	rtl_mempool_tests += $(rv32uxpulpimg_mempool_tests)
 
 endif
+endif
 
-# rv32si_snitch_sc_tests = \
-# 	csr \
-# 	dirty \
-# 	ma_fetch \
-# 	scall \
-# 	sbreak \
-# 	wfi \
+ifeq ($(COMPILER), llvm)
+ifeq ($(zfinx_rv),1)
 
-# rv32mi_snitch_sc_tests = \
-# 	breakpoint \
-# 	csr \
-# 	mcsr \
-# 	illegal \
-# 	ma_fetch \
-# 	ma_addr \
-# 	scall \
-# 	sbreak \
-# 	shamt \
+	rv32uzfinx_snitch_sc_tests = \
+		fadd \
+		fdiv \
+		fmadd \
+		fmin \
+		fsgnj
+	rv32uzhinx_snitch_sc_tests = \
+		fadd_h \
+		fdiv_h \
+		fmadd_h \
+		fmin_h \
+		fsgnj_h
+	rv32uzfinx_mempool_tests = $(addprefix rv32uzfinx-mempool-, $(rv32uzfinx_snitch_sc_tests))
+	rv32uzhinx_mempool_tests = $(addprefix rv32uzhinx-mempool-, $(rv32uzhinx_snitch_sc_tests))
+	rtl_mempool_tests += $(rv32uzfinx_mempool_tests)
+	rtl_mempool_tests += $(rv32uzhinx_mempool_tests)
 
-ifeq (COMPILER, llvm)
-	RISCV_ARCH = mempool
-else
-	RISCV_ARCH = mempool-rv32
-endif
-rv32ui_mempool_tests = $(addprefix rv32ui-$(RISCV_ARCH)-, $(rv32ui_snitch_sc_tests))
-rv32ua_mempool_tests = $(addprefix rv32ua-$(RISCV_ARCH)-, $(rv32ua_snitch_sc_tests))
-rv32um_mempool_tests = $(addprefix rv32um-$(RISCV_ARCH)-, $(rv32um_snitch_sc_tests))
-ifeq ($(xpulpimg),1)
-	rv32uxpulpimg_mempool_tests = $(addprefix rv32uxpulpimg-$(RISCV_ARCH)-, $(rv32uxpulpimg_snitch_sc_tests))
 endif
-# rv32si_mempool_tests = $(addprefix rv32si-$(RISCV_ARCH)-, $(rv32si_snitch_sc_tests))
-# rv32mi_mempool_tests = $(addprefix rv32mi-$(RISCV_ARCH)-, $(rv32mi_snitch_sc_tests))
-
-rtl_mempool_tests = \
-	$(rv32ui_$(RISCV_ARCH)_tests) \
-	$(rv32ua_$(RISCV_ARCH)_tests) \
-	$(rv32um_$(RISCV_ARCH)_tests)
-#	$(rv32si_$(RISCV_ARCH)_tests) \
-#	$(rv32mi_$(RISCV_ARCH)_tests)
-ifeq ($(xpulpimg),1)
-	rtl_mempool_tests += $(rv32uxpulpimg_$(RISCV_ARCH)_tests)
 endif
diff --git a/software/runtime/runtime.mk b/software/runtime/runtime.mk
index 96d25aba9..7ecb4e544 100644
--- a/software/runtime/runtime.mk
+++ b/software/runtime/runtime.mk
@@ -114,11 +114,15 @@ ifeq ($(COMPILER),gcc)
 	RISCV_CXXFLAGS      += $(RISCV_CCFLAGS)
 	RISCV_LDFLAGS       += -static -nostartfiles -lm -lgcc $(RISCV_FLAGS_GCC) $(RISCV_FLAGS_COMMON) -L$(ROOT_DIR)
 	RISCV_OBJDUMP_FLAGS += --disassembler-option="march=$(RISCV_ARCH_AS)"
+	# For unit tests
+	RISCV_CCFLAGS_TESTS ?= $(RISCV_FLAGS_GCC) $(RISCV_FLAGS_COMMON_TESTS) -fvisibility=hidden -nostdlib $(RISCV_LDFLAGS)
 else
 	RISCV_CCFLAGS       += $(RISCV_LLVM_TARGET) $(RISCV_FLAGS_LLVM) $(RISCV_FLAGS_COMMON)
 	RISCV_CXXFLAGS      += $(RISCV_CCFLAGS)
 	RISCV_LDFLAGS       += -static -nostartfiles -lm -lgcc -mcmodel=small $(RISCV_LLVM_TARGET) $(RISCV_FLAGS_COMMON) -L$(ROOT_DIR)
 	RISCV_OBJDUMP_FLAGS += --mcpu=mempool-rv32 --mattr=+m,+a,+xpulpmacsi,+xpulppostmod,+xpulpvect,+xpulpvectshufflepack,+zfinx
+	# For unit tests
+	RISCV_CCFLAGS_TESTS ?= $(RISCV_FLAGS_LLVM) $(RISCV_FLAGS_COMMON_TESTS) -fvisibility=hidden -nostdlib $(RISCV_LDFLAGS)
 endif
 
 LINKER_SCRIPT ?= $(ROOT_DIR)/arch.ld
@@ -132,9 +136,6 @@ RUNTIME += $(ROOT_DIR)/synchronization.c.o
 
 OMP_RUNTIME := $(addsuffix .o,$(shell find $(OMP_DIR) -name "*.c"))
 
-# For unit tests
-RISCV_CCFLAGS_TESTS ?= $(RISCV_FLAGS_GCC) $(RISCV_FLAGS_COMMON_TESTS) -fvisibility=hidden -nostdlib $(RISCV_LDFLAGS)
-
 .INTERMEDIATE: $(RUNTIME) $(OMP_RUNTIME) $(LINKER_SCRIPT)
 # Disable builtin rules
 .SUFFIXES: