axi_to_mem: Comb path from b_ready to w_ready

[niwis]

There is a combinational path in axi_to_mem from axi_req_i.b_ready to axi_resp_o.w_ready. In particular, this is can be dangerous when connecting this module downstream of axi_dw_downsize, which has a comb path from w_ready to b_ready, resulting in a combinational loop.

[christian-lanius]

Is there a workaround to this issue?
I have something along the lines:
AXI_UPSIZE -> AXI_MUX -> AXI_TO_MEM -> SRAM
and observe the combinational loop. I have tried to insert a AXI_CUT block after the AXI_MUX block, but this does not help.
I have parameterized the block with
NumBanks=1
BufDepth=1 (SRAM has latency of 1 cycle)
HideStrb=1
OutFifoDepth=1

Does any of the other axi_to_mem blocks (interleaved, split etc) not exhibit this problem?

[xXIty]

Same here... I think the trick is to register both sides of the module. For instance, place an axi_cut in one side and ensure the mem side is not answered combinationally.