From 7486028dabcbd140343868e7b0c6eb19788cc384 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 03:29:06 -0500 Subject: [PATCH 001/148] ignore build folder --- .gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..796b96d --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/build From 39ab9ce9c5af51ce8d1f6e058f907fafc625d75a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 03:30:05 -0500 Subject: [PATCH 002/148] Plan: replace object files in libbl602_wifi one by one --- CMakeLists.txt | 12 ++++++ src/bl602_wifi/CMakeLists.txt | 27 +++++++++++++ src/bl602_wifi/phy_bl602.c | 71 +++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 CMakeLists.txt create mode 100644 src/bl602_wifi/CMakeLists.txt create mode 100644 src/bl602_wifi/phy_bl602.c diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..5c60843 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,12 @@ +cmake_minimum_required(VERSION 3.14.0) +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR riscv) +SET(CMAKE_CROSSCOMPILING 1) +set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") + + +project(bl602_re VERSION 0.1.0) + +include_directories(./src/include) + +add_subdirectory(./src/bl602_wifi) diff --git a/src/bl602_wifi/CMakeLists.txt b/src/bl602_wifi/CMakeLists.txt new file mode 100644 index 0000000..3a5e008 --- /dev/null +++ b/src/bl602_wifi/CMakeLists.txt @@ -0,0 +1,27 @@ + + +file(GLOB bl602_wifi_original_OBJs +"${PROJECT_SOURCE_DIR}/libbl602_wifi/*.o" +) + +file(GLOB bl602_wifi_SRCs +"*.c" +) + +foreach(blsrc ${bl602_wifi_SRCs}) + get_filename_component(wle ${blsrc} NAME_WLE) + list(APPEND NEEDREMOVE ${wle}) +endforeach() + +foreach(blobj ${bl602_wifi_original_OBJs}) + get_filename_component(wle ${blobj} NAME_WLE) + list(APPEND bl602_wifi_OBJs ${wle}) +endforeach() + +list(REMOVE_ITEM bl602_wifi_OBJs ${NEEDREMOVE}) +list(TRANSFORM bl602_wifi_OBJs PREPEND "${PROJECT_SOURCE_DIR}/libbl602_wifi/") +list(TRANSFORM bl602_wifi_OBJs APPEND ".o") + + +add_library(bl602_wifi STATIC ${bl602_wifi_SRCs} ${bl602_wifi_OBJs}) + diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/phy_bl602.c new file mode 100644 index 0000000..027d385 --- /dev/null +++ b/src/bl602_wifi/phy_bl602.c @@ -0,0 +1,71 @@ +#include +#include +#include + +struct phy_bl602_cfg_tag { + uint32_t reserved; +}; // :48:8 + +struct phy_channel_info +{ + /// PHY channel information 1 + uint32_t info1; + /// PHY channel information 2 + uint32_t info2; +}; + +struct phy_env_tag { + struct phy_bl602_cfg_tag cfg; + uint16_t chnl_prim20_freq; + uint16_t chnl_center1_freq; + uint16_t chnl_center2_freq; + uint8_t band; + uint8_t chnl_type; +}; // :54:8 + +struct phy_env_tag phy_env[1]; // :75:20 +static int8_t rxgain_offset_vs_temperature; // :79:15 +static int8_t poweroffset[14]; // :80:15 + +void phy_config_rxgain(int offset) { + if (rxgain_offset_vs_temperature != offset) { + rxgain_offset_vs_temperature = (int8_t) offset; + AGC->rxgain_offset_vs_temperature[0] = (int)rxgain_offset_vs_temperature + 3; + AGC->rxgain_offset_vs_temperature[1] = (int)rxgain_offset_vs_temperature + 11; + AGC->rxgain_offset_vs_temperature[2] = (int)rxgain_offset_vs_temperature + 18; + AGC->rxgain_offset_vs_temperature[3] = (int)rxgain_offset_vs_temperature + 25; + AGC->rxgain_offset_vs_temperature[4] = (int)rxgain_offset_vs_temperature + 32; + AGC->rxgain_offset_vs_temperature[5] = (int)rxgain_offset_vs_temperature + 39; + AGC->rxgain_offset_vs_temperature[6] = (int)rxgain_offset_vs_temperature + 45; + AGC->rxgain_offset_vs_temperature[7] = (int)rxgain_offset_vs_temperature + 53; + AGC->rxgain_offset_vs_temperature[8] = (int)rxgain_offset_vs_temperature + 59; + } +} + +void phy_get_channel(struct phy_channel_info *info, uint8_t index) { + info->info1 = (uint32_t)phy_env[0].chnl_type << 8 | (uint32_t)phy_env[0].chnl_prim20_freq << 16 | + (uint32_t)phy_env[0].band; + info->info2 = phy_env[0].chnl_center1_freq | ((uint32_t)phy_env[0].chnl_center2_freq << 16); +} + +uint8_t phy_get_mac_freq(void) { + return 0x28; +} + +uint8_t phy_get_nss(void) { + return (uint8_t)(( (int8_t)(MDM->version.nss & 0xf) )- 1); +} + +void phy_get_version(uint32_t *version_1,uint32_t *version_2) { + *version_1 = MDM->version.value; + *version_2 = 0; + return; +} + +void agc_config(void) { + AGC->RWNXAGCCNTL.set_0x0_0 = 0; + AGC->RWNXAGCCNTL.set_0x0_1 = 0; + AGC->r0xb3a4.set_0x0_2 = 0; + AGC->r0xb3a4.set_0x0_3 = 0; + +} From d17771e34c7ed81c603f7e22f6d24c4fc8385740 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 03:36:24 -0500 Subject: [PATCH 003/148] return field after added --- script/reglib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/script/reglib.py b/script/reglib.py index b2fb4ce..9e4d505 100755 --- a/script/reglib.py +++ b/script/reglib.py @@ -281,7 +281,7 @@ def Goto(addr): def Field(name, mask): if context.r: - context.r.addField(name, mask) + return context.r.addField(name, mask) else: print("You are not in any register") From 80db0accad7894cc0a64ca2ac50bdf53da08ca34 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 04:02:26 -0500 Subject: [PATCH 004/148] add more reg from phy_bl602.o --- script/manualext.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 96adaf8..80781ee 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -13,7 +13,6 @@ Field('vht', 0xfffffffd) # very high throughput Field('v31', 0xfffeffff) # some switch? DAT_44c00000>>31 - Reg('rxchan', 0x44c00820) Field('rxcbwmax', 0xfcffffff) # Channel bandwidth Field('rxnssmax', 0xffffff8f) # number of spatial streams @@ -29,11 +28,14 @@ FieldBit('rxndpnstsmax', 0xc, 4) FieldBit('v18', 0x12) FieldBit('v19', 0x13) -FieldBit('v30', 0x1e) -FieldBit('v31', 0x1f) +FieldBit('mu_mimo_rx', 0x1e) +FieldBit('mu_mimo_tx', 0x1f) FieldBit('ldpctx', 0x1a) +FieldBit('ldpcrx', 0x1b) FieldBit('ntx', 4, 4) # phy_get_ntx (ntx + 1) FieldBit('txcbwmax', 0x18, 2) +FieldBit('bfmee_supported', 0x1c) +FieldBit('bfmer_supported', 0x1d) Reg('mdmconf', 0x44c00800) From fed3a5aaa58d91dd88eb40e0276181ebc802c416 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 04:03:31 -0500 Subject: [PATCH 005/148] update mdm.h with regs found in phy_bl602.o --- src/include/phy/mdm.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index a57d99b..9ce4863 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -17,9 +17,11 @@ typedef union { uint32_t pad3 : 1; uint32_t txcbwmax : 2; // @ 25 -- 24 # 0xfcffffff uint32_t ldpctx : 1; // @ 26 -- 26 # 0xfbffffff - uint32_t pad4 : 3; - uint32_t v30 : 1; // @ 30 -- 30 # 0xbfffffff - uint32_t v31 : 1; // @ 31 -- 31 # 0x7fffffff + uint32_t ldpcrx : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t bfmee_supported : 1; // @ 28 -- 28 # 0xefffffff + uint32_t bfmer_supported : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t mu_mimo_rx : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t mu_mimo_tx : 1; // @ 31 -- 31 # 0x7fffffff }; } version; // @ 0x0 uint8_t pad0[0x7fc]; From 8898ba599e2b1b045c21537970d0e4c79d5a60e9 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 05:11:03 -0500 Subject: [PATCH 006/148] add missing bit --- script/manualext.py | 1 + 1 file changed, 1 insertion(+) diff --git a/script/manualext.py b/script/manualext.py index 80781ee..2a182fd 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -21,6 +21,7 @@ Field('vht', 0xfffffffd) # very high throughput Field('v30', 0xfffeffff) # some switch? DAT_44c00000>>30 Field('_v30', 0xffefffff) # some switch? DAT_44c00000>>30 +FieldBit('reset', 0) # set 1 in phy_hw_set_channel for.. reset? Reg('version', 0x44c00000) FieldBit('vht', 31-9) From 2a14d5a1ddb74841275195f182ba2603a2e6e0be Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 05:11:19 -0500 Subject: [PATCH 007/148] add bit --- src/include/phy/mdm.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index 9ce4863..ebb7e60 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -49,17 +49,17 @@ typedef union { union { uint32_t value; struct { - uint32_t pad0 : 1; + uint32_t reset : 1; // @ 0 -- 0 # 0xfffffffe uint32_t vht : 1; // @ 1 -- 1 # 0xfffffffd - uint32_t pad1 : 2; + uint32_t pad0 : 2; uint32_t rxnssmax : 3; // @ 6 -- 4 # 0xffffff8f - uint32_t pad2 : 1; + uint32_t pad1 : 1; uint32_t v19 : 1; // @ 8 -- 8 # 0xfffffeff - uint32_t pad3 : 7; + uint32_t pad2 : 7; uint32_t v30 : 1; // @ 16 -- 16 # 0xfffeffff - uint32_t pad4 : 3; + uint32_t pad3 : 3; uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff - uint32_t pad5 : 3; + uint32_t pad4 : 3; uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff }; } rxchan; // @ 0x820 From b778274b6f628e3a810eaacdcb1b7c183399a7fa Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 05:47:51 -0500 Subject: [PATCH 008/148] add missing rxndpnstsmax --- script/manualext.py | 1 + src/include/phy/mdm.h | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 2a182fd..9dc38ac 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -22,6 +22,7 @@ Field('v30', 0xfffeffff) # some switch? DAT_44c00000>>30 Field('_v30', 0xffefffff) # some switch? DAT_44c00000>>30 FieldBit('reset', 0) # set 1 in phy_hw_set_channel for.. reset? +Field('rxndpnstsmax', 0xffff8fff) Reg('version', 0x44c00000) FieldBit('vht', 31-9) diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index ebb7e60..8bdd17f 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -55,11 +55,13 @@ typedef union { uint32_t rxnssmax : 3; // @ 6 -- 4 # 0xffffff8f uint32_t pad1 : 1; uint32_t v19 : 1; // @ 8 -- 8 # 0xfffffeff - uint32_t pad2 : 7; + uint32_t pad2 : 3; + uint32_t rxndpnstsmax : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; uint32_t v30 : 1; // @ 16 -- 16 # 0xfffeffff - uint32_t pad3 : 3; - uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff uint32_t pad4 : 3; + uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad5 : 3; uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff }; } rxchan; // @ 0x820 From 427e66d192e82e1ab654377ddd7c9dd9c3544c1f Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 06:35:36 -0500 Subject: [PATCH 009/148] generate agc code automatically --- script/manualext.py | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 9dc38ac..f81e071 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -159,11 +159,15 @@ def scan_write(code): name_f = f'set_{hex(value)}_{gid}' name_r = f'r{hex(addr&0xffff)}' gid = gid + 1 - Reg(name_r, addr) - Field(name_f, mask) - -scan_write(open('../blobs/agc_config.c').readlines()) -scan_write([ + r = Reg(name_r, addr) + f = Field(name_f, mask) + yield r.name, f.name, value + +print("agc_config") +for rn, fn, val in scan_write(open('../blobs/agc_config.c').readlines()): + print(f"AGC->{rn}.{fn} = {hex(val)}") +print("ex") +for rn, fn, val in scan_write([ "write_volatile_4(DAT_44c0c020,uVar4 & 0xfc00ffff | 0x140000);", "write_volatile_4(DAT_44c0b390,uVar1 & 0xfffffeff);", "write_volatile_4(DAT_44c0b500,uVar4 & 0xffffcfff | 0x2000);", @@ -171,7 +175,8 @@ def scan_write(code): "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffb);", "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffd);", "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffe);", -]) +]): + print(f"AGC->{rn}.{fn} = {hex(val)}") open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) From 1eda44aa7fc7c170e19c6b80281d86aa85970229 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 06:36:09 -0500 Subject: [PATCH 010/148] add used functions in header --- src/bl602_wifi/phy_adapt.h | 6 ++++ src/bl602_wifi/phy_bl602.h | 65 ++++++++++++++++++++++++++++++++++++++ src/bl602_wifi/phy_tcal.h | 6 ++++ src/bl602_wifi/phy_trpc.h | 9 ++++++ src/bl602_wifi/rf.h | 4 +++ src/bl602_wifi/rfc_bl602.h | 5 +++ 6 files changed, 95 insertions(+) create mode 100644 src/bl602_wifi/phy_adapt.h create mode 100644 src/bl602_wifi/phy_bl602.h create mode 100644 src/bl602_wifi/phy_tcal.h create mode 100644 src/bl602_wifi/phy_trpc.h create mode 100644 src/bl602_wifi/rf.h create mode 100644 src/bl602_wifi/rfc_bl602.h diff --git a/src/bl602_wifi/phy_adapt.h b/src/bl602_wifi/phy_adapt.h new file mode 100644 index 0000000..4de482b --- /dev/null +++ b/src/bl602_wifi/phy_adapt.h @@ -0,0 +1,6 @@ +#ifndef _PHY_ADAPT_H_ +#define _PHY_ADAPT_H_ +void pa_adapt(void); +void pa_init(void); +void pa_input(void); +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_bl602.h b/src/bl602_wifi/phy_bl602.h new file mode 100644 index 0000000..c0758f3 --- /dev/null +++ b/src/bl602_wifi/phy_bl602.h @@ -0,0 +1,65 @@ +#ifndef _PHY_BL602_H_ +#include + +enum +{ + /// 2.4GHz Band + PHY_BAND_2G4, + /// 5GHz band + PHY_BAND_5G, + /// Number of bands + PHY_BAND_MAX, +}; + +enum +{ + PHY_CHNL_BW_20, + PHY_CHNL_BW_40, + PHY_CHNL_BW_80, + PHY_CHNL_BW_160, + PHY_CHNL_BW_80P80, + PHY_CHNL_BW_OTHER, +}; + +struct phy_channel_info +{ + /// PHY channel information 1 + uint32_t info1; + /// PHY channel information 2 + uint32_t info2; +}; + +typedef struct phy_cfg_tag phy_cfg_tag; + +struct phy_cfg_tag { + uint32_t parameters[16]; +}; + + +struct phy_bl602_cfg_tag { + uint32_t reserved; +}; // :48:8 + +struct phy_env_tag { + struct phy_bl602_cfg_tag cfg; + uint16_t chnl_prim20_freq; + uint16_t chnl_center1_freq; + uint16_t chnl_center2_freq; + uint8_t band; + uint8_t chnl_type; +}; // :54:8 +struct phy_env_tag phy_env[1]; // :75:20 + +void phy_config_rxgain(int offset); +uint8_t phy_get_mac_freq(); +void phy_get_channel(struct phy_channel_info *info, uint8_t index); +uint8_t phy_get_mac_freq(void); +uint8_t phy_get_nss(void); +void phy_get_version(uint32_t *version_1,uint32_t *version_2); +void agc_config(void); +void mdm_reset(); +void mpif_clk_init(void); +uint8_t phy_vht_supported(); +uint8_t phy_get_ntx(void); +uint8_t phy_get_nss(void); +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_tcal.h b/src/bl602_wifi/phy_tcal.h new file mode 100644 index 0000000..87cb0c7 --- /dev/null +++ b/src/bl602_wifi/phy_tcal.h @@ -0,0 +1,6 @@ +#ifndef _PHY_TCAL_H_ +#define _PHY_TCAL_H_ +void phy_tcal_reset(void); +void phy_tcal_start(void); + +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_trpc.h b/src/bl602_wifi/phy_trpc.h new file mode 100644 index 0000000..e4480d9 --- /dev/null +++ b/src/bl602_wifi/phy_trpc.h @@ -0,0 +1,9 @@ +#ifndef _PHY_TRPC_H_ +#define _PHY_TRPC_H_ +#include +void trpc_init(void); +int8_t trpc_get_rf_max_power(void); +int8_t trpc_get_rf_min_power(void); +uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm); +void trpc_update_vs_channel(int8_t channel_MHz); // :171:6 +#endif \ No newline at end of file diff --git a/src/bl602_wifi/rf.h b/src/bl602_wifi/rf.h new file mode 100644 index 0000000..d73cf2d --- /dev/null +++ b/src/bl602_wifi/rf.h @@ -0,0 +1,4 @@ +#ifndef _RF_H_ +#define _RF_H_ +void rf_set_channel(uint8_t bandwidth, uint16_t channel_freq); +#endif \ No newline at end of file diff --git a/src/bl602_wifi/rfc_bl602.h b/src/bl602_wifi/rfc_bl602.h new file mode 100644 index 0000000..2387da6 --- /dev/null +++ b/src/bl602_wifi/rfc_bl602.h @@ -0,0 +1,5 @@ +#ifndef _RFC_BL602_H_ +#define _RFC_BL602_H_ +uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power); // :1479:10 +void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset); // :1643:6 +#endif \ No newline at end of file From 2e9d77294aecb1ecbd6b715c4594bb8044adcfbc Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 06:36:19 -0500 Subject: [PATCH 011/148] finish phy_bl602 --- src/bl602_wifi/phy_bl602.c | 325 ++++++++++++++++++++++++++++++++++--- 1 file changed, 299 insertions(+), 26 deletions(-) diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/phy_bl602.c index 027d385..d7401b1 100644 --- a/src/bl602_wifi/phy_bl602.c +++ b/src/bl602_wifi/phy_bl602.c @@ -1,29 +1,23 @@ #include #include #include +#include + +#include "phy_bl602.h" +#include "phy_trpc.h" +#include "rfc_bl602.h" +#include "phy_adapt.h" +#include "phy_tcal.h" +#include "rf.h" + +void assert_err(char * condition, char * file, int line); + +#define ASSERT_ERR(cond) if (!(cond)) assert_err(#cond, __FILE__, __LINE__); + +#define PHY_FORMATMOD_11B 0 +#define PHY_FORMATMOD_11G 1 +#define PHY_FORMATMOD_11N 2 -struct phy_bl602_cfg_tag { - uint32_t reserved; -}; // :48:8 - -struct phy_channel_info -{ - /// PHY channel information 1 - uint32_t info1; - /// PHY channel information 2 - uint32_t info2; -}; - -struct phy_env_tag { - struct phy_bl602_cfg_tag cfg; - uint16_t chnl_prim20_freq; - uint16_t chnl_center1_freq; - uint16_t chnl_center2_freq; - uint8_t band; - uint8_t chnl_type; -}; // :54:8 - -struct phy_env_tag phy_env[1]; // :75:20 static int8_t rxgain_offset_vs_temperature; // :79:15 static int8_t poweroffset[14]; // :80:15 @@ -63,9 +57,288 @@ void phy_get_version(uint32_t *version_1,uint32_t *version_2) { } void agc_config(void) { - AGC->RWNXAGCCNTL.set_0x0_0 = 0; - AGC->RWNXAGCCNTL.set_0x0_1 = 0; - AGC->r0xb3a4.set_0x0_2 = 0; - AGC->r0xb3a4.set_0x0_3 = 0; + AGC->RWNXAGCCNTL.set_0x0_0 = 0x0; + AGC->RWNXAGCCNTL.set_0x0_1 = 0x0; + AGC->r0xb3a4.set_0x0_2 = 0x0; + AGC->r0xb3a4.set_0x0_3 = 0x0; + AGC->r0xb394.set_0xf8_4 = 0xf8; + AGC->r0xb398.set_0x9e_5 = 0x9e; + AGC->r0xb3c4.set_0xce_6 = 0xce; + AGC->r0xb364.set_0x8_7 = 0x8; + AGC->r0xb364.set_0x3c_8 = 0x3c; + AGC->r0xb364.set_0x38_9 = 0x38; + AGC->r0xb364.set_0x39_10 = 0x39; + AGC->r0xb368.set_0x70_11 = 0x70; + AGC->r0xb368.set_0x70_12 = 0x70; + AGC->r0xb36c.set_0x12_13 = 0x12; + AGC->r0xb36c.set_0x5_14 = 0x5; + AGC->r0xb36c.set_0x28_15 = 0x28; + AGC->r0xb36c.set_0x7_16 = 0x7; + AGC->r0xb370.set_0x58_17 = 0x58; + AGC->r0xb3c0.set_0x18_18 = 0x18; + AGC->r0xb380.set_0x3e_19 = 0x3e; + AGC->r0xb380.set_0x37_20 = 0x37; + AGC->r0xb380.set_0x1_21 = 0x1; + AGC->r0xb380.set_0x0_22 = 0x0; + AGC->r0xb380.set_0x1_23 = 0x1; + AGC->r0xb384.set_0x39_24 = 0x39; + AGC->r0xb384.set_0x37_25 = 0x37; + AGC->r0xb384.set_0x14_26 = 0x14; + AGC->r0xb384.set_0x0_27 = 0x0; + AGC->r0xb384.set_0x2_28 = 0x2; + AGC->r0xb388.set_0xf_29 = 0xf; + AGC->r0xb388.set_0x17_30 = 0x17; + AGC->r0xb388.set_0x2a_31 = 0x2a; + AGC->r0xb388.set_0x0_32 = 0x0; + AGC->r0xb388.set_0x5_33 = 0x5; + AGC->r0xb38c.set_0x19_34 = 0x19; + AGC->r0xb38c.set_0x0_35 = 0x0; + AGC->r0xb38c.set_0xe_36 = 0xe; + AGC->r0xb38c.set_0x2_37 = 0x2; + AGC->r0xc830.set_0x3f_38 = 0x3f; + AGC->r0xc830.set_0x1_39 = 0x1; + AGC->r0xc830.set_0x36_40 = 0x36; + AGC->r0xc830.set_0x5_41 = 0x5; + AGC->r0xc814.set_0x0_42 = 0x0; + AGC->r0xc040.set_0xc_43 = 0xc; + AGC->r0xc040.set_0x3_44 = 0x3; + AGC->r0xc044.set_0x8_45 = 0x8; + AGC->r0xc044.set_0x0_46 = 0x0; + + phy_config_rxgain(0); + + AGC->r0xb3a0.set_0x9e_47 = 0x9e; + AGC->r0xb3c0.set_0xa4_48 = 0xa4; + AGC->r0xb3c0.set_0xa3_49 = 0xa3; + AGC->r0xc82c.set_0xb5_50 = 0xb5; + AGC->r0xc82c.set_0x1_51 = 0x1; + AGC->r0xc82c.set_0x1_52 = 0x1; + AGC->r0xc838.set_0x1_53 = 0x1; + AGC->r0xc838.set_0x100_54 = 0x100; + AGC->r0xc83c.set_0x1_55 = 0x1; + AGC->r0xc83c.set_0x17c_56 = 0x17c; + AGC->r0xc840.set_0x1_57 = 0x1; + AGC->r0xc840.set_0x100_58 = 0x100; + AGC->r0xc82c.set_0x40_59 = 0x40; +} + +void bz_phy_reset(void) { + // UNUSED Function + return ; +} + +void mdm_reset() { + MDM->swreset.value = 0x1111; + MDM->swreset.value = 0x0; +} + +void mpif_clk_init(void) { + // Empty Function + return ; +} + +uint8_t phy_bfmee_supported() { + return MDM->version.bfmee_supported; +} + +uint8_t phy_bfmer_supported(void) { + return MDM->version.bfmer_supported; +} + +void phy_get_rf_gain_capab(int8_t *max,int8_t *min) { + *max = trpc_get_rf_max_power(); + *min = trpc_get_rf_min_power(); +} + +void phy_get_rf_gain_idx(int8_t *power,uint8_t *idx) { + *idx = (uint8_t)rfc_get_power_level(2, (int)*power * 10); +} + +void phy_get_rf_gain_idx_vs_mode(uint8_t mode,int8_t *power,uint8_t *idx){ + *idx = (uint8_t)rfc_get_power_level(mode, (int)*power * 10); +} + +void phy_get_trpc_idx(uint8_t formatmod,uint8_t mcs,int8_t power,uint8_t *idx) { + // THIS IS ONLY MY GUESS. THE REAL DISASSEMBLY LOOKS VERY WEIRD AND IT MUST BE WRONG + ASSERT_ERR(formatmod <= PHY_FORMATMOD_11N); + if (formatmod == PHY_FORMATMOD_11G) + ASSERT_ERR((formatmod == PHY_FORMATMOD_11G) && (mcs <= 7)); // lc9 + if (formatmod == PHY_FORMATMOD_11B) + ASSERT_ERR((formatmod == PHY_FORMATMOD_11B) && (mcs <= 3)); // lc10 + if (formatmod == PHY_FORMATMOD_11N) + ASSERT_ERR((formatmod == PHY_FORMATMOD_11N) && (mcs <= 7)); // lc11 + *idx = (uint8_t)trpc_get_power_idx(formatmod, mcs, power); +} + +void phy_powroffset_set(int8_t *power_offset) { + for (int i = 0; i < 14; i++) { + poweroffset[i] = power_offset[i]; + } +} + +int phy_freq_to_channel(uint8_t band, uint16_t freq); + +void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t chantype) { + ASSERT_ERR(chantype == PHY_CHNL_BW_20); + ASSERT_ERR(band == PHY_BAND_2G4); + AGC->RWNXAGCCNTL.set_0x0_61 = 0; + MDM->rxchan.reset = 1; + MDM->mdmconf = 0; + mdm_reset(); + MDM->TXCTRL0 = 0xb4; + MDM->TXCTRL1 = 0x1c13; + MDM->TXCTRL3 = 0x2d00438; + MDM->TBECTRL0.tbe_count_adjust_20 = 0; + MDM->DCESTIMCTRL.value = 0xf0f; + MDM->DCESTIMCTRL.WAITHTSTF = 7; + MDM->r834.set60h = 0x6; + MDM->SMOOTHCTRL.value = 0x1880c06; + MDM->tbectrl2 = 0x7f03; + AGC->riu_rwnxagcaci20marg0 = 0; + AGC->riu_rwnxagcaci20marg1 = 0; + AGC->riu_rwnxagcaci20marg2 = 0; + MDM->txchan.txcbwmax = chantype; + + if (AGC->r000.iqcomp) { + AGC->riu_iqestiterclr = 1; + } + + rf_set_channel(chantype,freq1); + + uint8_t channel = 0; + + /* + int iVar3 = 0; + if (band == PHY_BAND_2G4) { + if ((freq - 0x96cU & 0xffff) >= 0x48) { + channel = 0xe; + if (freq != 0x9b4) { + channel = (uint8_t)((freq -0x967) / 5); + } + } + + } + */ + // TODO: are these two functions equivelant??? + channel = phy_freq_to_channel(band, freq); + rfc_apply_tx_power_offset(channel, poweroffset); + trpc_update_vs_channel((int8_t)freq1); +} + +void phy_set_channel(uint8_t band,uint8_t type,uint16_t prim20_freq,uint16_t center1_freq, + uint16_t center2_freq,uint8_t index) { + if ((center1_freq >= 2412 && center1_freq <= 2484) || (band == PHY_BAND_5G)) { + phy_hw_set_channel(band,prim20_freq,center1_freq,type); + phy_env[0].chnl_prim20_freq = prim20_freq; + phy_env[0].chnl_center1_freq = center1_freq; + phy_env[0].band = band; + phy_env[0].chnl_type = type; + } +} + +extern uint32_t agcmem[]; + +void phy_init(phy_cfg_tag *config) { + MDM->mdmconf = 0; + mdm_reset(); + MDM->rxchan.value = 0x20d; + MDM->rxchan.rxnssmax = phy_get_nss(); + MDM->rxchan.rxndpnstsmax = MDM->version.rxndpnstsmax; + MDM->rxchan.v19 = MDM->version.v19; + MDM->rxchan.vht = phy_vht_supported(); + MDM->rxchan.v30 = MDM->version.mu_mimo_rx; + MDM->r3024.precomp = 0x2D; + MDM->rxframeviolationmask = 0xffffffff; + + MDM->txchan.value = 0x20d; + MDM->txchan.txnssmax = phy_get_nss(); + MDM->txchan.ntxmax = phy_get_ntx(); + MDM->txchan.txcbwmax = MDM->version.txcbwmax; + MDM->txchan.v18 = MDM->version.v18; + MDM->txchan.vht = phy_vht_supported(); + MDM->txchan.v31 = MDM->version.mu_mimo_tx; + + MDM->r834.set1 = 1; + MDM->SMOOTHCTRL.CFGSMOOTHFORCE = 0; + MDM->SMOOTHSNRTHR.smoothsnrthrhigh = 0x1b; + MDM->SMOOTHSNRTHR.smoothsnrthrmid = 0xf; + MDM->rxctrl1 = 0x4920492; + MDM->r874.resetto1 = 1; + + AGC->r0xb500.set_0x2_62 = 0x02; + if (AGC->r000.iqcomp) { + AGC->r0xb110.set_0x0_63 = 0; + AGC->r0xb110.set_0x0_64 = 0; + AGC->r0xb110.set_0x0_65 = 0; + AGC->r0xb110.set_0x0_66 = 0; + AGC->riu_iqestiterclr = 0; + } + AGC->activeant = 1; + AGC->RWNXAGCCNTL.set1 = 1; + AGC->RWNXAGCCCATIMEOUT = 4000000; + AGC->irqmacccatimeouten.set1 = 1; + agc_config(); + AGC->RWNXAGCCNTL.agcfsmreset = 1; + + MDM->r874.set1beforewriteagcmem = 1; + + for (int i = 0; i < 0x200; i++) + AGCRAM->agcram[i] = agcmem[i]; + + MDM->r874.set1beforewriteagcmem = 0; + AGC->RWNXAGCCNTL.agcfsmreset = 0; + AGC->r0xc020.set_0x14_60 = 0x14; + phy_env[0].cfg.reserved = (config->parameters)[0]; + phy_env[0].chnl_center1_freq = 0xff; + phy_env[0].chnl_center2_freq = 0xff; + phy_env[0].chnl_prim20_freq = 0xff; + phy_env[0].band = 0x00; + phy_env[0].chnl_type = PHY_CHNL_BW_OTHER; + trpc_init(); + pa_init(); + phy_tcal_reset(); + phy_tcal_start(); +} + +uint8_t phy_vht_supported(){ + if (MDM->version.vht) // TODO: verify this cond + return 1; + return ((MDM->version.txcbwmax) >> 1) & 1; +} + +uint8_t phy_ldpc_rx_supported(void){ + return MDM->version.ldpcrx; +} + +uint8_t phy_ldpc_tx_supported(void){ + return MDM->version.ldpctx; +} + +void phy_mdm_isr(void) { + return; +} + +uint8_t phy_mu_mimo_rx_supported(void) { + return MDM->version.mu_mimo_rx; +} + +uint8_t phy_mu_mimo_tx_supported(void) { + return MDM->version.mu_mimo_tx; +} + +void phy_rc_isr(void) { + uint32_t val = AGC->r41c.value; + AGC->r420_copy41c = val; + if (val & 0x100) { + mdm_reset(); + } +} + +void phy_reset(void) { + return ; +} + +void phy_stop(void){ + return ; } From d395b9aa985f7821cb9b7f222e37bc13e3703404 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 19:14:14 -0500 Subject: [PATCH 012/148] support parse bl svd file and find reg with addr and mask --- script/manualext.py | 55 ++++++++++++++++++++++++++++----------------- script/reglib.py | 18 +++++++++++++++ script/svd2c.py | 45 +++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 21 deletions(-) create mode 100755 script/svd2c.py diff --git a/script/manualext.py b/script/manualext.py index f81e071..d407d0d 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -1,9 +1,12 @@ #!/usr/bin/env python3 from reglib import * +from typing import Mapping + +peris :Mapping[str, peripheral] = {} ############ MDM -Peripheral(peripheral('mdm', 0x44c00000, 0x4000)) +peris['mdm'] = Peripheral(peripheral('mdm', 0x44c00000, 0x4000)) Reg('txchan', 0x44c00824) Field('txcbwmax', 0xfcffffff) # Channel bandwidth @@ -92,16 +95,13 @@ Reg('r874', 0x44c00874) Field('resetto1', 0xf7ffffff) Field('set1beforewriteagcmem', 0xdfffffff) - -open('../src/include/phy/mdm.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) ############# AGC - -Peripheral(peripheral('agc', 0x44c0b000, 0x2000)) +peris['agc'] = Peripheral(peripheral('agc', 0x44c0b000, 0x2000)) Reg('r000', 0x44c0b000) FieldBit('iqcomp', 31-10) @@ -177,15 +177,15 @@ def scan_write(code): "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffe);", ]): print(f"AGC->{rn}.{fn} = {hex(val)}") -open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) -Peripheral(peripheral('agcram', 0x54c0a000, 0x800)) +peris['agcram'] = Peripheral(peripheral('agcram', 0x54c0a000, 0x800)) Buf('agcram', 0x54c0a000, 0x54c0a800 - 4) -open('../src/include/phy/agcram.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/agcram.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) # @@ -220,23 +220,23 @@ def getregs(fname, pattern='name'): -Peripheral(peripheral('mac_core', 0x44b00000, 0x1000)) +peris['mac_core'] = Peripheral(peripheral('mac_core', 0x44b00000, 0x1000)) for code, offset in getregs("../components/bl602/bl602_wifidrv/bl60x_wifi_driver/reg_mac_core.h", pattern='brief'): RegFromComment(offset + 0x44b00000, code) -open('../src/include/phy/mac_core.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/mac_core.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) -Peripheral(peripheral('mac_pl', 0x44b08000, 0x1000)) +peris['mac_pl'] = Peripheral(peripheral('mac_pl', 0x44b08000, 0x1000)) for code, offset in getregs("../alios/mac_pl.h"): RegFromComment(offset + 0x44b00000, code) -open('../src/include/phy/mac_pl.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/mac_pl.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) @@ -247,7 +247,7 @@ def getregs(fname, pattern='name'): ## look txl_payload_handle_backup for more info #### -Peripheral(peripheral('dma', 0x44a00000, 0x1000)) +peris['dma'] = Peripheral(peripheral('dma', 0x44a00000, 0x1000)) Reg('status', 0x44a00024) Field("TX", 0x1f) @@ -283,13 +283,13 @@ def getregs(fname, pattern='name'): Reg('LinkListItem1', 0x44a000ac) FieldBit("lli", 0, 16) -open('../src/include/phy/dma.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/dma.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) ############# sysctrl -Peripheral(peripheral('sysctrl', 0x44900000, 0x1000)) +peris['sysctrl'] = Peripheral(peripheral('sysctrl', 0x44900000, 0x1000)) Reg('time', 0x44900084) FieldBit('time_greater_on_bit12', 0) Reg("sysctrl_r68", 0x44900068) # set to 0x8000000c for init @@ -303,7 +303,7 @@ def getregs(fname, pattern='name'): Reg("r074", 0x44900068) # set to b09 -open('../src/include/phy/sysctrl.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/sysctrl.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) @@ -311,20 +311,33 @@ def getregs(fname, pattern='name'): ############# Wifi Regs 92 ## wtf is this??? -Peripheral(peripheral('sysctrl92', 0x44920000, 0x1000)) +peris['sysctrl92'] = Peripheral(peripheral('sysctrl92', 0x44920000, 0x1000)) Reg("set5010001f", 0x44920004) -open('../src/include/phy/sysctrl92.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/sysctrl92.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) ############# Wifi IPC (EMB/Core) -Peripheral(peripheral('ipc', 0x44800000, 0x1000)) +peris['ipc'] = Peripheral(peripheral('ipc', 0x44800000, 0x1000)) for code, offset in getregs("../components/bl602/bl602_wifidrv/bl60x_wifi_driver/reg_ipc_app.h", pattern='brief'): RegFromComment(offset + 0x44800000, code) -open('../src/include/phy/ipc.h', 'w').write('\n'.join(GenHeader())) +#open('../src/include/phy/ipc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) -#print('\n'.join(GenSVD())) \ No newline at end of file +#print('\n'.join(GenSVD())) + +if __name__ == '__main__': + import sys + if len(sys.argv) == 1: + for p_name, p in peris.items(): + open(f"../src/include/phy/{p_name}.h", "w").write("\n".join(p.genHeader())) + else: + if len(sys.argv) >= 2: + addr = int(sys.argv[1], 16) + mask = 0 + if len(sys.argv) == 3: + mask = int(sys.argv[2], 16) + print(CAccess(peris, addr, mask)) \ No newline at end of file diff --git a/script/reglib.py b/script/reglib.py index 9e4d505..05a4fe7 100755 --- a/script/reglib.py +++ b/script/reglib.py @@ -296,6 +296,24 @@ def HasField(addr): return context.r.hasField(addr) print("You are not in any register") +def CAccess(peris, addr, mask): + for p_name, p in peris.items(): + if p.base <= addr and p.base + p.size >= addr: + r = p.findReg(addr) + if r: + if r.fields: + if mask == 0: + return f"{p_name.upper()}->{r.name}.value" + else: + f = r.hasField(mask) + if f: + return f"{p_name.upper()}->{r.name}.{f.name}" + else: + return f"({p_name.upper()}->{r.name}.value) & {hex(mask)}" + else: + return f"{p_name.upper()}->{r.name}" + + def RegFromComment(addr, comment:str): name = "" import re diff --git a/script/svd2c.py b/script/svd2c.py new file mode 100755 index 0000000..8eaa3d9 --- /dev/null +++ b/script/svd2c.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +import xml.etree.ElementTree as ET +from reglib import * +from typing import Mapping + +peris :Mapping[str, peripheral] = {} + +import pickle, os +if os.path.exists("./peris.cache"): + peris = pickle.load(open("./peris.cache", "rb")) +else: + tree = ET.parse('../components/bl602/bl602_std/bl602_std/Device/Bouffalo/BL602/Peripherals/soc602_reg.svd') + + root = tree.getroot() + + for p in root.iter('peripheral'): + p_name = p.find('name').text + baseAddress = int(p.find('baseAddress').text, 16) + addressSize = int(p.find('./addressBlock/size').text, 16) + + pp = Peripheral(peripheral(p_name, baseAddress, addressSize)) + for r in p.iter('register'): + r_name = r.find('name').text + r_offset = int(r.find('addressOffset').text, 16) + Reg(r_name, r_offset + baseAddress) + for f in p.iter('field'): + f_name = f.find('name').text + lsb = int(f.find('lsb').text) + msb = int(f.find('msb').text) + FieldBit(f_name, lsb, msb - lsb + 1) + peris[p_name] = pp + pickle.dump(peris, open("./peris.cache", "wb")) + +if __name__ == '__main__': + import sys + if len(sys.argv) == 1: + for p_name, p in peris.items(): + open(f"../src/include/soc/{p_name}.h", "w").write("\n".join(p.genHeader())) + else: + if len(sys.argv) >= 2: + addr = int(sys.argv[1], 16) + mask = 0 + if len(sys.argv) == 3: + mask = int(sys.argv[2], 16) + print(CAccess(peris, addr, mask)) \ No newline at end of file From ad428c3a8d8dfbf2fa4e1d0bb727815329a9ffc8 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 19:17:19 -0500 Subject: [PATCH 013/148] no longer need to print the access code --- script/manualext.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index d407d0d..c42cd9d 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -163,10 +163,11 @@ def scan_write(code): f = Field(name_f, mask) yield r.name, f.name, value -print("agc_config") +#print("agc_config") for rn, fn, val in scan_write(open('../blobs/agc_config.c').readlines()): - print(f"AGC->{rn}.{fn} = {hex(val)}") -print("ex") + pass + #print(f"AGC->{rn}.{fn} = {hex(val)}") +#print("ex") for rn, fn, val in scan_write([ "write_volatile_4(DAT_44c0c020,uVar4 & 0xfc00ffff | 0x140000);", "write_volatile_4(DAT_44c0b390,uVar1 & 0xfffffeff);", @@ -176,7 +177,8 @@ def scan_write(code): "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffd);", "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffe);", ]): - print(f"AGC->{rn}.{fn} = {hex(val)}") + pass + #print(f"AGC->{rn}.{fn} = {hex(val)}") #open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) From d77652c374747eec71ccf4f2710210d14944aaf6 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 05:11:03 -0500 Subject: [PATCH 014/148] add missing bit --- script/manualext.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/script/manualext.py b/script/manualext.py index c42cd9d..4c27eb2 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -25,7 +25,10 @@ Field('v30', 0xfffeffff) # some switch? DAT_44c00000>>30 Field('_v30', 0xffefffff) # some switch? DAT_44c00000>>30 FieldBit('reset', 0) # set 1 in phy_hw_set_channel for.. reset? +<<<<<<< HEAD Field('rxndpnstsmax', 0xffff8fff) +======= +>>>>>>> 42c4e98 (add missing bit) Reg('version', 0x44c00000) FieldBit('vht', 31-9) From f910c82f7e551019758fa62370d6fb0001084ecb Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 05:11:19 -0500 Subject: [PATCH 015/148] add bit --- script/manualext.py | 3 --- src/include/phy/mdm.h | 4 ++-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 4c27eb2..c42cd9d 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -25,10 +25,7 @@ Field('v30', 0xfffeffff) # some switch? DAT_44c00000>>30 Field('_v30', 0xffefffff) # some switch? DAT_44c00000>>30 FieldBit('reset', 0) # set 1 in phy_hw_set_channel for.. reset? -<<<<<<< HEAD Field('rxndpnstsmax', 0xffff8fff) -======= ->>>>>>> 42c4e98 (add missing bit) Reg('version', 0x44c00000) FieldBit('vht', 31-9) diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index 8bdd17f..e536cf3 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -59,9 +59,9 @@ typedef union { uint32_t rxndpnstsmax : 3; // @ 14 -- 12 # 0xffff8fff uint32_t pad3 : 1; uint32_t v30 : 1; // @ 16 -- 16 # 0xfffeffff - uint32_t pad4 : 3; + uint32_t pad3 : 3; uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff - uint32_t pad5 : 3; + uint32_t pad4 : 3; uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff }; } rxchan; // @ 0x820 From cfbeae3658ef2b3923efffeb0d5c6aa97f63bd2f Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 05:47:51 -0500 Subject: [PATCH 016/148] add missing rxndpnstsmax --- src/include/phy/mdm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index e536cf3..8bdd17f 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -59,9 +59,9 @@ typedef union { uint32_t rxndpnstsmax : 3; // @ 14 -- 12 # 0xffff8fff uint32_t pad3 : 1; uint32_t v30 : 1; // @ 16 -- 16 # 0xfffeffff - uint32_t pad3 : 3; - uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff uint32_t pad4 : 3; + uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad5 : 3; uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff }; } rxchan; // @ 0x820 From 26793ff37539e6b16a3c9f4a3d6c0a7e78fa554a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:03:03 -0500 Subject: [PATCH 017/148] add bz_phyfunc --- script/manualext.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/script/manualext.py b/script/manualext.py index c42cd9d..94e58ba 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -331,6 +331,11 @@ def getregs(fname, pattern='name'): #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) + +peris['bz_phy'] = Peripheral(peripheral('bz_phy', 0x40002000, 0x1000)) +scan_write(open('../blobs/bz_phy.c').readlines()) + + if __name__ == '__main__': import sys if len(sys.argv) == 1: From 377b3c2b8e05203fb4281351d1cf1692c0f80cb5 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:03:18 -0500 Subject: [PATCH 018/148] add bz_phy.h --- src/include/phy/bz_phy.h | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 src/include/phy/bz_phy.h diff --git a/src/include/phy/bz_phy.h b/src/include/phy/bz_phy.h new file mode 100644 index 0000000..354d4d5 --- /dev/null +++ b/src/include/phy/bz_phy.h @@ -0,0 +1,8 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + }; +} bz_phy_regs; +#define BZ_PHY_BASE 0x40002000 +#define BZ_PHY ((bz_phy_regs* volatile)(BZ_PHY_BASE)) \ No newline at end of file From 3ce657a2d55ebd88e7f736f068ee104ce9992377 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:10:49 -0500 Subject: [PATCH 019/148] add support for 0x --- script/manualext.py | 9 ++++++--- src/include/phy/bz_phy.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 94e58ba..d2c8244 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -134,9 +134,12 @@ gid = 0 -def scan_write(code): +def scan_write(code, dat="dat"): global gid - write_pattern = r'write_volatile_4\(DAT_([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| 0x([0-9a-f]+))*\);' + if dat == 'dat': + write_pattern = r'write_volatile_4\(DAT_([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| 0x([0-9a-f]+))*\);' + else: + write_pattern = r'write_volatile_4\(0x([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| 0x([0-9a-f]+))*\);' for l in code: import re g = re.search(write_pattern, l) @@ -333,7 +336,7 @@ def getregs(fname, pattern='name'): peris['bz_phy'] = Peripheral(peripheral('bz_phy', 0x40002000, 0x1000)) -scan_write(open('../blobs/bz_phy.c').readlines()) +scan_write(open('../blobs/bz_phy.c').readlines(), '0x') if __name__ == '__main__': diff --git a/src/include/phy/bz_phy.h b/src/include/phy/bz_phy.h index 354d4d5..f81f5cd 100644 --- a/src/include/phy/bz_phy.h +++ b/src/include/phy/bz_phy.h @@ -2,6 +2,40 @@ typedef union { uint32_t regs[0x400]; uint8_t pad[0x1000]; struct { + uint8_t pad0[0x808]; + union { + uint32_t value; + struct { + uint32_t pad0 : 23; + uint32_t set_0x1_67 : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t set_0x8_68 : 8; // @ 31 -- 24 # 0xffffff + }; + } r0x2808; // @ 0x808 + union { + uint32_t value; + struct { + uint32_t set_0x0_71 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 15; + uint32_t set_0x1_69 : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t set_0x4_70 : 8; // @ 31 -- 24 # 0xffffff + }; + } r0x280c; // @ 0x80c + union { + uint32_t value; + struct { + uint32_t set_0x0_76 : 1; // @ 0 -- 0 # 0xfffffffe + }; + } r0x2810; // @ 0x810 + uint8_t pad1[0x40]; + union { + uint32_t value; + struct { + uint32_t set_0x1e_75 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t set_0x20_72 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t set_0xa_74 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t set_0x1e_73 : 8; // @ 31 -- 24 # 0xffffff + }; + } r0x2854; // @ 0x854 }; } bz_phy_regs; #define BZ_PHY_BASE 0x40002000 From 55be85b90a93c73f47c3feb92612e42ae4fc2977 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:24:19 -0500 Subject: [PATCH 020/148] foreach in scan --- script/manualext.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/script/manualext.py b/script/manualext.py index d2c8244..6821868 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -336,7 +336,9 @@ def getregs(fname, pattern='name'): peris['bz_phy'] = Peripheral(peripheral('bz_phy', 0x40002000, 0x1000)) -scan_write(open('../blobs/bz_phy.c').readlines(), '0x') +for rn, fn, val in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): + pass + #print(f"BZ_PHY->{rn}.{fn} = {hex(val)}") if __name__ == '__main__': From 7261e1c67412b22daa5d74b29de9c95259674e21 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:10:49 -0500 Subject: [PATCH 021/148] add support for 0x --- src/bl602_wifi/phy_bl602.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/phy_bl602.c index d7401b1..7858ac0 100644 --- a/src/bl602_wifi/phy_bl602.c +++ b/src/bl602_wifi/phy_bl602.c @@ -2,6 +2,7 @@ #include #include #include +#include #include "phy_bl602.h" #include "phy_trpc.h" @@ -123,7 +124,16 @@ void agc_config(void) { } void bz_phy_reset(void) { - // UNUSED Function + BZ_PHY->r0x2808.set_0x1_67 = 0x1; + BZ_PHY->r0x2808.set_0x8_68 = 0x8; + BZ_PHY->r0x280c.set_0x1_69 = 0x1; + BZ_PHY->r0x280c.set_0x4_70 = 0x4; + BZ_PHY->r0x280c.set_0x0_71 = 0x0; + BZ_PHY->r0x2854.set_0x20_72 = 0x20; + BZ_PHY->r0x2854.set_0x1e_73 = 0x1e; + BZ_PHY->r0x2854.set_0xa_74 = 0xa; + BZ_PHY->r0x2854.set_0x1e_75 = 0x1e; + BZ_PHY->r0x2810.set_0x0_76 = 0x0; return ; } From ec7126964ce44584c6618aaf74507ef2f20d1d45 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:28:13 -0500 Subject: [PATCH 022/148] fix bz_phy.c --- blobs/bz_phy.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 blobs/bz_phy.c diff --git a/blobs/bz_phy.c b/blobs/bz_phy.c new file mode 100644 index 0000000..97c9944 --- /dev/null +++ b/blobs/bz_phy.c @@ -0,0 +1,31 @@ +void bz_phy_reset(void) + +{ + uint uVar1; + + uVar1 = read_volatile_4(0x40002808); + write_volatile_4(0x40002808,uVar1 & 0xff7fffff | 0x800000); + uVar1 = read_volatile_4(0x40002808); + write_volatile_4(0x40002808,uVar1 & 0xffffff | 0x8000000); + uVar1 = read_volatile_4(0x4000280c); + write_volatile_4(0x4000280c,uVar1 & 0xff7fffff | 0x800000); + uVar1 = read_volatile_4(0x4000280c); + write_volatile_4(0x4000280c,uVar1 & 0xffffff | 0x4000000); + uVar1 = read_volatile_4(0x4000280c); + write_volatile_4(0x4000280c,uVar1 & 0xffffff00); + uVar1 = read_volatile_4(0x40002854); + write_volatile_4(0x40002854,uVar1 & 0xffff00ff | 0x2000); + uVar1 = read_volatile_4(0x40002854); + write_volatile_4(0x40002854,uVar1 & 0xffffff | 0x1e000000); + uVar1 = read_volatile_4(0x40002854); + write_volatile_4(0x40002854,uVar1 & 0xff00ffff | 0xa0000); + uVar1 = read_volatile_4(0x40002854); + write_volatile_4(0x40002854,uVar1 & 0xffffff00 | 0x1e); + uVar1 = read_volatile_4(0x40002810); + write_volatile_4(0x40002810,uVar1 & 0xfffffffe); + uVar1 = read_volatile_4(0x40002810); + write_volatile_4(0x40002810,uVar1 | 0x2); + uVar1 = read_volatile_4(0x40002cac); + write_volatile_4(0x40002cac,uVar1 & 0xffffffe0 | 0x4); + return; +} \ No newline at end of file From f32ad885d7c3e257f5c6f82f6143515708d4f838 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:29:29 -0500 Subject: [PATCH 023/148] add bz_phy_reset --- src/bl602_wifi/phy_bl602.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/phy_bl602.c index 7858ac0..7931908 100644 --- a/src/bl602_wifi/phy_bl602.c +++ b/src/bl602_wifi/phy_bl602.c @@ -134,6 +134,8 @@ void bz_phy_reset(void) { BZ_PHY->r0x2854.set_0xa_74 = 0xa; BZ_PHY->r0x2854.set_0x1e_75 = 0x1e; BZ_PHY->r0x2810.set_0x0_76 = 0x0; + BZ_PHY->r0x2810.set_0x1_77 = 0x1; + BZ_PHY->r0x2cac.set_0x4_78 = 0x4; return ; } From c98ef5a3e620cf43a4ca2bd5782409901c4049cb Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:30:12 -0500 Subject: [PATCH 024/148] new header --- src/include/phy/bz_phy.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/include/phy/bz_phy.h b/src/include/phy/bz_phy.h index f81f5cd..a2ba2df 100644 --- a/src/include/phy/bz_phy.h +++ b/src/include/phy/bz_phy.h @@ -24,6 +24,7 @@ typedef union { uint32_t value; struct { uint32_t set_0x0_76 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t set_0x1_77 : 1; // @ 1 -- 1 # 0xfffffffd }; } r0x2810; // @ 0x810 uint8_t pad1[0x40]; @@ -36,6 +37,13 @@ typedef union { uint32_t set_0x1e_73 : 8; // @ 31 -- 24 # 0xffffff }; } r0x2854; // @ 0x854 + uint8_t pad2[0x454]; + union { + uint32_t value; + struct { + uint32_t set_0x4_78 : 5; // @ 4 -- 0 # 0xffffffe0 + }; + } r0x2cac; // @ 0xcac }; } bz_phy_regs; #define BZ_PHY_BASE 0x40002000 From fc7f9f889aea977446695f5d28c255cc33853de6 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 21 Jul 2021 19:14:14 -0500 Subject: [PATCH 025/148] support parse bl svd file and find reg with addr and mask --- script/manualext.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/script/manualext.py b/script/manualext.py index 6821868..dc98b5a 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -334,6 +334,7 @@ def getregs(fname, pattern='name'): #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) +<<<<<<< HEAD peris['bz_phy'] = Peripheral(peripheral('bz_phy', 0x40002000, 0x1000)) for rn, fn, val in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): @@ -341,6 +342,8 @@ def getregs(fname, pattern='name'): #print(f"BZ_PHY->{rn}.{fn} = {hex(val)}") +======= +>>>>>>> d18fd82 (support parse bl svd file and find reg with addr and mask) if __name__ == '__main__': import sys if len(sys.argv) == 1: From 58095db6601fca26c6825cb58555352bdeb91870 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 22 Jul 2021 01:03:03 -0500 Subject: [PATCH 026/148] add bz_phyfunc --- script/manualext.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index dc98b5a..64fee3f 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -334,16 +334,12 @@ def getregs(fname, pattern='name'): #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) -<<<<<<< HEAD peris['bz_phy'] = Peripheral(peripheral('bz_phy', 0x40002000, 0x1000)) for rn, fn, val in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): pass #print(f"BZ_PHY->{rn}.{fn} = {hex(val)}") - -======= ->>>>>>> d18fd82 (support parse bl svd file and find reg with addr and mask) if __name__ == '__main__': import sys if len(sys.argv) == 1: From c8111a78dc1d70a7ff71c3b09fee75067ed1ffc0 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Fri, 23 Jul 2021 03:53:18 -0500 Subject: [PATCH 027/148] more stable name --- script/manualext.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 64fee3f..a987640 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -147,10 +147,12 @@ def scan_write(code, dat="dat"): continue value = 0 addr = int(g.group(1), 16) + lsb = 0 if g.group(3) == None: # mask value = int(g.group(5), 16) mask = (~value) & 0xffffffff - value = value >> ((value & (-value)).bit_length() - 1) + lsb = ((value & (-value)).bit_length() - 1) + value = value >> lsb else: mask = int(g.group(3), 16) if g.group(5): # value @@ -159,7 +161,9 @@ def scan_write(code, dat="dat"): lsb = lsb.bit_length() - 1 value = int(g.group(5), 16) value = value >> lsb - name_f = f'set_{hex(value)}_{gid}' + else: + lsb = 0 + name_f = f'set_{hex(value)}_{lsb}' name_r = f'r{hex(addr&0xffff)}' gid = gid + 1 r = Reg(name_r, addr) From 5a877e604409be34a3a7b18c32e304f827616635 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 02:21:39 -0500 Subject: [PATCH 028/148] add extra information from DWARF --- script/manualext.py | 145 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 127 insertions(+), 18 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index a987640..0912ee3 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -92,9 +92,9 @@ Field('smoothsnrthrmid', 0xffffff00) Reg('rxctrl1', 0x44c0083c) # reset to 0x4920492 -Reg('r874', 0x44c00874) +Reg('r0x874', 0x44c00874) Field('resetto1', 0xf7ffffff) -Field('set1beforewriteagcmem', 0xdfffffff) +Field('mdm_agcmemclkforce', 0xdfffffff) #print('\n'.join(GenSVD())) @@ -105,6 +105,16 @@ Reg('r000', 0x44c0b000) FieldBit('iqcomp', 31-10) +### guess +Reg('RWNXAGCRAMP', 0x44c0b36c) +FieldBit('RAMPDNNDLINDEX', 24, 3) # 0x05 +FieldBit('RAMPDNGAPQDB', 16, 8) # 0x20 +FieldBit('RAMPUPNDLINDEX', 8, 3) # 0x7 +FieldBit('RAMPUPGAPQDB', 0, 8) # 0x20 + +### + + Reg('RWNXAGCCNTL', 0x44c0b390) Field('set1', 0xfffffffc) Field('agcfsmreset', 0xffffefff) # set 1 before agc mem, maybe @@ -137,9 +147,9 @@ def scan_write(code, dat="dat"): global gid if dat == 'dat': - write_pattern = r'write_volatile_4\(DAT_([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| 0x([0-9a-f]+))*\);' + write_pattern = r'write_volatile_4\(DAT_([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| ([0-9a-z]+))*\);' else: - write_pattern = r'write_volatile_4\(0x([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| 0x([0-9a-f]+))*\);' + write_pattern = r'write_volatile_4\(0x([0-9a-f]+),uVar\d( & 0x([0-9a-f]+))*( \| ([0-9a-z]+))*\);' for l in code: import re g = re.search(write_pattern, l) @@ -167,15 +177,94 @@ def scan_write(code, dat="dat"): name_r = f'r{hex(addr&0xffff)}' gid = gid + 1 r = Reg(name_r, addr) - f = Field(name_f, mask) - yield r.name, f.name, value - -#print("agc_config") -for rn, fn, val in scan_write(open('../blobs/agc_config.c').readlines()): - pass - #print(f"AGC->{rn}.{fn} = {hex(val)}") -#print("ex") -for rn, fn, val in scan_write([ + yield r, Field(name_f, mask) + + +agc_attr = [ + (0x44c0b390, "riu_htstfgainen"), + (0x44c0b390, "riu_rifsdeten"), + (0x44c0b3a4, "riu_fe20gain"), + (0x44c0b3a4, "riu_fe40gain"), + (0x44c0b394, "riu_vpeakadcqdbv"), + (0x44c0b398, "riu_adcpowmindbm"), + (0x44c0b3c4, "riu_adcpowsupthrdbm"), + (0x44c0b364, "riu_satdelay50ns"), + (0x44c0b364, "riu_sathighthrdbv"), + (0x44c0b364, "riu_satlowthrdbv"), + (0x44c0b364, "riu_satthrdbv"), + (0x44c0b368, "riu_crossdnthrqdbm"), + (0x44c0b368, "riu_crossupthrqdbm"), + (0x44c0b36c, "riu_rampupgapqdb"), + (0x44c0b36c, "riu_rampupndlindex"), + (0x44c0b36c, "riu_rampdngapqdb"), + (0x44c0b36c, "riu_rampdnndlindex"), + (0x44c0b370, "riu_adcpowdisthrdbv"), + (0x44c0b3c0, "riu_idinbdpowgapdnqdbm"), + (0x44c0b380, "riu_evt0op3"), + (0x44c0b380, "riu_evt0op2"), + (0x44c0b380, "riu_evt0op1"), + (0x44c0b380, "riu_evt0pathcomb"), + (0x44c0b380, "riu_evt0opcomb"), + (0x44c0b384, "riu_evt1op1"), + (0x44c0b384, "riu_evt1op2"), + (0x44c0b384, "riu_evt1op3"), + (0x44c0b384, "riu_evt1pathcomb"), + (0x44c0b384, "riu_evt1opcomb"), + (0x44c0b388, "riu_evt2op1"), + (0x44c0b388, "riu_evt2op2"), + (0x44c0b388, "riu_evt2op3"), + (0x44c0b388, "riu_evt2pathcomb"), + (0x44c0b388, "riu_evt2opcomb"), + (0x44c0b38c, "riu_evt3op1"), + (0x44c0b38c, "riu_evt3op2"), + (0x44c0b38c, "riu_evt3op3"), + (0x44c0b38c, "riu_evt3opcomb"), + (0x44c0c830, "rc2_evt4op1"), + (0x44c0c830, "rc2_evt4op2"), + (0x44c0c830, "rc2_evt4op3"), + (0x44c0c830, "rc2_evt4opcomb"), + (0x44c0c814, "rc2_pkdet_mode"), + (0x44c0c814, "rc2_pkdet_cnt_thr"), + (0x44c0c814, "rc2_pkdet_cnt_thr"), + (0x44c0c040, "rc2_rx0_vga_idx_max"), + (0x44c0c040, "rc2_rx0_vga_idx_min"), + (0x44c0c044, "rc2_rx0_lna_idx_max"), + (0x44c0c044, "rc2_rx0_lna_idx_min"), + (0x44c0b3a0, "riu_inbdpowmindbm"), + (0x44c0b3c0, "riu_inbdpowsupthrdbm"), + (0x44c0b3c0, "riu_inbdpowinfthrdbm"), + (0x44c0c82c, "rc2_inbdpow_adj_thr_dbm"), + (0x44c0c82c, "rc2_inbdpowsupthr_adj_en"), + (0x44c0c82c, "rc2_inbdpowinfthr_adj_en"), + (0x44c0c838, "rc2_reflevofdmthd_en"), + (0x44c0c838, "rc2_reflevofdmthd"), + (0x44c0c83c, "rc2_reflevdsssthd_en"), + (0x44c0c83c, "rc2_reflevdsssthd"), + (0x44c0c840, "rc2_reflevdssscontthd_en"), + (0x44c0c840, "rc2_reflevdssscontthd"), + (0x44c0c82c, "rc2_inbdpowfastvalid_cnt"), +] + +i = 0 +for r, f in scan_write(open('../blobs/agc_config.c').readlines()): + if r.offset == agc_attr[i][0] - 0x44c0b000: + f.name = agc_attr[i][1] + else: + print(f"mismatched {i} {agc_attr[i][1]} {hex(r.offset + 0x44c0b000)} {hex(agc_attr[i][0])}") + i = i + 1 + +extra_regs = [ + "rc_paoff_delay", + "riu_agcfsmreset", + "riu_txshift4044", + "riu_rxiqphaseesten", + "riu_rxiqgainesten", + "riu_rxiqphasecompen", + "riu_rxiqgaincompen" +] + +i = 0 +for _, f in scan_write([ "write_volatile_4(DAT_44c0c020,uVar4 & 0xfc00ffff | 0x140000);", "write_volatile_4(DAT_44c0b390,uVar1 & 0xfffffeff);", "write_volatile_4(DAT_44c0b500,uVar4 & 0xffffcfff | 0x2000);", @@ -184,8 +273,8 @@ def scan_write(code, dat="dat"): "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffd);", "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffe);", ]): - pass - #print(f"AGC->{rn}.{fn} = {hex(val)}") + f.name = agc_attr[i][1] + i = i + 1 #open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) #print('\n'.join(GenSVD())) @@ -340,9 +429,29 @@ def getregs(fname, pattern='name'): peris['bz_phy'] = Peripheral(peripheral('bz_phy', 0x40002000, 0x1000)) -for rn, fn, val in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): - pass - #print(f"BZ_PHY->{rn}.{fn} = {hex(val)}") + +extra_bz_phy = [ +(0x40002808,"bz_phy_tx_rampup_fm_on"), +(0x40002808,"bz_phy_tx_rampup_time_us"), +(0x4000280c,"bz_phy_tx_rampdn_fm_on"), +(0x4000280c,"bz_phy_tx_rampdn_time_us"), +(0x4000280c,"bz_phy_tx_rampdn_pad0_time_us"), +(0x40002854,"bz_phy_rx_proc_time_mlsd_us"), +(0x40002854,"bz_phy_rx_proc_time_direct_us"), +(0x40002854,"bz_phy_rx_proc_time_eq_us"), +(0x40002854,"bz_phy_rx_proc_time_viterbi_us"), +(0x40002810,"bz_phy_rx_dfe_notch_en"), +(0x40002810,"bz_phy_rx_dfe_toc_en"), +(0x40002cac,"bz_agc_rbb_ind_min"), +] + +i = 0 +for r, f in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): + if r.offset == extra_bz_phy[i][0] - 0x40002000: + f.name = extra_bz_phy[i][1] + else: + print(f"mismatched {i} {extra_bz_phy[i][1]} {hex(r.offset + 0x40002000)} {hex(extra_bz_phy[i][0])}") + i = i + 1 if __name__ == '__main__': import sys From 95cf6ec12e6426127f2bbbeed3b41916907e153a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 02:22:45 -0500 Subject: [PATCH 029/148] add extra names --- src/include/phy/agc.h | 137 ++++++++++++++++++++------------------- src/include/phy/bz_phy.h | 24 +++---- src/include/phy/mdm.h | 4 +- 3 files changed, 83 insertions(+), 82 deletions(-) diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h index e3c4e4e..15fc4a8 100644 --- a/src/include/phy/agc.h +++ b/src/include/phy/agc.h @@ -14,10 +14,10 @@ typedef union { union { uint32_t value; struct { - uint32_t set_0x0_66 : 1; // @ 0 -- 0 # 0xfffffffe - uint32_t set_0x0_65 : 1; // @ 1 -- 1 # 0xfffffffd - uint32_t set_0x0_64 : 1; // @ 2 -- 2 # 0xfffffffb - uint32_t set_0x0_63 : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t riu_adcpowsupthrdbm : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t riu_adcpowmindbm : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t riu_vpeakadcqdbv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t riu_fe40gain : 1; // @ 3 -- 3 # 0xfffffff7 }; } r0xb110; // @ 0x110 uint8_t pad1[0x4]; @@ -30,38 +30,38 @@ typedef union { union { uint32_t value; struct { - uint32_t set_0x39_10 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t riu_satthrdbv : 6; // @ 5 -- 0 # 0xffffffc0 uint32_t pad0 : 2; - uint32_t set_0x38_9 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t riu_satlowthrdbv : 6; // @ 13 -- 8 # 0xffffc0ff uint32_t pad1 : 2; - uint32_t set_0x3c_8 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t riu_sathighthrdbv : 6; // @ 21 -- 16 # 0xffc0ffff uint32_t pad2 : 2; - uint32_t set_0x8_7 : 5; // @ 28 -- 24 # 0xe0ffffff + uint32_t riu_satdelay50ns : 5; // @ 28 -- 24 # 0xe0ffffff }; } r0xb364; // @ 0x364 union { uint32_t value; struct { - uint32_t set_0x70_12 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t riu_crossupthrqdbm : 10; // @ 9 -- 0 # 0xfffffc00 uint32_t pad0 : 2; - uint32_t set_0x70_11 : 10; // @ 21 -- 12 # 0xffc00fff + uint32_t riu_crossdnthrqdbm : 10; // @ 21 -- 12 # 0xffc00fff }; } r0xb368; // @ 0x368 union { uint32_t value; struct { - uint32_t set_0x12_13 : 8; // @ 7 -- 0 # 0xffffff00 - uint32_t set_0x5_14 : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t riu_rampupgapqdb : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t riu_rampupndlindex : 3; // @ 10 -- 8 # 0xfffff8ff uint32_t pad0 : 5; - uint32_t set_0x28_15 : 8; // @ 23 -- 16 # 0xff00ffff - uint32_t set_0x7_16 : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t riu_rampdngapqdb : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t riu_rampdnndlindex : 3; // @ 26 -- 24 # 0xf8ffffff }; - } r0xb36c; // @ 0x36c + } RWNXAGCRAMP; // @ 0x36c union { uint32_t value; struct { uint32_t pad0 : 16; - uint32_t set_0x58_17 : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t riu_adcpowdisthrdbv : 7; // @ 22 -- 16 # 0xff80ffff }; } r0xb370; // @ 0x370 uint8_t pad4[0xc]; @@ -69,44 +69,44 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 10; - uint32_t set_0x1_23 : 3; // @ 12 -- 10 # 0xffffe3ff - uint32_t set_0x0_22 : 1; // @ 13 -- 13 # 0xffffdfff - uint32_t set_0x3e_19 : 6; // @ 19 -- 14 # 0xfff03fff - uint32_t set_0x37_20 : 6; // @ 25 -- 20 # 0xfc0fffff - uint32_t set_0x1_21 : 6; // @ 31 -- 26 # 0x3ffffff + uint32_t riu_evt0opcomb : 3; // @ 12 -- 10 # 0xffffe3ff + uint32_t riu_evt0pathcomb : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t riu_evt0op3 : 6; // @ 19 -- 14 # 0xfff03fff + uint32_t riu_evt0op2 : 6; // @ 25 -- 20 # 0xfc0fffff + uint32_t riu_evt0op1 : 6; // @ 31 -- 26 # 0x3ffffff }; } r0xb380; // @ 0x380 union { uint32_t value; struct { uint32_t pad0 : 10; - uint32_t set_0x2_28 : 3; // @ 12 -- 10 # 0xffffe3ff - uint32_t set_0x0_27 : 1; // @ 13 -- 13 # 0xffffdfff - uint32_t set_0x14_26 : 6; // @ 19 -- 14 # 0xfff03fff - uint32_t set_0x37_25 : 6; // @ 25 -- 20 # 0xfc0fffff - uint32_t set_0x39_24 : 6; // @ 31 -- 26 # 0x3ffffff + uint32_t riu_evt1opcomb : 3; // @ 12 -- 10 # 0xffffe3ff + uint32_t riu_evt1pathcomb : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t riu_evt1op3 : 6; // @ 19 -- 14 # 0xfff03fff + uint32_t riu_evt1op2 : 6; // @ 25 -- 20 # 0xfc0fffff + uint32_t riu_evt1op1 : 6; // @ 31 -- 26 # 0x3ffffff }; } r0xb384; // @ 0x384 union { uint32_t value; struct { uint32_t pad0 : 10; - uint32_t set_0x5_33 : 3; // @ 12 -- 10 # 0xffffe3ff - uint32_t set_0x0_32 : 1; // @ 13 -- 13 # 0xffffdfff - uint32_t set_0x2a_31 : 6; // @ 19 -- 14 # 0xfff03fff - uint32_t set_0x17_30 : 6; // @ 25 -- 20 # 0xfc0fffff - uint32_t set_0xf_29 : 6; // @ 31 -- 26 # 0x3ffffff + uint32_t riu_evt2opcomb : 3; // @ 12 -- 10 # 0xffffe3ff + uint32_t riu_evt2pathcomb : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t riu_evt2op3 : 6; // @ 19 -- 14 # 0xfff03fff + uint32_t riu_evt2op2 : 6; // @ 25 -- 20 # 0xfc0fffff + uint32_t riu_evt2op1 : 6; // @ 31 -- 26 # 0x3ffffff }; } r0xb388; // @ 0x388 union { uint32_t value; struct { uint32_t pad0 : 10; - uint32_t set_0x2_37 : 3; // @ 12 -- 10 # 0xffffe3ff + uint32_t riu_evt3opcomb : 3; // @ 12 -- 10 # 0xffffe3ff uint32_t pad1 : 1; - uint32_t set_0xe_36 : 6; // @ 19 -- 14 # 0xfff03fff - uint32_t set_0x0_35 : 6; // @ 25 -- 20 # 0xfc0fffff - uint32_t set_0x19_34 : 6; // @ 31 -- 26 # 0x3ffffff + uint32_t riu_evt3op3 : 6; // @ 19 -- 14 # 0xfff03fff + uint32_t riu_evt3op2 : 6; // @ 25 -- 20 # 0xfc0fffff + uint32_t riu_evt3op1 : 6; // @ 31 -- 26 # 0x3ffffff }; } r0xb38c; // @ 0x38c union { @@ -114,41 +114,41 @@ typedef union { struct { uint32_t set1 : 2; // @ 1 -- 0 # 0xfffffffc uint32_t pad0 : 6; - uint32_t set_0x0_61 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t riu_rifsdeten : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad1 : 1; - uint32_t set_0x0_1 : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t riu_rifsdeten : 1; // @ 10 -- 10 # 0xfffffbff uint32_t pad2 : 1; uint32_t agcfsmreset : 1; // @ 12 -- 12 # 0xffffefff uint32_t pad3 : 3; - uint32_t set_0x0_0 : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t riu_htstfgainen : 1; // @ 16 -- 16 # 0xfffeffff }; } RWNXAGCCNTL; // @ 0x390 union { uint32_t value; struct { uint32_t pad0 : 16; - uint32_t set_0xf8_4 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t riu_vpeakadcqdbv : 8; // @ 23 -- 16 # 0xff00ffff }; } r0xb394; // @ 0x394 union { uint32_t value; struct { uint32_t pad0 : 8; - uint32_t set_0x9e_5 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t riu_adcpowmindbm : 8; // @ 15 -- 8 # 0xffff00ff }; } r0xb398; // @ 0x398 uint8_t pad5[0x4]; union { uint32_t value; struct { - uint32_t set_0x9e_47 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t riu_inbdpowmindbm : 8; // @ 7 -- 0 # 0xffffff00 }; } r0xb3a0; // @ 0x3a0 union { uint32_t value; struct { - uint32_t set_0x0_2 : 8; // @ 7 -- 0 # 0xffffff00 - uint32_t set_0x0_3 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t riu_fe20gain : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t riu_fe40gain : 8; // @ 15 -- 8 # 0xffff00ff }; } r0xb3a4; // @ 0x3a4 uint8_t pad6[0x14]; @@ -156,16 +156,16 @@ typedef union { union { uint32_t value; struct { - uint32_t set_0xa4_48 : 8; // @ 7 -- 0 # 0xffffff00 - uint32_t set_0xa3_49 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t riu_inbdpowsupthrdbm : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t riu_inbdpowinfthrdbm : 8; // @ 15 -- 8 # 0xffff00ff uint32_t pad0 : 8; - uint32_t set_0x18_18 : 8; // @ 31 -- 24 # 0xffffff + uint32_t riu_idinbdpowgapdnqdbm : 8; // @ 31 -- 24 # 0xffffff }; } r0xb3c0; // @ 0x3c0 union { uint32_t value; struct { - uint32_t set_0xce_6 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t riu_adcpowsupthrdbm : 8; // @ 7 -- 0 # 0xffffff00 }; } r0xb3c4; // @ 0x3c4 uint8_t pad7[0x4c]; @@ -190,7 +190,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 12; - uint32_t set_0x2_62 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t riu_fe20gain : 2; // @ 13 -- 12 # 0xffffcfff }; } r0xb500; // @ 0x500 uint8_t pad10[0xb1c]; @@ -198,7 +198,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 16; - uint32_t set_0x14_60 : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t riu_htstfgainen : 10; // @ 25 -- 16 # 0xfc00ffff }; } r0xc020; // @ 0x1020 uint8_t pad11[0x1c]; @@ -206,15 +206,15 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 15; - uint32_t set_0x3_44 : 5; // @ 19 -- 15 # 0xfff07fff - uint32_t set_0xc_43 : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t rc2_rx0_vga_idx_min : 5; // @ 19 -- 15 # 0xfff07fff + uint32_t rc2_rx0_vga_idx_max : 5; // @ 24 -- 20 # 0xfe0fffff }; } r0xc040; // @ 0x1040 union { uint32_t value; struct { - uint32_t set_0x0_46 : 8; // @ 7 -- 0 # 0xffffff00 - uint32_t set_0x8_45 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t rc2_rx0_lna_idx_min : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t rc2_rx0_lna_idx_max : 8; // @ 15 -- 8 # 0xffff00ff }; } r0xc044; // @ 0x1044 uint8_t pad12[0x38]; @@ -230,55 +230,56 @@ typedef union { union { uint32_t value; struct { - uint32_t set_0x0_42 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t rc2_pkdet_mode : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t rc2_pkdet_cnt_thr : 4; // @ 5 -- 2 # 0xffffffc3 }; } r0xc814; // @ 0x1814 uint8_t pad15[0x14]; union { uint32_t value; struct { - uint32_t set_0xb5_50 : 8; // @ 7 -- 0 # 0xffffff00 - uint32_t set_0x1_51 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t rc2_inbdpow_adj_thr_dbm : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t rc2_inbdpowsupthr_adj_en : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad0 : 2; - uint32_t set_0x1_52 : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t rc2_inbdpowinfthr_adj_en : 1; // @ 11 -- 11 # 0xfffff7ff uint32_t pad1 : 3; - uint32_t set_0x40_59 : 9; // @ 23 -- 15 # 0xff007fff + uint32_t rc2_inbdpowfastvalid_cnt : 9; // @ 23 -- 15 # 0xff007fff }; } r0xc82c; // @ 0x182c union { uint32_t value; struct { uint32_t pad0 : 10; - uint32_t set_0x5_41 : 3; // @ 12 -- 10 # 0xffffe3ff + uint32_t rc2_evt4opcomb : 3; // @ 12 -- 10 # 0xffffe3ff uint32_t pad1 : 1; - uint32_t set_0x36_40 : 6; // @ 19 -- 14 # 0xfff03fff - uint32_t set_0x1_39 : 6; // @ 25 -- 20 # 0xfc0fffff - uint32_t set_0x3f_38 : 6; // @ 31 -- 26 # 0x3ffffff + uint32_t rc2_evt4op3 : 6; // @ 19 -- 14 # 0xfff03fff + uint32_t rc2_evt4op2 : 6; // @ 25 -- 20 # 0xfc0fffff + uint32_t rc2_evt4op1 : 6; // @ 31 -- 26 # 0x3ffffff }; } r0xc830; // @ 0x1830 uint8_t pad16[0x4]; union { uint32_t value; struct { - uint32_t set_0x100_54 : 19; // @ 18 -- 0 # 0xfff80000 + uint32_t rc2_reflevofdmthd : 19; // @ 18 -- 0 # 0xfff80000 uint32_t pad0 : 12; - uint32_t set_0x1_53 : 1; // @ 31 -- 31 # 0x7fffffff + uint32_t rc2_reflevofdmthd_en : 1; // @ 31 -- 31 # 0x7fffffff }; } r0xc838; // @ 0x1838 union { uint32_t value; struct { - uint32_t set_0x17c_56 : 20; // @ 19 -- 0 # 0xfff00000 + uint32_t rc2_reflevdsssthd : 20; // @ 19 -- 0 # 0xfff00000 uint32_t pad0 : 11; - uint32_t set_0x1_55 : 1; // @ 31 -- 31 # 0x7fffffff + uint32_t rc2_reflevdsssthd_en : 1; // @ 31 -- 31 # 0x7fffffff }; } r0xc83c; // @ 0x183c union { uint32_t value; struct { - uint32_t set_0x100_58 : 22; // @ 21 -- 0 # 0xffc00000 + uint32_t rc2_reflevdssscontthd : 22; // @ 21 -- 0 # 0xffc00000 uint32_t pad0 : 9; - uint32_t set_0x1_57 : 1; // @ 31 -- 31 # 0x7fffffff + uint32_t rc2_reflevdssscontthd_en : 1; // @ 31 -- 31 # 0x7fffffff }; } r0xc840; // @ 0x1840 }; diff --git a/src/include/phy/bz_phy.h b/src/include/phy/bz_phy.h index a2ba2df..2259841 100644 --- a/src/include/phy/bz_phy.h +++ b/src/include/phy/bz_phy.h @@ -7,41 +7,41 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 23; - uint32_t set_0x1_67 : 1; // @ 23 -- 23 # 0xff7fffff - uint32_t set_0x8_68 : 8; // @ 31 -- 24 # 0xffffff + uint32_t bz_phy_tx_rampup_fm_on : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t bz_phy_tx_rampup_time_us : 8; // @ 31 -- 24 # 0xffffff }; } r0x2808; // @ 0x808 union { uint32_t value; struct { - uint32_t set_0x0_71 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t bz_phy_tx_rampdn_pad0_time_us : 8; // @ 7 -- 0 # 0xffffff00 uint32_t pad0 : 15; - uint32_t set_0x1_69 : 1; // @ 23 -- 23 # 0xff7fffff - uint32_t set_0x4_70 : 8; // @ 31 -- 24 # 0xffffff + uint32_t bz_phy_tx_rampdn_fm_on : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t bz_phy_tx_rampdn_time_us : 8; // @ 31 -- 24 # 0xffffff }; } r0x280c; // @ 0x80c union { uint32_t value; struct { - uint32_t set_0x0_76 : 1; // @ 0 -- 0 # 0xfffffffe - uint32_t set_0x1_77 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t bz_phy_rx_dfe_notch_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t bz_phy_rx_dfe_toc_en : 1; // @ 1 -- 1 # 0xfffffffd }; } r0x2810; // @ 0x810 uint8_t pad1[0x40]; union { uint32_t value; struct { - uint32_t set_0x1e_75 : 8; // @ 7 -- 0 # 0xffffff00 - uint32_t set_0x20_72 : 8; // @ 15 -- 8 # 0xffff00ff - uint32_t set_0xa_74 : 8; // @ 23 -- 16 # 0xff00ffff - uint32_t set_0x1e_73 : 8; // @ 31 -- 24 # 0xffffff + uint32_t bz_phy_rx_proc_time_viterbi_us : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t bz_phy_rx_proc_time_mlsd_us : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t bz_phy_rx_proc_time_eq_us : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t bz_phy_rx_proc_time_direct_us : 8; // @ 31 -- 24 # 0xffffff }; } r0x2854; // @ 0x854 uint8_t pad2[0x454]; union { uint32_t value; struct { - uint32_t set_0x4_78 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t bz_agc_rbb_ind_min : 5; // @ 4 -- 0 # 0xffffffe0 }; } r0x2cac; // @ 0xcac }; diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index 8bdd17f..62a5a81 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -116,9 +116,9 @@ typedef union { uint32_t pad0 : 27; uint32_t resetto1 : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t pad1 : 1; - uint32_t set1beforewriteagcmem : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t mdm_agcmemclkforce : 1; // @ 29 -- 29 # 0xdfffffff }; - } r874; // @ 0x874 + } r0x874; // @ 0x874 uint8_t pad6[0x10]; union { uint32_t value; From 80069a967bf92bc6e1bfc4db1307371a29c4b985 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 04:31:36 -0500 Subject: [PATCH 030/148] import other DWARF info and done --- script/manualext.py | 70 ++++++++++++++++++------------------- src/include/phy/agc.h | 8 ++--- src/include/phy/dma.h | 10 +++--- src/include/phy/mdm.h | 34 +++++++++--------- src/include/phy/sysctrl.h | 12 ++++--- src/include/phy/sysctrl92.h | 2 +- 6 files changed, 69 insertions(+), 67 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 0912ee3..6693cb3 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -12,33 +12,33 @@ Field('txcbwmax', 0xfcffffff) # Channel bandwidth Field('txnssmax', 0xffffff8f) # number of spatial streams Field('ntxmax', 0xff8fffff) # tx chan? -Field('v18', 0xfffffeff) # some switch? DAT_44c00000>>18 +Field('txldpcen', 0xfffffeff) # some switch? DAT_44c00000>>18 Field('vht', 0xfffffffd) # very high throughput -Field('v31', 0xfffeffff) # some switch? DAT_44c00000>>31 +Field('txmumimoen', 0xfffeffff) # some switch? DAT_44c00000>>31 Reg('rxchan', 0x44c00820) Field('rxcbwmax', 0xfcffffff) # Channel bandwidth Field('rxnssmax', 0xffffff8f) # number of spatial streams # Field('nrxmax', 0xff8fffff) # not exists -Field('v19', 0xfffffeff) # some switch? DAT_44c00000>>19 -Field('vht', 0xfffffffd) # very high throughput -Field('v30', 0xfffeffff) # some switch? DAT_44c00000>>30 -Field('_v30', 0xffefffff) # some switch? DAT_44c00000>>30 -FieldBit('reset', 0) # set 1 in phy_hw_set_channel for.. reset? +Field('rxldpcen', 0xfffffeff) # some switch? DAT_44c00000>>19 +Field('rxvhten', 0xfffffffd) # very high throughput +Field('rxmumimoen', 0xfffeffff) # some switch? DAT_44c00000>>30 +Field('rxmumimoapeplenen', 0xffefffff) # some switch? DAT_44c00000>>30 +FieldBit('rxdsssen', 0) # set 1 in phy_hw_set_channel for.. reset? Field('rxndpnstsmax', 0xffff8fff) Reg('version', 0x44c00000) FieldBit('vht', 31-9) FieldBit('nss', 8, 4) # phy_get_nss (nss + 1) -FieldBit('rxndpnstsmax', 0xc, 4) -FieldBit('v18', 0x12) -FieldBit('v19', 0x13) +FieldBit('nsts', 0xc, 4) +FieldBit('ldpcenc', 0x12) +FieldBit('ldpcdec', 0x13) FieldBit('mu_mimo_rx', 0x1e) FieldBit('mu_mimo_tx', 0x1f) FieldBit('ldpctx', 0x1a) FieldBit('ldpcrx', 0x1b) FieldBit('ntx', 4, 4) # phy_get_ntx (ntx + 1) -FieldBit('txcbwmax', 0x18, 2) +FieldBit('chbw', 0x18, 2) FieldBit('bfmee_supported', 0x1c) FieldBit('bfmer_supported', 0x1d) @@ -50,9 +50,9 @@ FieldBit('FSMSWRESET', 4) FieldBit('MDMSWRESET', 0) -Reg('TXCTRL0', 0x44c00838) -Reg('TXCTRL1', 0x44c0088c) -Reg('TXCTRL3', 0x44c00898) +Reg('txstartdelay', 0x44c00838) +Reg('txctrl1', 0x44c0088c) +Reg('txctrl3', 0x44c00898) Reg('TBECTRL0', 0x44c00858) Field('tbe_count_adjust_20', 0xffffff00) @@ -62,8 +62,8 @@ Field('WAITHTSTF', 0xffffff80) Reg('r834', 0x44c00834) -Field('set60h', 0x00ffffff) -FieldBit('set1', 0) +Field('tddchtstfmargin', 0x00ffffff) +FieldBit('rxtdctrl1', 0) Reg('SMOOTHCTRL', 0x44c00818) FieldBit('TDCYCROTVAL20', 0, 8) @@ -93,7 +93,7 @@ Reg('rxctrl1', 0x44c0083c) # reset to 0x4920492 Reg('r0x874', 0x44c00874) -Field('resetto1', 0xf7ffffff) +Field('rcclkforce', 0xf7ffffff) Field('mdm_agcmemclkforce', 0xdfffffff) #print('\n'.join(GenSVD())) @@ -116,9 +116,9 @@ Reg('RWNXAGCCNTL', 0x44c0b390) -Field('set1', 0xfffffffc) +Field('combpathsel', 0xfffffffc) Field('agcfsmreset', 0xffffefff) # set 1 before agc mem, maybe - +Field('rifsdeten', 0xfffffbff) Reg('riu_rwnxagcaci20marg0', 0x44c0b340) Reg('riu_rwnxagcaci20marg1', 0x44c0b344) Reg('riu_rwnxagcaci20marg2', 0x44c0b348) @@ -132,13 +132,14 @@ Reg('irqmacccatimeouten', 0x44c0b414) Field('set1', 0xFFFFFEFF) -Reg('r41c', 0x44c0b41c) +Reg('rwnxmacintstatmasked', 0x44c0b41c) FieldBit('needreset', 8) # guess -Reg('r420_copy41c', 0x44c0b420) + +Reg('rwnxmacintack', 0x44c0b420) Reg('rc218', 0x44c0c218) -Field('set0', 0xffff0000) +Field('txhbf20coeffsel', 0xffff0000) Buf('rxgain_offset_vs_temperature', 0x44c0c080, 0x44c0c088, 1) @@ -347,13 +348,13 @@ def getregs(fname, pattern='name'): peris['dma'] = Peripheral(peripheral('dma', 0x44a00000, 0x1000)) -Reg('status', 0x44a00024) +Reg('int_status', 0x44a00024) Field("TX", 0x1f) FieldBit("RXHeader", 5) ## guess FieldBit("RXPayload", 6) ## guess FieldBit("b8", 8) -Reg('tx_reset', 0x44a00020) # my guess, setting of r20 should reset 0x24?? +Reg('int_ack', 0x44a00020) # my guess, setting of r20 should reset 0x24?? # kind like response... FieldBit("b8", 8) # set at txl_cfm_dma_int_handler FieldBit("b7", 7) # set at ipc_emb_dbg_dma_int_handler @@ -362,9 +363,10 @@ def getregs(fname, pattern='name'): Field("TX", 0x1f) Reg("dma_status", 0x44a00010) -Field("busyatffff", 0xffff) +Field("dma_status_oft_free", 0xffff) # my guess!! +# access with dma_lli_counter_get(reg_idx) Reg('TX_BCN', 0x44a00080) FieldBit('bridgedmacnt', 0, 16) Reg('TX_AC_0', 0x44a00084) @@ -377,9 +379,9 @@ def getregs(fname, pattern='name'): FieldBit('bridgedmacnt', 0, 16) Reg('LinkListItem0', 0x44a000a4) -FieldBit("lli", 0, 16) +FieldBit("counter", 0, 16) Reg('LinkListItem1', 0x44a000ac) -FieldBit("lli", 0, 16) +FieldBit("counter", 0, 16) #open('../src/include/phy/dma.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) @@ -390,16 +392,14 @@ def getregs(fname, pattern='name'): peris['sysctrl'] = Peripheral(peripheral('sysctrl', 0x44900000, 0x1000)) Reg('time', 0x44900084) FieldBit('time_greater_on_bit12', 0) -Reg("sysctrl_r68", 0x44900068) # set to 0x8000000c for init -Reg("sysctrl_re0", 0x449000e0) # or with 0x1ff00 -Field("set1", (~0x1ff00) & 0xffffffff) +Reg("diag_conf", 0x44900068) # set to 0x8000000c for init +Field("diag_sel", 0xffff0000) +Reg("misc_cntl", 0x449000e0) # or with 0x1ff00 +Field("set1", (~0x1ff00) & 0xffffffff) -## two regs for helper_record_all_states -Reg("r068", 0x44900068) -Field("set14", 0xffff0000) -Reg("r074", 0x44900068) # set to b09 +Reg("r074", 0x44900074) # set to b09 #open('../src/include/phy/sysctrl.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) @@ -410,7 +410,7 @@ def getregs(fname, pattern='name'): ## wtf is this??? peris['sysctrl92'] = Peripheral(peripheral('sysctrl92', 0x44920000, 0x1000)) -Reg("set5010001f", 0x44920004) +Reg("ptr_config", 0x44920004) #open('../src/include/phy/sysctrl92.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h index 15fc4a8..465cc73 100644 --- a/src/include/phy/agc.h +++ b/src/include/phy/agc.h @@ -112,7 +112,7 @@ typedef union { union { uint32_t value; struct { - uint32_t set1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t combpathsel : 2; // @ 1 -- 0 # 0xfffffffc uint32_t pad0 : 6; uint32_t riu_rifsdeten : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad1 : 1; @@ -183,8 +183,8 @@ typedef union { uint32_t pad0 : 8; uint32_t needreset : 1; // @ 8 -- 8 # 0xfffffeff }; - } r41c; // @ 0x41c - uint32_t r420_copy41c; // @ 0x420 + } rwnxmacintstatmasked; // @ 0x41c + uint32_t rwnxmacintack; // @ 0x420 uint8_t pad9[0xdc]; union { uint32_t value; @@ -223,7 +223,7 @@ typedef union { union { uint32_t value; struct { - uint32_t set0 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t txhbf20coeffsel : 16; // @ 15 -- 0 # 0xffff0000 }; } rc218; // @ 0x1218 uint8_t pad14[0x5f8]; diff --git a/src/include/phy/dma.h b/src/include/phy/dma.h index 708712e..9525c12 100644 --- a/src/include/phy/dma.h +++ b/src/include/phy/dma.h @@ -7,7 +7,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 16; - uint32_t busyatffff : 16; // @ 31 -- 16 # 0xffff + uint32_t dma_status_oft_free : 16; // @ 31 -- 16 # 0xffff }; } dma_status; // @ 0x10 uint8_t pad1[0xc]; @@ -21,7 +21,7 @@ typedef union { uint32_t b8 : 1; // @ 8 -- 8 # 0xfffffeff uint32_t TX : 27; // @ 31 -- 5 # 0x1f }; - } tx_reset; // @ 0x20 + } int_ack; // @ 0x20 union { uint32_t value; struct { @@ -32,7 +32,7 @@ typedef union { uint32_t b8 : 1; // @ 8 -- 8 # 0xfffffeff uint32_t TX : 27; // @ 31 -- 5 # 0x1f }; - } status; // @ 0x24 + } int_status; // @ 0x24 uint8_t pad2[0x58]; union { uint32_t value; @@ -68,14 +68,14 @@ typedef union { union { uint32_t value; struct { - uint32_t lli : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t counter : 16; // @ 15 -- 0 # 0xffff0000 }; } LinkListItem0; // @ 0xa4 uint8_t pad4[0x4]; union { uint32_t value; struct { - uint32_t lli : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t counter : 16; // @ 15 -- 0 # 0xffff0000 }; } LinkListItem1; // @ 0xac }; diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index 62a5a81..341242e 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -8,14 +8,14 @@ typedef union { uint32_t pad0 : 4; uint32_t ntx : 4; // @ 7 -- 4 # 0xffffff0f uint32_t nss : 4; // @ 11 -- 8 # 0xfffff0ff - uint32_t rxndpnstsmax : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t nsts : 4; // @ 15 -- 12 # 0xffff0fff uint32_t pad1 : 2; - uint32_t v18 : 1; // @ 18 -- 18 # 0xfffbffff - uint32_t v19 : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ldpcenc : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ldpcdec : 1; // @ 19 -- 19 # 0xfff7ffff uint32_t pad2 : 2; uint32_t vht : 1; // @ 22 -- 22 # 0xffbfffff uint32_t pad3 : 1; - uint32_t txcbwmax : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t chbw : 2; // @ 25 -- 24 # 0xfcffffff uint32_t ldpctx : 1; // @ 26 -- 26 # 0xfbffffff uint32_t ldpcrx : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t bfmee_supported : 1; // @ 28 -- 28 # 0xefffffff @@ -49,18 +49,18 @@ typedef union { union { uint32_t value; struct { - uint32_t reset : 1; // @ 0 -- 0 # 0xfffffffe - uint32_t vht : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rxdsssen : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rxvhten : 1; // @ 1 -- 1 # 0xfffffffd uint32_t pad0 : 2; uint32_t rxnssmax : 3; // @ 6 -- 4 # 0xffffff8f uint32_t pad1 : 1; - uint32_t v19 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t rxldpcen : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad2 : 3; uint32_t rxndpnstsmax : 3; // @ 14 -- 12 # 0xffff8fff uint32_t pad3 : 1; - uint32_t v30 : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t rxmumimoen : 1; // @ 16 -- 16 # 0xfffeffff uint32_t pad4 : 3; - uint32_t _v30 : 1; // @ 20 -- 20 # 0xffefffff + uint32_t rxmumimoapeplenen : 1; // @ 20 -- 20 # 0xffefffff uint32_t pad5 : 3; uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff }; @@ -73,9 +73,9 @@ typedef union { uint32_t pad1 : 2; uint32_t txnssmax : 3; // @ 6 -- 4 # 0xffffff8f uint32_t pad2 : 1; - uint32_t v18 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t txldpcen : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad3 : 7; - uint32_t v31 : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t txmumimoen : 1; // @ 16 -- 16 # 0xfffeffff uint32_t pad4 : 3; uint32_t ntxmax : 3; // @ 22 -- 20 # 0xff8fffff uint32_t pad5 : 1; @@ -93,12 +93,12 @@ typedef union { union { uint32_t value; struct { - uint32_t set1 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rxtdctrl1 : 1; // @ 0 -- 0 # 0xfffffffe uint32_t pad0 : 23; - uint32_t set60h : 8; // @ 31 -- 24 # 0xffffff + uint32_t tddchtstfmargin : 8; // @ 31 -- 24 # 0xffffff }; } r834; // @ 0x834 - uint32_t TXCTRL0; // @ 0x838 + uint32_t txstartdelay; // @ 0x838 uint32_t rxctrl1; // @ 0x83c uint8_t pad3[0x18]; union { @@ -114,7 +114,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 27; - uint32_t resetto1 : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t rcclkforce : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t pad1 : 1; uint32_t mdm_agcmemclkforce : 1; // @ 29 -- 29 # 0xdfffffff }; @@ -132,9 +132,9 @@ typedef union { uint32_t AGCSWRESET : 1; // @ 12 -- 12 # 0xffffefff }; } swreset; // @ 0x888 - uint32_t TXCTRL1; // @ 0x88c + uint32_t txctrl1; // @ 0x88c uint8_t pad7[0x8]; - uint32_t TXCTRL3; // @ 0x898 + uint32_t txctrl3; // @ 0x898 uint32_t rxframeviolationmask; // @ 0x89c uint8_t pad8[0x2784]; union { diff --git a/src/include/phy/sysctrl.h b/src/include/phy/sysctrl.h index eeb0009..208b8c3 100644 --- a/src/include/phy/sysctrl.h +++ b/src/include/phy/sysctrl.h @@ -6,24 +6,26 @@ typedef union { union { uint32_t value; struct { - uint32_t set14 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t diag_sel : 16; // @ 15 -- 0 # 0xffff0000 }; - } sysctrl_r68; // @ 0x68 - uint8_t pad1[0x18]; + } diag_conf; // @ 0x68 + uint8_t pad1[0x8]; + uint32_t r074; // @ 0x74 + uint8_t pad2[0xc]; union { uint32_t value; struct { uint32_t time_greater_on_bit12 : 1; // @ 0 -- 0 # 0xfffffffe }; } time; // @ 0x84 - uint8_t pad2[0x58]; + uint8_t pad3[0x58]; union { uint32_t value; struct { uint32_t pad0 : 8; uint32_t set1 : 9; // @ 16 -- 8 # 0xfffe00ff }; - } sysctrl_re0; // @ 0xe0 + } misc_cntl; // @ 0xe0 }; } sysctrl_regs; #define SYSCTRL_BASE 0x44900000 diff --git a/src/include/phy/sysctrl92.h b/src/include/phy/sysctrl92.h index 53c2e7c..a137b6b 100644 --- a/src/include/phy/sysctrl92.h +++ b/src/include/phy/sysctrl92.h @@ -3,7 +3,7 @@ typedef union { uint8_t pad[0x1000]; struct { uint8_t pad0[0x4]; - uint32_t set5010001f; // @ 0x4 + uint32_t ptr_config; // @ 0x4 }; } sysctrl92_regs; #define SYSCTRL92_BASE 0x44920000 From 16d67b82d78d900835cef2ec91a96f386de27563 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 04:34:09 -0500 Subject: [PATCH 031/148] padding to 32 --- script/reglib.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/script/reglib.py b/script/reglib.py index 05a4fe7..7db82d2 100755 --- a/script/reglib.py +++ b/script/reglib.py @@ -97,6 +97,8 @@ def genHeader(self): padId = padId + 1 s.extend(ident(i.genHeader(), 2, '\t')) currentBit = i.msb + 1 + if currentBit != 32: + s.append(f'\t\tuint32_t pad{padId} : {32 - currentBit};') s.extend([ "\t};", @@ -290,6 +292,12 @@ def FieldBit(name, bit, len=1): context.r.addField(name, (~(((2**len)-1)< Date: Sat, 24 Jul 2021 04:34:28 -0500 Subject: [PATCH 032/148] done --- src/include/phy/agc.h | 21 ++++++++++++++++ src/include/phy/bz_phy.h | 2 ++ src/include/phy/dma.h | 7 ++++++ src/include/phy/mac_core.h | 50 ++++++++++++++++++++++++++++++++++++++ src/include/phy/mac_pl.h | 23 ++++++++++++++++++ src/include/phy/mdm.h | 9 +++++++ src/include/phy/sysctrl.h | 3 +++ 7 files changed, 115 insertions(+) diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h index 465cc73..c89c8ad 100644 --- a/src/include/phy/agc.h +++ b/src/include/phy/agc.h @@ -7,6 +7,7 @@ typedef union { struct { uint32_t pad0 : 21; uint32_t iqcomp : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad1 : 10; }; } r000; // @ 0x0 uint32_t activeant; // @ 0x4 @@ -18,6 +19,7 @@ typedef union { uint32_t riu_adcpowmindbm : 1; // @ 1 -- 1 # 0xfffffffd uint32_t riu_vpeakadcqdbv : 1; // @ 2 -- 2 # 0xfffffffb uint32_t riu_fe40gain : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; }; } r0xb110; // @ 0x110 uint8_t pad1[0x4]; @@ -37,6 +39,7 @@ typedef union { uint32_t riu_sathighthrdbv : 6; // @ 21 -- 16 # 0xffc0ffff uint32_t pad2 : 2; uint32_t riu_satdelay50ns : 5; // @ 28 -- 24 # 0xe0ffffff + uint32_t pad3 : 3; }; } r0xb364; // @ 0x364 union { @@ -45,6 +48,7 @@ typedef union { uint32_t riu_crossupthrqdbm : 10; // @ 9 -- 0 # 0xfffffc00 uint32_t pad0 : 2; uint32_t riu_crossdnthrqdbm : 10; // @ 21 -- 12 # 0xffc00fff + uint32_t pad1 : 10; }; } r0xb368; // @ 0x368 union { @@ -55,6 +59,7 @@ typedef union { uint32_t pad0 : 5; uint32_t riu_rampdngapqdb : 8; // @ 23 -- 16 # 0xff00ffff uint32_t riu_rampdnndlindex : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad1 : 5; }; } RWNXAGCRAMP; // @ 0x36c union { @@ -62,6 +67,7 @@ typedef union { struct { uint32_t pad0 : 16; uint32_t riu_adcpowdisthrdbv : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad1 : 9; }; } r0xb370; // @ 0x370 uint8_t pad4[0xc]; @@ -121,6 +127,7 @@ typedef union { uint32_t agcfsmreset : 1; // @ 12 -- 12 # 0xffffefff uint32_t pad3 : 3; uint32_t riu_htstfgainen : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 15; }; } RWNXAGCCNTL; // @ 0x390 union { @@ -128,6 +135,7 @@ typedef union { struct { uint32_t pad0 : 16; uint32_t riu_vpeakadcqdbv : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad1 : 8; }; } r0xb394; // @ 0x394 union { @@ -135,6 +143,7 @@ typedef union { struct { uint32_t pad0 : 8; uint32_t riu_adcpowmindbm : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad1 : 16; }; } r0xb398; // @ 0x398 uint8_t pad5[0x4]; @@ -142,6 +151,7 @@ typedef union { uint32_t value; struct { uint32_t riu_inbdpowmindbm : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; }; } r0xb3a0; // @ 0x3a0 union { @@ -149,6 +159,7 @@ typedef union { struct { uint32_t riu_fe20gain : 8; // @ 7 -- 0 # 0xffffff00 uint32_t riu_fe40gain : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } r0xb3a4; // @ 0x3a4 uint8_t pad6[0x14]; @@ -166,6 +177,7 @@ typedef union { uint32_t value; struct { uint32_t riu_adcpowsupthrdbm : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; }; } r0xb3c4; // @ 0x3c4 uint8_t pad7[0x4c]; @@ -174,6 +186,7 @@ typedef union { struct { uint32_t pad0 : 8; uint32_t set1 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 23; }; } irqmacccatimeouten; // @ 0x414 uint8_t pad8[0x4]; @@ -182,6 +195,7 @@ typedef union { struct { uint32_t pad0 : 8; uint32_t needreset : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 23; }; } rwnxmacintstatmasked; // @ 0x41c uint32_t rwnxmacintack; // @ 0x420 @@ -191,6 +205,7 @@ typedef union { struct { uint32_t pad0 : 12; uint32_t riu_fe20gain : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pad1 : 18; }; } r0xb500; // @ 0x500 uint8_t pad10[0xb1c]; @@ -199,6 +214,7 @@ typedef union { struct { uint32_t pad0 : 16; uint32_t riu_htstfgainen : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 6; }; } r0xc020; // @ 0x1020 uint8_t pad11[0x1c]; @@ -208,6 +224,7 @@ typedef union { uint32_t pad0 : 15; uint32_t rc2_rx0_vga_idx_min : 5; // @ 19 -- 15 # 0xfff07fff uint32_t rc2_rx0_vga_idx_max : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t pad1 : 7; }; } r0xc040; // @ 0x1040 union { @@ -215,6 +232,7 @@ typedef union { struct { uint32_t rc2_rx0_lna_idx_min : 8; // @ 7 -- 0 # 0xffffff00 uint32_t rc2_rx0_lna_idx_max : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } r0xc044; // @ 0x1044 uint8_t pad12[0x38]; @@ -224,6 +242,7 @@ typedef union { uint32_t value; struct { uint32_t txhbf20coeffsel : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } rc218; // @ 0x1218 uint8_t pad14[0x5f8]; @@ -232,6 +251,7 @@ typedef union { struct { uint32_t rc2_pkdet_mode : 2; // @ 1 -- 0 # 0xfffffffc uint32_t rc2_pkdet_cnt_thr : 4; // @ 5 -- 2 # 0xffffffc3 + uint32_t pad0 : 26; }; } r0xc814; // @ 0x1814 uint8_t pad15[0x14]; @@ -244,6 +264,7 @@ typedef union { uint32_t rc2_inbdpowinfthr_adj_en : 1; // @ 11 -- 11 # 0xfffff7ff uint32_t pad1 : 3; uint32_t rc2_inbdpowfastvalid_cnt : 9; // @ 23 -- 15 # 0xff007fff + uint32_t pad2 : 8; }; } r0xc82c; // @ 0x182c union { diff --git a/src/include/phy/bz_phy.h b/src/include/phy/bz_phy.h index 2259841..f44f20d 100644 --- a/src/include/phy/bz_phy.h +++ b/src/include/phy/bz_phy.h @@ -25,6 +25,7 @@ typedef union { struct { uint32_t bz_phy_rx_dfe_notch_en : 1; // @ 0 -- 0 # 0xfffffffe uint32_t bz_phy_rx_dfe_toc_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; }; } r0x2810; // @ 0x810 uint8_t pad1[0x40]; @@ -42,6 +43,7 @@ typedef union { uint32_t value; struct { uint32_t bz_agc_rbb_ind_min : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 27; }; } r0x2cac; // @ 0xcac }; diff --git a/src/include/phy/dma.h b/src/include/phy/dma.h index 9525c12..9c4e2fd 100644 --- a/src/include/phy/dma.h +++ b/src/include/phy/dma.h @@ -38,30 +38,35 @@ typedef union { uint32_t value; struct { uint32_t bridgedmacnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } TX_BCN; // @ 0x80 union { uint32_t value; struct { uint32_t bridgedmacnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } TX_AC_0; // @ 0x84 union { uint32_t value; struct { uint32_t bridgedmacnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } TX_AC_1; // @ 0x88 union { uint32_t value; struct { uint32_t bridgedmacnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } TX_AC_2; // @ 0x8c union { uint32_t value; struct { uint32_t bridgedmacnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } TX_AC_3; // @ 0x90 uint8_t pad3[0x10]; @@ -69,6 +74,7 @@ typedef union { uint32_t value; struct { uint32_t counter : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } LinkListItem0; // @ 0xa4 uint8_t pad4[0x4]; @@ -76,6 +82,7 @@ typedef union { uint32_t value; struct { uint32_t counter : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } LinkListItem1; // @ 0xac }; diff --git a/src/include/phy/mac_core.h b/src/include/phy/mac_core.h index c434fec..f869d75 100644 --- a/src/include/phy/mac_core.h +++ b/src/include/phy/mac_core.h @@ -28,6 +28,7 @@ typedef union { uint32_t coex : 1; // @ 14 -- 14 # 0xffffbfff uint32_t pad1 : 1; uint32_t mac80211MHFormat : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 15; }; } VERSION_1; // @ 0x4 union { @@ -37,12 +38,14 @@ typedef union { uint32_t ieRelease : 1; // @ 7 -- 7 # 0xffffff7f uint32_t releaseNumber : 6; // @ 13 -- 8 # 0xffffc0ff uint32_t phaseNumber : 3; // @ 16 -- 14 # 0xfffe3fff + uint32_t pad0 : 15; }; } VERSION_2; // @ 0x8 union { uint32_t value; struct { uint32_t bitmapCnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } BITMAP_CNT; // @ 0xc union { @@ -55,6 +58,7 @@ typedef union { uint32_t value; struct { uint32_t macAddrHigh : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } MAC_ADDR_HI; // @ 0x14 union { @@ -67,6 +71,7 @@ typedef union { uint32_t value; struct { uint32_t macAddrHighMask : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } MAC_ADDR_HI_MASK; // @ 0x1c union { @@ -79,6 +84,7 @@ typedef union { uint32_t value; struct { uint32_t bssIDHigh : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } BSS_ID_HI; // @ 0x24 union { @@ -91,6 +97,7 @@ typedef union { uint32_t value; struct { uint32_t bssIDHighMask : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } BSS_ID_HI_MASK; // @ 0x2c uint8_t pad0[0x8]; @@ -99,12 +106,14 @@ typedef union { struct { uint32_t currentState : 4; // @ 3 -- 0 # 0xfffffff0 uint32_t nextState : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t pad0 : 24; }; } STATE_CNTRL; // @ 0x38 union { uint32_t value; struct { uint32_t probeDelay : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } SCAN_CNTRL; // @ 0x3c uint8_t pad1[0x4]; @@ -138,6 +147,7 @@ typedef union { uint32_t tsfUpdatedBySW : 1; // @ 24 -- 24 # 0xfeffffff uint32_t tsfMgtDisable : 1; // @ 25 -- 25 # 0xfdffffff uint32_t rxRIFSEn : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad2 : 5; }; } MAC_CNTRL_1; // @ 0x4c uint8_t pad3[0x4]; @@ -154,6 +164,7 @@ typedef union { uint32_t baPSBitmapReset : 1; // @ 7 -- 7 # 0xffffff7f uint32_t pad0 : 8; uint32_t rxFlowCntrlEn : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad1 : 15; }; } MAC_ERR_REC_CNTRL; // @ 0x54 union { @@ -163,6 +174,7 @@ typedef union { uint32_t errInRxLevel1 : 1; // @ 1 -- 1 # 0xfffffffd uint32_t errInTxRxLevel2 : 1; // @ 2 -- 2 # 0xfffffffb uint32_t errInHWLevel3 : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; }; } MAC_ERR_SET_STATUS; // @ 0x58 union { @@ -172,6 +184,7 @@ typedef union { uint32_t clearErrInRxLevel1 : 1; // @ 1 -- 1 # 0xfffffffd uint32_t clearErrInTxRxLevel2 : 1; // @ 2 -- 2 # 0xfffffffb uint32_t clearErrInHWLevel3 : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; }; } MAC_ERR_CLEAR_STATUS; // @ 0x5c union { @@ -226,6 +239,7 @@ typedef union { uint32_t bcnUpdateOffset : 8; // @ 7 -- 0 # 0xffffff00 uint32_t timOffset : 8; // @ 15 -- 8 # 0xffff00ff uint32_t aid : 12; // @ 27 -- 16 # 0xf000ffff + uint32_t pad0 : 4; }; } BCN_CNTRL_2; // @ 0x68 uint8_t pad4[0x24]; @@ -242,6 +256,7 @@ typedef union { uint32_t value; struct { uint32_t cfpMaxDuration : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } DTIM_CFP_2; // @ 0x94 union { @@ -249,6 +264,7 @@ typedef union { struct { uint32_t dot11ShortRetryLimit : 8; // @ 7 -- 0 # 0xffffff00 uint32_t dot11LongRetryLimit : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } RETRY_LIMITS; // @ 0x98 union { @@ -258,6 +274,7 @@ typedef union { uint32_t bbServiceB : 8; // @ 23 -- 16 # 0xff00ffff uint32_t pad0 : 2; uint32_t maxPHYNtx : 3; // @ 28 -- 26 # 0xe3ffffff + uint32_t pad1 : 3; }; } BB_SERVICE; // @ 0x9c union { @@ -265,6 +282,7 @@ typedef union { struct { uint32_t ofdmMaxPwrLevel : 8; // @ 7 -- 0 # 0xffffff00 uint32_t dsssMaxPwrLevel : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } MAX_POWER_LEVEL; // @ 0xa0 uint8_t pad5[0x8]; @@ -302,6 +320,7 @@ typedef union { uint32_t value; struct { uint32_t macAddrRAMHigh : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } ENCR_MAC_ADDR_HIGH; // @ 0xc0 union { @@ -348,6 +367,7 @@ typedef union { uint32_t value; struct { uint32_t bssBasicRateSet : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 20; }; } RATES; // @ 0xdc union { @@ -364,6 +384,7 @@ typedef union { uint32_t macCoreClkFreq : 8; // @ 7 -- 0 # 0xffffff00 uint32_t txRFDelayInMACClk : 10; // @ 17 -- 8 # 0xfffc00ff uint32_t txChainDelayInMACClk : 10; // @ 27 -- 18 # 0xf003ffff + uint32_t pad0 : 4; }; } TIMINGS_1; // @ 0xe4 union { @@ -371,6 +392,7 @@ typedef union { struct { uint32_t slotTime : 8; // @ 7 -- 0 # 0xffffff00 uint32_t slotTimeInMACClk : 16; // @ 23 -- 8 # 0xff0000ff + uint32_t pad0 : 8; }; } TIMINGS_2; // @ 0xe8 union { @@ -379,6 +401,7 @@ typedef union { uint32_t macProcDelayInMACClk : 10; // @ 9 -- 0 # 0xfffffc00 uint32_t txDelayRFOnInMACClk : 10; // @ 19 -- 10 # 0xfff003ff uint32_t rxRFDelayInMACClk : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t pad0 : 2; }; } TIMINGS_3; // @ 0xec union { @@ -394,6 +417,7 @@ typedef union { struct { uint32_t sifsB : 8; // @ 7 -- 0 # 0xffffff00 uint32_t sifsBInMACClk : 16; // @ 23 -- 8 # 0xff0000ff + uint32_t pad0 : 8; }; } TIMINGS_5; // @ 0xf4 union { @@ -401,6 +425,7 @@ typedef union { struct { uint32_t sifsA : 8; // @ 7 -- 0 # 0xffffff00 uint32_t sifsAInMACClk : 16; // @ 23 -- 8 # 0xff0000ff + uint32_t pad0 : 8; }; } TIMINGS_6; // @ 0xf8 union { @@ -408,6 +433,7 @@ typedef union { struct { uint32_t rifs : 8; // @ 7 -- 0 # 0xffffff00 uint32_t rxCCADelay : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad0 : 20; }; } TIMINGS_7; // @ 0xfc union { @@ -425,6 +451,7 @@ typedef union { uint32_t txDMAProcDlyInMACClk : 10; // @ 9 -- 0 # 0xfffffc00 uint32_t rifsInMACClk : 10; // @ 19 -- 10 # 0xfff003ff uint32_t rifsTOInMACClk : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t pad0 : 2; }; } TIMINGS_9; // @ 0x104 uint8_t pad7[0x4]; @@ -433,6 +460,7 @@ typedef union { struct { uint32_t edcaTriggerTimer : 8; // @ 7 -- 0 # 0xffffff00 uint32_t hccaTriggerTimer : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } PROT_TRIG_TIMER; // @ 0x10c union { @@ -440,6 +468,7 @@ typedef union { struct { uint32_t txAbsoluteTimeout : 8; // @ 7 -- 0 # 0xffffff00 uint32_t txPacketTimeout : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } TX_TRIGGER_TIMER; // @ 0x110 union { @@ -448,6 +477,7 @@ typedef union { uint32_t rxAbsoluteTimeout : 8; // @ 7 -- 0 # 0xffffff00 uint32_t rxPacketTimeout : 8; // @ 15 -- 8 # 0xffff00ff uint32_t rxPayloadUsedCount : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad0 : 8; }; } RX_TRIGGER_TIMER; // @ 0x114 union { @@ -476,6 +506,7 @@ typedef union { uint32_t value; struct { uint32_t monotonicCounterHigh2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } MONOTONIC_COUNTER_2_HI; // @ 0x124 union { @@ -489,6 +520,7 @@ typedef union { uint32_t value; struct { uint32_t maxAllowedLength : 20; // @ 19 -- 0 # 0xfff00000 + uint32_t pad0 : 12; }; } MAX_RX_LENGTH; // @ 0x150 uint8_t pad9[0xac]; @@ -499,6 +531,7 @@ typedef union { uint32_t cwMin0 : 4; // @ 7 -- 4 # 0xffffff0f uint32_t cwMax0 : 4; // @ 11 -- 8 # 0xfffff0ff uint32_t txOpLimit0 : 16; // @ 27 -- 12 # 0xf0000fff + uint32_t pad0 : 4; }; } EDCA_AC_0; // @ 0x200 union { @@ -508,6 +541,7 @@ typedef union { uint32_t cwMin1 : 4; // @ 7 -- 4 # 0xffffff0f uint32_t cwMax1 : 4; // @ 11 -- 8 # 0xfffff0ff uint32_t txOpLimit1 : 16; // @ 27 -- 12 # 0xf0000fff + uint32_t pad0 : 4; }; } EDCA_AC_1; // @ 0x204 union { @@ -517,6 +551,7 @@ typedef union { uint32_t cwMin2 : 4; // @ 7 -- 4 # 0xffffff0f uint32_t cwMax2 : 4; // @ 11 -- 8 # 0xfffff0ff uint32_t txOpLimit2 : 16; // @ 27 -- 12 # 0xf0000fff + uint32_t pad0 : 4; }; } EDCA_AC_2; // @ 0x208 union { @@ -526,6 +561,7 @@ typedef union { uint32_t cwMin3 : 4; // @ 7 -- 4 # 0xffffff0f uint32_t cwMax3 : 4; // @ 11 -- 8 # 0xfffff0ff uint32_t txOpLimit3 : 16; // @ 27 -- 12 # 0xf0000fff + uint32_t pad0 : 4; }; } EDCA_AC_3; // @ 0x20c uint8_t pad10[0x10]; @@ -543,6 +579,7 @@ typedef union { uint32_t pad0 : 2; uint32_t remTXOPInDurField : 1; // @ 4 -- 4 # 0xffffffef uint32_t keepTXOPOpen : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 26; }; } EDCA_CNTRL; // @ 0x224 uint8_t pad11[0x58]; @@ -558,6 +595,7 @@ typedef union { uint32_t value; struct { uint32_t quietOffset1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } QUIET_ELEMENT_1B; // @ 0x284 union { @@ -572,6 +610,7 @@ typedef union { uint32_t value; struct { uint32_t quietOffset2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } QUIET_ELEMENT_2B; // @ 0x28c union { @@ -614,12 +653,14 @@ typedef union { uint32_t startTxFormatMod : 3; // @ 26 -- 24 # 0xf8ffffff uint32_t startTxPreType : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t startTxBW : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t pad1 : 2; }; } START_TX_1; // @ 0x304 union { uint32_t value; struct { uint32_t durControlFrm : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } START_TX_2; // @ 0x308 union { @@ -648,6 +689,7 @@ typedef union { uint32_t dynBWEn : 1; // @ 7 -- 7 # 0xffffff7f uint32_t aPPDUMaxTime : 8; // @ 15 -- 8 # 0xffff00ff uint32_t maxSupportedBW : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad0 : 14; }; } TX_BW_CNTRL; // @ 0x310 union { @@ -655,6 +697,7 @@ typedef union { struct { uint32_t bssBasicHTMCSSetEM : 16; // @ 15 -- 0 # 0xffff0000 uint32_t bssBasicHTMCSSetUM : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad0 : 10; }; } HTMCS; // @ 0x314 uint8_t pad13[0x4]; @@ -662,12 +705,14 @@ typedef union { uint32_t value; struct { uint32_t bssBasicVHTMCSSet : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } VHTMCS; // @ 0x31c union { uint32_t value; struct { uint32_t supportLSTP : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; }; } LSTP; // @ 0x320 uint8_t pad14[0xdc]; @@ -679,6 +724,7 @@ typedef union { uint32_t coexWlanChanOffset : 1; // @ 12 -- 12 # 0xffffefff uint32_t pad1 : 3; uint32_t coexWlanChanFreq : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 9; }; } COEX_CONTROL; // @ 0x400 union { @@ -727,12 +773,14 @@ typedef union { struct { uint32_t debugPortSel1 : 8; // @ 7 -- 0 # 0xffffff00 uint32_t debugPortSel2 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } DEBUG_PORT_SEL; // @ 0x510 union { uint32_t value; struct { uint32_t navCounter : 26; // @ 25 -- 0 # 0xfc000000 + uint32_t pad0 : 6; }; } DEBUG_NAV; // @ 0x514 union { @@ -745,6 +793,7 @@ typedef union { uint32_t activeAC : 2; // @ 17 -- 16 # 0xfffcffff uint32_t pad0 : 6; uint32_t backoffOffset : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad1 : 6; }; } DEBUG_CW; // @ 0x518 union { @@ -770,6 +819,7 @@ typedef union { uint32_t value; struct { uint32_t rxReqForceDeassertion : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; }; } DEBUG_PHY; // @ 0x55c }; diff --git a/src/include/phy/mac_pl.h b/src/include/phy/mac_pl.h index 3c9c7ad..918266a 100644 --- a/src/include/phy/mac_pl.h +++ b/src/include/phy/mac_pl.h @@ -7,6 +7,7 @@ typedef union { uint32_t value; struct { uint32_t nextTBTT : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } NEXT_TBTT; // @ 0x40 uint8_t pad1[0x4]; @@ -23,6 +24,7 @@ typedef union { uint32_t value; struct { uint32_t softReset : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; }; } MAC_CNTRL_2; // @ 0x50 uint8_t pad3[0x18]; @@ -55,6 +57,7 @@ typedef union { uint32_t phyRxStart : 1; // @ 23 -- 23 # 0xff7fffff uint32_t rxHeaderDMADead : 1; // @ 24 -- 24 # 0xfeffffff uint32_t rxPayloadDMADead : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t pad1 : 6; }; } GEN_INT_STATUS; // @ 0x6c union { @@ -85,6 +88,7 @@ typedef union { uint32_t phyRxStart : 1; // @ 23 -- 23 # 0xff7fffff uint32_t rxHeaderDMADead : 1; // @ 24 -- 24 # 0xfeffffff uint32_t rxPayloadDMADead : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t pad1 : 6; }; } GEN_INT_ACK; // @ 0x70 union { @@ -152,6 +156,7 @@ typedef union { uint32_t ac2TxBufTrigger : 1; // @ 26 -- 26 # 0xfbffffff uint32_t ac3TxBufTrigger : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t bcnTxBufTrigger : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad0 : 3; }; } TX_RX_INT_STATUS; // @ 0x78 union { @@ -186,6 +191,7 @@ typedef union { uint32_t ac2TxBufTrigger : 1; // @ 26 -- 26 # 0xfbffffff uint32_t ac3TxBufTrigger : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t bcnTxBufTrigger : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad1 : 3; }; } TX_RX_INT_ACK; // @ 0x7c union { @@ -237,6 +243,7 @@ typedef union { uint32_t absTimers7 : 1; // @ 7 -- 7 # 0xffffff7f uint32_t absTimers8 : 1; // @ 8 -- 8 # 0xfffffeff uint32_t absTimers9 : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 22; }; } TIMERS_INT_EVENT_SET; // @ 0x84 union { @@ -252,6 +259,7 @@ typedef union { uint32_t absTimers7 : 1; // @ 7 -- 7 # 0xffffff7f uint32_t absTimers8 : 1; // @ 8 -- 8 # 0xfffffeff uint32_t absTimers9 : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 22; }; } TIMERS_INT_EVENT_CLEAR; // @ 0x88 union { @@ -267,6 +275,7 @@ typedef union { uint32_t maskabsTimers7 : 1; // @ 7 -- 7 # 0xffffff7f uint32_t maskabsTimers8 : 1; // @ 8 -- 8 # 0xfffffeff uint32_t maskabsTimers9 : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 22; }; } TIMERS_INT_UN_MASK; // @ 0x8c uint8_t pad4[0x14]; @@ -299,6 +308,7 @@ typedef union { uint32_t value; struct { uint32_t ppduMCSIndex : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 25; }; } TIME_ON_AIR_PARAM_2; // @ 0x164 union { @@ -336,6 +346,7 @@ typedef union { uint32_t rxPayloadNewTail : 1; // @ 25 -- 25 # 0xfdffffff uint32_t rxHeaderNewHead : 1; // @ 26 -- 26 # 0xfbffffff uint32_t rxPayloadNewHead : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t pad3 : 4; }; } DMA_CNTRL_SET; // @ 0x180 union { @@ -363,6 +374,7 @@ typedef union { uint32_t rxPayloadNewTail : 1; // @ 25 -- 25 # 0xfdffffff uint32_t rxHeaderNewHead : 1; // @ 26 -- 26 # 0xfbffffff uint32_t rxPayloadNewHead : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t pad3 : 4; }; } DMA_CNTRL_CLEAR; // @ 0x184 union { @@ -381,6 +393,7 @@ typedef union { uint32_t rxHeaderState : 2; // @ 25 -- 24 # 0xfcffffff uint32_t pad5 : 2; uint32_t rxPayloadState : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t pad6 : 2; }; } DMA_STATUS_1; // @ 0x188 union { @@ -416,6 +429,7 @@ typedef union { uint32_t txAC1NewHeadErr : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t txAC2NewHeadErr : 1; // @ 28 -- 28 # 0xefffffff uint32_t txAC3NewHeadErr : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad0 : 2; }; } DMA_STATUS_2; // @ 0x18c union { @@ -429,6 +443,7 @@ typedef union { uint32_t rxPayBusErr : 1; // @ 5 -- 5 # 0xffffffdf uint32_t rxHdrNewHeadErr : 1; // @ 6 -- 6 # 0xffffffbf uint32_t rxPayNewHeadErr : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; }; } DMA_STATUS_3; // @ 0x190 union { @@ -449,6 +464,7 @@ typedef union { uint32_t txAC1HaltAfterTXOP : 1; // @ 12 -- 12 # 0xffffefff uint32_t txAC2HaltAfterTXOP : 1; // @ 13 -- 13 # 0xffffdfff uint32_t txAC3HaltAfterTXOP : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pad0 : 17; }; } DMA_STATUS_4; // @ 0x194 union { @@ -489,6 +505,7 @@ typedef union { uint32_t dmaTBDSize : 6; // @ 17 -- 12 # 0xfffc0fff uint32_t dmaRHDSize : 6; // @ 23 -- 18 # 0xff03ffff uint32_t dmaRBDSize : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad0 : 2; }; } TX_STRUCT_SIZES; // @ 0x1ac uint8_t pad7[0x8]; @@ -514,6 +531,7 @@ typedef union { uint32_t txFIFOThreshold : 8; // @ 7 -- 0 # 0xffffff00 uint32_t pad0 : 8; uint32_t rxFIFOThreshold : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad1 : 8; }; } DMA_THRESHOLD; // @ 0x1c0 uint8_t pad8[0x4c]; @@ -524,6 +542,7 @@ typedef union { uint32_t ac1HasData : 1; // @ 1 -- 1 # 0xfffffffd uint32_t ac2HasData : 1; // @ 2 -- 2 # 0xfffffffb uint32_t ac3HasData : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; }; } EDCA_AC_HAS_DATA_SET; // @ 0x210 union { @@ -533,6 +552,7 @@ typedef union { uint32_t ac1HasData : 1; // @ 1 -- 1 # 0xfffffffd uint32_t ac2HasData : 1; // @ 2 -- 2 # 0xfffffffb uint32_t ac3HasData : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; }; } EDCA_AC_HAS_DATA_CLEAR; // @ 0x214 uint8_t pad9[0x10]; @@ -562,6 +582,7 @@ typedef union { uint32_t value; struct { uint32_t txBWAfterDrop : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 30; }; } TX_BW_DROP_INFO; // @ 0x330 uint8_t pad11[0x30]; @@ -592,6 +613,7 @@ typedef union { uint32_t secU3ac1TxBufTrigger : 1; // @ 21 -- 21 # 0xffdfffff uint32_t secU3ac2TxBufTrigger : 1; // @ 22 -- 22 # 0xffbfffff uint32_t secU3ac3TxBufTrigger : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad0 : 8; }; } SEC_USERS_TX_INT_EVENT_SET; // @ 0x364 union { @@ -621,6 +643,7 @@ typedef union { uint32_t secU3ac1TxBufTrigger : 1; // @ 21 -- 21 # 0xffdfffff uint32_t secU3ac2TxBufTrigger : 1; // @ 22 -- 22 # 0xffbfffff uint32_t secU3ac3TxBufTrigger : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad0 : 8; }; } SEC_USERS_TX_INT_EVENT_CLEAR; // @ 0x368 union { diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index 341242e..1ab9362 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -36,6 +36,7 @@ typedef union { uint32_t CFGSMOOTHFORCE : 1; // @ 18 -- 18 # 0xfffbffff uint32_t SMOOTHEN : 1; // @ 19 -- 19 # 0xfff7ffff uint32_t TDCYCROTVAL80 : 8; // @ 27 -- 20 # 0xf00fffff + uint32_t pad0 : 4; }; } SMOOTHCTRL; // @ 0x818 union { @@ -44,6 +45,7 @@ typedef union { uint32_t WAITHTSTF : 7; // @ 6 -- 0 # 0xffffff80 uint32_t pad0 : 1; uint32_t delaynormalgi : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 18; }; } DCESTIMCTRL; // @ 0x81c union { @@ -63,6 +65,7 @@ typedef union { uint32_t rxmumimoapeplenen : 1; // @ 20 -- 20 # 0xffefffff uint32_t pad5 : 3; uint32_t rxcbwmax : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 6; }; } rxchan; // @ 0x820 union { @@ -80,6 +83,7 @@ typedef union { uint32_t ntxmax : 3; // @ 22 -- 20 # 0xff8fffff uint32_t pad5 : 1; uint32_t txcbwmax : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 6; }; } txchan; // @ 0x824 uint8_t pad2[0x8]; @@ -88,6 +92,7 @@ typedef union { struct { uint32_t smoothsnrthrmid : 8; // @ 7 -- 0 # 0xffffff00 uint32_t smoothsnrthrhigh : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad0 : 16; }; } SMOOTHSNRTHR; // @ 0x830 union { @@ -105,6 +110,7 @@ typedef union { uint32_t value; struct { uint32_t tbe_count_adjust_20 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; }; } TBECTRL0; // @ 0x858 uint8_t pad4[0x4]; @@ -117,6 +123,7 @@ typedef union { uint32_t rcclkforce : 1; // @ 27 -- 27 # 0xf7ffffff uint32_t pad1 : 1; uint32_t mdm_agcmemclkforce : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad2 : 2; }; } r0x874; // @ 0x874 uint8_t pad6[0x10]; @@ -130,6 +137,7 @@ typedef union { uint32_t DSPSWRESET : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad2 : 3; uint32_t AGCSWRESET : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad3 : 19; }; } swreset; // @ 0x888 uint32_t txctrl1; // @ 0x88c @@ -142,6 +150,7 @@ typedef union { struct { uint32_t pad0 : 16; uint32_t precomp : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad1 : 10; }; } r3024; // @ 0x3024 uint8_t pad9[0x8]; diff --git a/src/include/phy/sysctrl.h b/src/include/phy/sysctrl.h index 208b8c3..8f186ab 100644 --- a/src/include/phy/sysctrl.h +++ b/src/include/phy/sysctrl.h @@ -7,6 +7,7 @@ typedef union { uint32_t value; struct { uint32_t diag_sel : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; }; } diag_conf; // @ 0x68 uint8_t pad1[0x8]; @@ -16,6 +17,7 @@ typedef union { uint32_t value; struct { uint32_t time_greater_on_bit12 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; }; } time; // @ 0x84 uint8_t pad3[0x58]; @@ -24,6 +26,7 @@ typedef union { struct { uint32_t pad0 : 8; uint32_t set1 : 9; // @ 16 -- 8 # 0xfffe00ff + uint32_t pad1 : 15; }; } misc_cntl; // @ 0xe0 }; From 5968b959875a645362707faf2185b8bc4ffd2944 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 04:41:26 -0500 Subject: [PATCH 033/148] put irqmacccatimeouten as field name --- script/manualext.py | 2 +- src/include/phy/agc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 6693cb3..d55faab 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -130,7 +130,7 @@ Reg('RWNXAGCCCATIMEOUT', 0x44c0b3bc) # 4000000 Reg('irqmacccatimeouten', 0x44c0b414) -Field('set1', 0xFFFFFEFF) +Field('irqmacccatimeouten', 0xFFFFFEFF) Reg('rwnxmacintstatmasked', 0x44c0b41c) FieldBit('needreset', 8) # guess diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h index c89c8ad..1a2d832 100644 --- a/src/include/phy/agc.h +++ b/src/include/phy/agc.h @@ -185,7 +185,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 8; - uint32_t set1 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t irqmacccatimeouten : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad1 : 23; }; } irqmacccatimeouten; // @ 0x414 From bdac2397107d7597dc65d0ddcb4ea85e3cd16446 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 07:05:00 -0500 Subject: [PATCH 034/148] fix agc --- script/manualext.py | 8 +++++--- src/include/phy/agc.h | 14 +++++++------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index d55faab..b23b600 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -118,7 +118,9 @@ Reg('RWNXAGCCNTL', 0x44c0b390) Field('combpathsel', 0xfffffffc) Field('agcfsmreset', 0xffffefff) # set 1 before agc mem, maybe -Field('rifsdeten', 0xfffffbff) +#Field('rifsdeten', 0xfffffbff) +#Field('riu_ofdmonly_setf', 0xfffffeff) + Reg('riu_rwnxagcaci20marg0', 0x44c0b340) Reg('riu_rwnxagcaci20marg1', 0x44c0b344) Reg('riu_rwnxagcaci20marg2', 0x44c0b348) @@ -256,7 +258,7 @@ def scan_write(code, dat="dat"): extra_regs = [ "rc_paoff_delay", - "riu_agcfsmreset", + "riu_ofdmonly", "riu_txshift4044", "riu_rxiqphaseesten", "riu_rxiqgainesten", @@ -274,7 +276,7 @@ def scan_write(code, dat="dat"): "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffd);", "write_volatile_4(DAT_44c0b110,uVar4 & 0xfffffffe);", ]): - f.name = agc_attr[i][1] + f.name = extra_regs[i] i = i + 1 #open('../src/include/phy/agc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h index 1a2d832..267ce23 100644 --- a/src/include/phy/agc.h +++ b/src/include/phy/agc.h @@ -15,10 +15,10 @@ typedef union { union { uint32_t value; struct { - uint32_t riu_adcpowsupthrdbm : 1; // @ 0 -- 0 # 0xfffffffe - uint32_t riu_adcpowmindbm : 1; // @ 1 -- 1 # 0xfffffffd - uint32_t riu_vpeakadcqdbv : 1; // @ 2 -- 2 # 0xfffffffb - uint32_t riu_fe40gain : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t riu_rxiqgaincompen : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t riu_rxiqphasecompen : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t riu_rxiqgainesten : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t riu_rxiqphaseesten : 1; // @ 3 -- 3 # 0xfffffff7 uint32_t pad0 : 28; }; } r0xb110; // @ 0x110 @@ -120,7 +120,7 @@ typedef union { struct { uint32_t combpathsel : 2; // @ 1 -- 0 # 0xfffffffc uint32_t pad0 : 6; - uint32_t riu_rifsdeten : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t riu_ofdmonly : 1; // @ 8 -- 8 # 0xfffffeff uint32_t pad1 : 1; uint32_t riu_rifsdeten : 1; // @ 10 -- 10 # 0xfffffbff uint32_t pad2 : 1; @@ -204,7 +204,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 12; - uint32_t riu_fe20gain : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t riu_txshift4044 : 2; // @ 13 -- 12 # 0xffffcfff uint32_t pad1 : 18; }; } r0xb500; // @ 0x500 @@ -213,7 +213,7 @@ typedef union { uint32_t value; struct { uint32_t pad0 : 16; - uint32_t riu_htstfgainen : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t rc_paoff_delay : 10; // @ 25 -- 16 # 0xfc00ffff uint32_t pad1 : 6; }; } r0xc020; // @ 0x1020 From 5ab3eca41430d5e3898c6370b9ef78cf8da08789 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 07:19:01 -0500 Subject: [PATCH 035/148] fix var names --- src/bl602_wifi/phy_bl602.c | 202 +++++++++++++++++++------------------ 1 file changed, 102 insertions(+), 100 deletions(-) diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/phy_bl602.c index 7931908..3ed6880 100644 --- a/src/bl602_wifi/phy_bl602.c +++ b/src/bl602_wifi/phy_bl602.c @@ -58,84 +58,86 @@ void phy_get_version(uint32_t *version_1,uint32_t *version_2) { } void agc_config(void) { - AGC->RWNXAGCCNTL.set_0x0_0 = 0x0; - AGC->RWNXAGCCNTL.set_0x0_1 = 0x0; - AGC->r0xb3a4.set_0x0_2 = 0x0; - AGC->r0xb3a4.set_0x0_3 = 0x0; - AGC->r0xb394.set_0xf8_4 = 0xf8; - AGC->r0xb398.set_0x9e_5 = 0x9e; - AGC->r0xb3c4.set_0xce_6 = 0xce; - AGC->r0xb364.set_0x8_7 = 0x8; - AGC->r0xb364.set_0x3c_8 = 0x3c; - AGC->r0xb364.set_0x38_9 = 0x38; - AGC->r0xb364.set_0x39_10 = 0x39; - AGC->r0xb368.set_0x70_11 = 0x70; - AGC->r0xb368.set_0x70_12 = 0x70; - AGC->r0xb36c.set_0x12_13 = 0x12; - AGC->r0xb36c.set_0x5_14 = 0x5; - AGC->r0xb36c.set_0x28_15 = 0x28; - AGC->r0xb36c.set_0x7_16 = 0x7; - AGC->r0xb370.set_0x58_17 = 0x58; - AGC->r0xb3c0.set_0x18_18 = 0x18; - AGC->r0xb380.set_0x3e_19 = 0x3e; - AGC->r0xb380.set_0x37_20 = 0x37; - AGC->r0xb380.set_0x1_21 = 0x1; - AGC->r0xb380.set_0x0_22 = 0x0; - AGC->r0xb380.set_0x1_23 = 0x1; - AGC->r0xb384.set_0x39_24 = 0x39; - AGC->r0xb384.set_0x37_25 = 0x37; - AGC->r0xb384.set_0x14_26 = 0x14; - AGC->r0xb384.set_0x0_27 = 0x0; - AGC->r0xb384.set_0x2_28 = 0x2; - AGC->r0xb388.set_0xf_29 = 0xf; - AGC->r0xb388.set_0x17_30 = 0x17; - AGC->r0xb388.set_0x2a_31 = 0x2a; - AGC->r0xb388.set_0x0_32 = 0x0; - AGC->r0xb388.set_0x5_33 = 0x5; - AGC->r0xb38c.set_0x19_34 = 0x19; - AGC->r0xb38c.set_0x0_35 = 0x0; - AGC->r0xb38c.set_0xe_36 = 0xe; - AGC->r0xb38c.set_0x2_37 = 0x2; - AGC->r0xc830.set_0x3f_38 = 0x3f; - AGC->r0xc830.set_0x1_39 = 0x1; - AGC->r0xc830.set_0x36_40 = 0x36; - AGC->r0xc830.set_0x5_41 = 0x5; - AGC->r0xc814.set_0x0_42 = 0x0; - AGC->r0xc040.set_0xc_43 = 0xc; - AGC->r0xc040.set_0x3_44 = 0x3; - AGC->r0xc044.set_0x8_45 = 0x8; - AGC->r0xc044.set_0x0_46 = 0x0; + AGC->RWNXAGCCNTL.riu_htstfgainen = 0x0; + AGC->RWNXAGCCNTL.riu_rifsdeten = 0x0; + AGC->r0xb3a4.riu_fe20gain = 0x0; + AGC->r0xb3a4.riu_fe40gain = 0x0; + AGC->r0xb394.riu_vpeakadcqdbv = 0xf8; + AGC->r0xb398.riu_adcpowmindbm = 0x9e; + AGC->r0xb3c4.riu_adcpowsupthrdbm = 0xce; + AGC->r0xb364.riu_satdelay50ns = 0x8; + AGC->r0xb364.riu_sathighthrdbv = 0x3c; + AGC->r0xb364.riu_satlowthrdbv = 0x38; + AGC->r0xb364.riu_satthrdbv = 0x39; + AGC->r0xb368.riu_crossdnthrqdbm = 0x70; + AGC->r0xb368.riu_crossupthrqdbm = 0x70; + AGC->RWNXAGCRAMP.riu_rampupgapqdb = 0x12; + AGC->RWNXAGCRAMP.riu_rampupndlindex = 0x5; + AGC->RWNXAGCRAMP.riu_rampdngapqdb = 0x28; + AGC->RWNXAGCRAMP.riu_rampdnndlindex = 0x7; + AGC->r0xb370.riu_adcpowdisthrdbv = 0x58; + AGC->r0xb3c0.riu_idinbdpowgapdnqdbm = 0x18; + AGC->r0xb380.riu_evt0op3 = 0x3e; + AGC->r0xb380.riu_evt0op2 = 0x37; + AGC->r0xb380.riu_evt0op1 = 0x1; + AGC->r0xb380.riu_evt0pathcomb = 0x0; + AGC->r0xb380.riu_evt0opcomb = 0x1; + AGC->r0xb384.riu_evt1op1 = 0x39; + AGC->r0xb384.riu_evt1op2 = 0x37; + AGC->r0xb384.riu_evt1op3 = 0x14; + AGC->r0xb384.riu_evt1pathcomb = 0x0; + AGC->r0xb384.riu_evt1opcomb = 0x2; + AGC->r0xb388.riu_evt2op1 = 0xf; + AGC->r0xb388.riu_evt2op2 = 0x17; + AGC->r0xb388.riu_evt2op3 = 0x2a; + AGC->r0xb388.riu_evt2pathcomb = 0x0; + AGC->r0xb388.riu_evt2opcomb = 0x5; + AGC->r0xb38c.riu_evt3op1 = 0x19; + AGC->r0xb38c.riu_evt3op2 = 0x0; + AGC->r0xb38c.riu_evt3op3 = 0xe; + AGC->r0xb38c.riu_evt3opcomb = 0x2; + AGC->r0xc830.rc2_evt4op1 = 0x3f; + AGC->r0xc830.rc2_evt4op2 = 0x1; + AGC->r0xc830.rc2_evt4op3 = 0x36; + AGC->r0xc830.rc2_evt4opcomb = 0x5; + AGC->r0xc814.rc2_pkdet_mode = 0x0; + AGC->r0xc814.rc2_pkdet_cnt_thr = 0x2; + AGC->r0xc814.rc2_pkdet_cnt_thr = 0x2; + AGC->r0xc040.rc2_rx0_vga_idx_max = 0xc; + AGC->r0xc040.rc2_rx0_vga_idx_min = 0x3; + AGC->r0xc044.rc2_rx0_lna_idx_max = 0x8; + AGC->r0xc044.rc2_rx0_lna_idx_min = 0x0; phy_config_rxgain(0); - AGC->r0xb3a0.set_0x9e_47 = 0x9e; - AGC->r0xb3c0.set_0xa4_48 = 0xa4; - AGC->r0xb3c0.set_0xa3_49 = 0xa3; - AGC->r0xc82c.set_0xb5_50 = 0xb5; - AGC->r0xc82c.set_0x1_51 = 0x1; - AGC->r0xc82c.set_0x1_52 = 0x1; - AGC->r0xc838.set_0x1_53 = 0x1; - AGC->r0xc838.set_0x100_54 = 0x100; - AGC->r0xc83c.set_0x1_55 = 0x1; - AGC->r0xc83c.set_0x17c_56 = 0x17c; - AGC->r0xc840.set_0x1_57 = 0x1; - AGC->r0xc840.set_0x100_58 = 0x100; - AGC->r0xc82c.set_0x40_59 = 0x40; + AGC->r0xb3a0.riu_inbdpowmindbm = 0x9e; + AGC->r0xb3c0.riu_inbdpowsupthrdbm = 0xa4; + AGC->r0xb3c0.riu_inbdpowinfthrdbm = 0xa3; + AGC->r0xc82c.rc2_inbdpow_adj_thr_dbm = 0xb5; + AGC->r0xc82c.rc2_inbdpowsupthr_adj_en = 0x1; + AGC->r0xc82c.rc2_inbdpowinfthr_adj_en = 0x1; + AGC->r0xc838.rc2_reflevofdmthd_en = 0x1; + AGC->r0xc838.rc2_reflevofdmthd = 0x100; + AGC->r0xc83c.rc2_reflevdsssthd_en = 0x1; + AGC->r0xc83c.rc2_reflevdsssthd = 0x17c; + AGC->r0xc840.rc2_reflevdssscontthd_en = 0x1; + AGC->r0xc840.rc2_reflevdssscontthd = 0x100; + AGC->r0xc82c.rc2_inbdpowfastvalid_cnt = 0x40; } void bz_phy_reset(void) { - BZ_PHY->r0x2808.set_0x1_67 = 0x1; - BZ_PHY->r0x2808.set_0x8_68 = 0x8; - BZ_PHY->r0x280c.set_0x1_69 = 0x1; - BZ_PHY->r0x280c.set_0x4_70 = 0x4; - BZ_PHY->r0x280c.set_0x0_71 = 0x0; - BZ_PHY->r0x2854.set_0x20_72 = 0x20; - BZ_PHY->r0x2854.set_0x1e_73 = 0x1e; - BZ_PHY->r0x2854.set_0xa_74 = 0xa; - BZ_PHY->r0x2854.set_0x1e_75 = 0x1e; - BZ_PHY->r0x2810.set_0x0_76 = 0x0; - BZ_PHY->r0x2810.set_0x1_77 = 0x1; - BZ_PHY->r0x2cac.set_0x4_78 = 0x4; + BZ_PHY->r0x2808.bz_phy_tx_rampup_fm_on = 0x1; + BZ_PHY->r0x2808.bz_phy_tx_rampup_time_us = 0x8; + BZ_PHY->r0x280c.bz_phy_tx_rampdn_fm_on = 0x1; + BZ_PHY->r0x280c.bz_phy_tx_rampdn_time_us = 0x4; + BZ_PHY->r0x280c.bz_phy_tx_rampdn_pad0_time_us = 0x0; + BZ_PHY->r0x2854.bz_phy_rx_proc_time_mlsd_us = 0x20; + BZ_PHY->r0x2854.bz_phy_rx_proc_time_direct_us = 0x1e; + BZ_PHY->r0x2854.bz_phy_rx_proc_time_eq_us = 0xa; + BZ_PHY->r0x2854.bz_phy_rx_proc_time_viterbi_us = 0x1e; + BZ_PHY->r0x2810.bz_phy_rx_dfe_notch_en = 0x0; + BZ_PHY->r0x2810.bz_phy_rx_dfe_toc_en = 0x1; + BZ_PHY->r0x2cac.bz_agc_rbb_ind_min = 0x4; return ; } @@ -193,17 +195,17 @@ int phy_freq_to_channel(uint8_t band, uint16_t freq); void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t chantype) { ASSERT_ERR(chantype == PHY_CHNL_BW_20); ASSERT_ERR(band == PHY_BAND_2G4); - AGC->RWNXAGCCNTL.set_0x0_61 = 0; - MDM->rxchan.reset = 1; + AGC->RWNXAGCCNTL.riu_ofdmonly = 0; + MDM->rxchan.rxdsssen = 1; MDM->mdmconf = 0; mdm_reset(); - MDM->TXCTRL0 = 0xb4; - MDM->TXCTRL1 = 0x1c13; - MDM->TXCTRL3 = 0x2d00438; + MDM->txstartdelay = 0xb4; + MDM->txctrl1 = 0x1c13; + MDM->txctrl3 = 0x2d00438; MDM->TBECTRL0.tbe_count_adjust_20 = 0; MDM->DCESTIMCTRL.value = 0xf0f; MDM->DCESTIMCTRL.WAITHTSTF = 7; - MDM->r834.set60h = 0x6; + MDM->r834.tddchtstfmargin = 0x6; MDM->SMOOTHCTRL.value = 0x1880c06; MDM->tbectrl2 = 0x7f03; AGC->riu_rwnxagcaci20marg0 = 0; @@ -256,51 +258,51 @@ void phy_init(phy_cfg_tag *config) { mdm_reset(); MDM->rxchan.value = 0x20d; MDM->rxchan.rxnssmax = phy_get_nss(); - MDM->rxchan.rxndpnstsmax = MDM->version.rxndpnstsmax; - MDM->rxchan.v19 = MDM->version.v19; - MDM->rxchan.vht = phy_vht_supported(); - MDM->rxchan.v30 = MDM->version.mu_mimo_rx; + MDM->rxchan.rxndpnstsmax = MDM->version.nsts; + MDM->rxchan.rxldpcen = MDM->version.ldpcdec; + MDM->rxchan.rxvhten = phy_vht_supported(); + MDM->rxchan.rxmumimoen = MDM->version.mu_mimo_rx; MDM->r3024.precomp = 0x2D; MDM->rxframeviolationmask = 0xffffffff; MDM->txchan.value = 0x20d; MDM->txchan.txnssmax = phy_get_nss(); MDM->txchan.ntxmax = phy_get_ntx(); - MDM->txchan.txcbwmax = MDM->version.txcbwmax; - MDM->txchan.v18 = MDM->version.v18; + MDM->txchan.txcbwmax = MDM->version.chbw; + MDM->txchan.txldpcen = MDM->version.ldpcenc; MDM->txchan.vht = phy_vht_supported(); - MDM->txchan.v31 = MDM->version.mu_mimo_tx; + MDM->txchan.txmumimoen = MDM->version.mu_mimo_tx; - MDM->r834.set1 = 1; + MDM->r834.rxtdctrl1 = 1; MDM->SMOOTHCTRL.CFGSMOOTHFORCE = 0; MDM->SMOOTHSNRTHR.smoothsnrthrhigh = 0x1b; MDM->SMOOTHSNRTHR.smoothsnrthrmid = 0xf; MDM->rxctrl1 = 0x4920492; - MDM->r874.resetto1 = 1; + MDM->r0x874.rcclkforce = 1; - AGC->r0xb500.set_0x2_62 = 0x02; + AGC->r0xb500.riu_txshift4044 = 0x02; if (AGC->r000.iqcomp) { - AGC->r0xb110.set_0x0_63 = 0; - AGC->r0xb110.set_0x0_64 = 0; - AGC->r0xb110.set_0x0_65 = 0; - AGC->r0xb110.set_0x0_66 = 0; + AGC->r0xb110.riu_rxiqphaseesten = 0; + AGC->r0xb110.riu_rxiqgainesten = 0; + AGC->r0xb110.riu_rxiqphasecompen = 0; + AGC->r0xb110.riu_rxiqgaincompen = 0; AGC->riu_iqestiterclr = 0; } AGC->activeant = 1; - AGC->RWNXAGCCNTL.set1 = 1; + AGC->RWNXAGCCNTL.combpathsel = 1; AGC->RWNXAGCCCATIMEOUT = 4000000; - AGC->irqmacccatimeouten.set1 = 1; + AGC->irqmacccatimeouten.irqmacccatimeouten = 1; agc_config(); AGC->RWNXAGCCNTL.agcfsmreset = 1; - MDM->r874.set1beforewriteagcmem = 1; + MDM->r0x874.mdm_agcmemclkforce = 1; for (int i = 0; i < 0x200; i++) AGCRAM->agcram[i] = agcmem[i]; - MDM->r874.set1beforewriteagcmem = 0; + MDM->r0x874.mdm_agcmemclkforce = 0; AGC->RWNXAGCCNTL.agcfsmreset = 0; - AGC->r0xc020.set_0x14_60 = 0x14; + AGC->r0xc020.rc_paoff_delay = 0x14; phy_env[0].cfg.reserved = (config->parameters)[0]; phy_env[0].chnl_center1_freq = 0xff; phy_env[0].chnl_center2_freq = 0xff; @@ -316,7 +318,7 @@ void phy_init(phy_cfg_tag *config) { uint8_t phy_vht_supported(){ if (MDM->version.vht) // TODO: verify this cond return 1; - return ((MDM->version.txcbwmax) >> 1) & 1; + return ((MDM->version.chbw) >> 1) & 1; } uint8_t phy_ldpc_rx_supported(void){ @@ -340,8 +342,8 @@ uint8_t phy_mu_mimo_tx_supported(void) { } void phy_rc_isr(void) { - uint32_t val = AGC->r41c.value; - AGC->r420_copy41c = val; + uint32_t val = AGC->rwnxmacintstatmasked.value; + AGC->rwnxmacintack = val; if (val & 0x100) { mdm_reset(); } From c158eeaf86485d7e89150b4db2b13422a07397da Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 21:34:31 -0500 Subject: [PATCH 036/148] fix regs and add phy_adapt --- script/manualext.py | 10 ++- src/bl602_wifi/assert.h | 6 ++ src/bl602_wifi/hal_desc.h | 121 +++++++++++++++++++++++++ src/bl602_wifi/phy_adapt.c | 175 +++++++++++++++++++++++++++++++++++++ src/bl602_wifi/phy_adapt.h | 92 ++++++++++++++++++- src/bl602_wifi/phy_bl602.c | 36 ++------ src/bl602_wifi/phy_bl602.h | 76 +++++++++++++++- src/bl602_wifi/phy_hal.h | 17 ++++ src/bl602_wifi/utils.h | 3 + src/include/stdint.h | 4 +- 10 files changed, 502 insertions(+), 38 deletions(-) create mode 100644 src/bl602_wifi/assert.h create mode 100644 src/bl602_wifi/hal_desc.h create mode 100644 src/bl602_wifi/phy_adapt.c create mode 100644 src/bl602_wifi/phy_hal.h create mode 100644 src/bl602_wifi/utils.h diff --git a/script/manualext.py b/script/manualext.py index b23b600..6304b8e 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -180,7 +180,7 @@ def scan_write(code, dat="dat"): name_r = f'r{hex(addr&0xffff)}' gid = gid + 1 r = Reg(name_r, addr) - yield r, Field(name_f, mask) + yield r, Field(name_f, mask), value agc_attr = [ @@ -249,12 +249,13 @@ def scan_write(code, dat="dat"): ] i = 0 -for r, f in scan_write(open('../blobs/agc_config.c').readlines()): +for r, f, val in scan_write(open('../blobs/agc_config.c').readlines()): if r.offset == agc_attr[i][0] - 0x44c0b000: f.name = agc_attr[i][1] else: print(f"mismatched {i} {agc_attr[i][1]} {hex(r.offset + 0x44c0b000)} {hex(agc_attr[i][0])}") i = i + 1 + #print(f"AGC->{r.name}.{f.name} = {hex(val)};") extra_regs = [ "rc_paoff_delay", @@ -267,7 +268,7 @@ def scan_write(code, dat="dat"): ] i = 0 -for _, f in scan_write([ +for _, f, _ in scan_write([ "write_volatile_4(DAT_44c0c020,uVar4 & 0xfc00ffff | 0x140000);", "write_volatile_4(DAT_44c0b390,uVar1 & 0xfffffeff);", "write_volatile_4(DAT_44c0b500,uVar4 & 0xffffcfff | 0x2000);", @@ -448,12 +449,13 @@ def getregs(fname, pattern='name'): ] i = 0 -for r, f in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): +for r, f, val in scan_write(open('../blobs/bz_phy.c').readlines(), '0x'): if r.offset == extra_bz_phy[i][0] - 0x40002000: f.name = extra_bz_phy[i][1] else: print(f"mismatched {i} {extra_bz_phy[i][1]} {hex(r.offset + 0x40002000)} {hex(extra_bz_phy[i][0])}") i = i + 1 + # print(f"BZ_PHY->{r.name}.{f.name} = {hex(val)}") if __name__ == '__main__': import sys diff --git a/src/bl602_wifi/assert.h b/src/bl602_wifi/assert.h new file mode 100644 index 0000000..0daa8c9 --- /dev/null +++ b/src/bl602_wifi/assert.h @@ -0,0 +1,6 @@ +#ifndef _ASSERT_H_ +#define _ASSERT_H_ +void assert_err(char * condition, char * file, int line); + +#define ASSERT_ERR(cond) if (!(cond)) assert_err(#cond, __FILE__, __LINE__); +#endif \ No newline at end of file diff --git a/src/bl602_wifi/hal_desc.h b/src/bl602_wifi/hal_desc.h new file mode 100644 index 0000000..6a68565 --- /dev/null +++ b/src/bl602_wifi/hal_desc.h @@ -0,0 +1,121 @@ + +#ifndef _HAL_DESC_H_ +#define _HAL_DESC_H_ +#include +struct tx_policy_tbl { + uint32_t upatterntx; // +0 + uint32_t phycntrlinfo1; // +4 + uint32_t phycntrlinfo2; // +8 + uint32_t maccntrlinfo1; // +12 + uint32_t maccntrlinfo2; // +16 + uint32_t ratecntrlinfo[4]; // +20 + uint32_t powercntrlinfo[4]; // +36 +}; // :669:8 + +struct tx_compressed_policy_tbl { + uint32_t upatterntx; // +0 + uint32_t sec_user_control; // +4 +}; // :689:8 + +struct tx_hd { + uint32_t upatterntx; // +0 + uint32_t nextfrmexseq_ptr; // +4 + uint32_t nextmpdudesc_ptr; // +8 + union { + uint32_t first_pbd_ptr; + uint32_t sec_user1_ptr; + }; // +12 + union { + uint32_t datastartptr; + uint32_t sec_user2_ptr; + }; // +16 + union { + uint32_t dataendptr; + uint32_t sec_user3_ptr; + }; // +20 + uint32_t frmlen; // +24 + uint32_t frmlifetime; // +28 + uint32_t phyctrlinfo; // +32 + uint32_t policyentryaddr; // +36 + uint32_t optlen[3]; // +40 + uint32_t macctrlinfo1; // +52 + uint32_t macctrlinfo2; // +56 + uint32_t statinfo; // +60 + uint32_t mediumtimeused; // +64 +}; // :698:8 + +struct tx_pbd { + uint32_t upatterntx; // +0 + uint32_t next; // +4 + uint32_t datastartptr; // +8 + uint32_t dataendptr; // +12 + uint32_t bufctrlinfo; // +16 +}; // :748:8 + +struct rx_hd { + uint32_t upatternrx; // +0 + uint32_t next; // +4 + uint32_t first_pbd_ptr; // +8 + struct rx_swdesc *swdesc; // +12 + uint32_t datastartptr; // +16 + uint32_t dataendptr; // +20 + uint32_t headerctrlinfo; // +24 + uint16_t frmlen; // +28 + uint16_t ampdu_stat_info; // +30 + uint32_t tsflo; // +32 + uint32_t tsfhi; // +36 + uint32_t recvec1a; // +40 + uint32_t recvec1b; // +44 + uint32_t recvec1c; // +48 + uint32_t recvec1d; // +52 + uint32_t recvec2a; // +56 + uint32_t recvec2b; // +60 + uint32_t statinfo; // +64 +}; // :774:8 + +struct rx_pbd { + uint32_t upattern; // +0 + uint32_t next; // +4 + uint32_t datastartptr; // +8 + uint32_t dataendptr; // +12 + uint16_t bufstatinfo; // +16 + uint16_t reserved; // +18 +}; // :816:8 + +struct rx_dmadesc { + struct rx_hd hd; // +0 + struct phy_channel_info phy_info; // +68 + uint32_t flags; // +76 + uint32_t pattern; // +80 + uint32_t payl_offset; // +84 + uint32_t reserved_pad[2]; // +88 + uint32_t use_in_tcpip; // +96 +}; // :834:8 + +struct rx_payloaddesc { + struct rx_pbd pbd; // +0 + uint32_t pd_status; // +20 + uint32_t *buffer_rx; // +24 + void *pbuf_holder[6]; // +28 +}; // :854:8 + +struct tx_cfm_tag { + uint16_t pn[4]; // +0 + uint16_t sn; // +8 + uint16_t timestamp; // +10 + int8_t credits; // +12 + uint8_t ampdu_size; // +13 + uint8_t pad[2]; // +14 + uint32_t status; // +16 +}; // :865:8 + +struct tx_hw_desc { + struct tx_cfm_tag *cfm_ptr; // +0 + struct tx_hd thd; // +4 +}; // :885:8 + +struct tx_agg_desc { + uint8_t reserved; // +0 +}; // :979:8 + +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_adapt.c b/src/bl602_wifi/phy_adapt.c new file mode 100644 index 0000000..3f5d671 --- /dev/null +++ b/src/bl602_wifi/phy_adapt.c @@ -0,0 +1,175 @@ +#include "phy_adapt.h" +#include "utils.h" +#include "phy_hal.h" +#include "assert.h" + +static pa_state_t pa_env[4]; // :136:19 + +void pa_adapt(uint8_t id) { + static uint32_t count = 0; + count++; + if (id > 3) { + return ; + } + int next_ptr = pa_env[id].input_buffer_ptr; + int ptr = (next_ptr - 1 + 8) % 8; // (next_ptr - 1) & 7 + if (pa_env[id].input_buffer[ptr].new) { + int rssi = pa_env[id].input_buffer[ptr].rssi; + if (pa_env[id].rss_state == 0) { + if (pa_env[id].rss_count < 7) { + pa_env[id].rss_count ++; + } else { + pa_env[id].rss_state = 1; + int sum_rssi = 0; + int min_rssi = 100; + int max_rssi = -100; + for (int i = 1; i < 7; i++) { + int _rssi = (int)pa_env[id].input_buffer[(next_ptr - i) % 8].rssi; + sum_rssi = _rssi; + if (_rssi > max_rssi) { + max_rssi = _rssi; + } + if (_rssi < min_rssi) { + min_rssi = _rssi; + } + } + pa_env[id].rss = (sum_rssi - min_rssi - max_rssi) / 4; + } + } else { + if (pa_env[id].rss_hit_count < 5) { + if (rssi + 100 < 101) { + char rss = pa_env[id].rss; + int diff = rssi - rss; + if (diff + 10 < 21) { + pa_env[id].rss_hit_count = 0; + pa_env[id].rss = (char)(diff >> 2) + rss; + } else { + pa_env[id].rss_hit_count ++; + } + } + } else { + pa_env[id].rss_hit_count = 0; + pa_env[id].rss_state = 0; + pa_env[id].rss_count = 0; + } + } + + if ((count & 0xf) == 0xf) { + float ppm; + if ((rssi - pa_env[id].rss) + 10U < 0x15) { + ppm = pa_env[id].input_buffer[ptr].ppm; + if (ABS(ppm) < 2.0) { + double d_ppm = (double)ppm; + double a = 0; + double d_ce = ((double)pa_env[id].ce); + if (rssi < -0x55) { + d_ppm = d_ce * (double)0.03125; + // 0x3fa00000 00000000 + } else { + d_ppm = d_ce * (double)0.125; + // 0x3fc00000 00000000 + } + d_ppm += d_ce; + ppm = (float) d_ppm; + pa_env[id].ce = ppm; + } + } + ppm = pa_env[id].ce; + if (ABS(ppm) > 5) { + if (ppm > 0) { + int cap = hal_get_capcode(); + if (cap != 0) { + hal_set_capcode(hal_get_capcode() - 1); + } + } + if (ppm < 0) { + int cap = hal_get_capcode(); + if (cap < 0x3f) { + hal_set_capcode(hal_get_capcode() + 1); + } + } + pa_env[id].ce = 0.0; + } + } + } +} + +void pa_init(void) { + for (int i = 0; i < 3; i++) { + pa_env[i].rss_state = 0; + pa_env[i].rss_count = 0; + pa_env[i].rss_state = 0; + pa_env[i].rss_count = 0; + pa_env[i].last_update = 0; + pa_env[i].input_buffer_ptr = 0; + pa_env[i].ce_state = 0; + pa_env[i].ce = 0.0; + pa_env[i].ce_num_up_cmds = 0; + pa_env[i].ce_num_dn_cmds = 0; + for (int j = 0; j < 8; j++) { + pa_env[i].input_buffer[j].lna = 0; + pa_env[i].input_buffer[j].new = 0; + pa_env[i].input_buffer[j].ppm = 0; + pa_env[i].input_buffer[j].rssi = 0; + } + } +} + + +float calc_ppm_dsss(uint8_t rxv_freqoff) { + return ((double)rxv_freqoff) * 0.7; +} + +float calc_ppm_ofdm(uint16_t rxv_freqoff) { + return (((double)(-(int)rxv_freqoff)) * 20.0) / 2440.0; +} + +float calc_ppm(rvec_t * rvec) { + if ((rvec->format_mod) == 0 && (rvec->leg_rate < 4)) { + return calc_ppm_dsss(rvec->freqoff_lo); + } else { + return calc_ppm_ofdm(rvec->freqoff); + } +} + + +void pa_input(uint8_t id, struct rx_hd *rhd) { + if (id < 4) { + int ptr = pa_env[id].input_buffer_ptr; + rvec_t *rvec = &(rhd->recvec1a); + input_t *buffer = &(pa_env[id].input_buffer[ptr]); + pa_env[id].last_update = rhd->tsflo; + buffer->new = 1; + //pa_env[id].input_buffer[id].rssi = *(int8_t *)((int)&rhd->recvec1c + 3); + buffer->rssi = rvec->rssi1; + //pa_env[id].input_buffer[id].lna = (char)((int)(rhd->recvec1d << 20) >> 28); + buffer->lna = rvec->agc_lna; + buffer->ppm = calc_ppm(rvec); + ptr = (ptr + 1) & 7; + pa_env[id].input_buffer_ptr = ptr; + } +} + +int8_t pa_alloc(uint32_t vif_addr) { + for (int i = 0; i < 4; i++) { + if (!pa_env[i].used) { + pa_env[i].used = 1; + pa_env[i].vif_tag = vif_addr; + return i; + } + } + + return -1; +} + +void pa_reset(uint8_t id) { + return ; +} + +void pa_free(uint8_t id) { + if (id < 4) { + pa_env[id].used = 0; + pa_env[id].vif_tag = 0; + } +} + diff --git a/src/bl602_wifi/phy_adapt.h b/src/bl602_wifi/phy_adapt.h index 4de482b..7fbe645 100644 --- a/src/bl602_wifi/phy_adapt.h +++ b/src/bl602_wifi/phy_adapt.h @@ -1,6 +1,94 @@ #ifndef _PHY_ADAPT_H_ #define _PHY_ADAPT_H_ -void pa_adapt(void); +#include +#include "hal_desc.h" + +typedef struct { + int8_t rssi; // +0 + int8_t lna; // +1 + float ppm; // +4 + uint8_t new; // +8 +} input_t; // :53:3 + +typedef struct { + uint8_t used; // +0 + uint32_t vif_tag; // +4 + input_t input_buffer[8]; // +8 + int8_t input_buffer_ptr; // +104 + // input_buffer is something like a ring buffer + // input_buffer[input_buffer_ptr] is the in-coming data buffer + // and input_buffer[input_buffer_ptr -1, -2, -3, ..., -6] + // are available datas + // the most recent one is input_buffer[input_buffer_ptr -1] + // wrapped by math mod + uint32_t last_update; // +108 + int8_t rss; // +112 + int8_t rss_acq; // +113 + int8_t rss_trk; // +114 + int8_t rss_state; // +115 + uint8_t rss_hit_count; // +116 + uint32_t rss_count; // +120 + int8_t ris; // +124 + float ce; // +128 + int8_t ce_in; // +132 + int8_t ce_acq; // +133 + int8_t ce_trk; // +134 + int8_t ce_state; // +135 + int8_t ce_num_up_cmds; // +136 + int8_t ce_num_dn_cmds; // +137 +} pa_state_t; // :83:3 + +typedef struct { + uint32_t leg_length:12; // +0 + uint32_t leg_rate:4; // +0 + uint32_t ht_length:16; // +0 + + uint32_t _ht_length:4; // +4 + uint32_t short_gi:1; // +4 + uint32_t stbc:2; // +4 + uint32_t smoothing:1; // +4 + uint32_t mcs:7; // +4 + uint32_t pre_type:1; // +4 + uint32_t format_mod:3; // +4 + uint32_t ch_bw:2; // +4 + uint32_t n_sts:3; // +4 + uint32_t lsig_valid:1; // +4 + uint32_t sounding:1; // +4 + uint32_t num_extn_ss:2; // +4 + uint32_t aggregation:1; // +4 + uint32_t fec_coding:1; // +4 + uint32_t dyn_bw:1; // +4 + uint32_t doze_not_allowed:1; // +4 + + uint32_t antenna_set:8; // +8 + uint32_t partial_aid:9; // +8 + uint32_t group_id:6; // +8 + uint32_t reserved_1c:1; // +8 + int32_t rssi1:8; // +8 + int32_t rssi2:8; // +12 + int32_t agc_lna:4; // +12 + int32_t agc_rbb1:5; // +12 + int32_t agc_dg:7; // +12 + uint32_t reserved_1d:8; // +12 + uint32_t rcpi:8; // +16 + uint32_t evm1:8; // +16 + uint32_t evm2:8; // +16 + union { + uint32_t freqoff:16; + struct { + uint32_t freqoff_lo:8; // +16 + uint32_t freqoff_hi:8; // +20 + }; + }; + uint32_t reserved2b_1:8; // +20 + uint32_t reserved2b_2:8; // +20 + uint32_t reserved2b_3:8; // +20 +} rvec_t; // :134:3 + +void pa_adapt(uint8_t id); void pa_init(void); -void pa_input(void); +void pa_input(uint8_t id, struct rx_hd *rhd); +int8_t pa_alloc(uint32_t vif_addr); +void pa_reset(uint8_t id); +void pa_free(uint8_t id); #endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/phy_bl602.c index 3ed6880..4d98ce9 100644 --- a/src/bl602_wifi/phy_bl602.c +++ b/src/bl602_wifi/phy_bl602.c @@ -10,14 +10,7 @@ #include "phy_adapt.h" #include "phy_tcal.h" #include "rf.h" - -void assert_err(char * condition, char * file, int line); - -#define ASSERT_ERR(cond) if (!(cond)) assert_err(#cond, __FILE__, __LINE__); - -#define PHY_FORMATMOD_11B 0 -#define PHY_FORMATMOD_11G 1 -#define PHY_FORMATMOD_11N 2 +#include "assert.h" static int8_t rxgain_offset_vs_temperature; // :79:15 static int8_t poweroffset[14]; // :80:15 @@ -168,11 +161,11 @@ void phy_get_rf_gain_idx(int8_t *power,uint8_t *idx) { *idx = (uint8_t)rfc_get_power_level(2, (int)*power * 10); } -void phy_get_rf_gain_idx_vs_mode(uint8_t mode,int8_t *power,uint8_t *idx){ +void phy_get_rf_gain_idx_vs_mode(uint8_t mode,int8_t *power,uint8_t *idx) { *idx = (uint8_t)rfc_get_power_level(mode, (int)*power * 10); } -void phy_get_trpc_idx(uint8_t formatmod,uint8_t mcs,int8_t power,uint8_t *idx) { +void phy_get_trpc_idx(uint8_t formatmod,uint8_t mcs,int8_t power,uint8_t *idx) { // THIS IS ONLY MY GUESS. THE REAL DISASSEMBLY LOOKS VERY WEIRD AND IT MUST BE WRONG ASSERT_ERR(formatmod <= PHY_FORMATMOD_11N); if (formatmod == PHY_FORMATMOD_11G) @@ -190,8 +183,6 @@ void phy_powroffset_set(int8_t *power_offset) { } } -int phy_freq_to_channel(uint8_t band, uint16_t freq); - void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t chantype) { ASSERT_ERR(chantype == PHY_CHNL_BW_20); ASSERT_ERR(band == PHY_BAND_2G4); @@ -222,19 +213,6 @@ void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t cha uint8_t channel = 0; - /* - int iVar3 = 0; - if (band == PHY_BAND_2G4) { - if ((freq - 0x96cU & 0xffff) >= 0x48) { - channel = 0xe; - if (freq != 0x9b4) { - channel = (uint8_t)((freq -0x967) / 5); - } - } - - } - */ - // TODO: are these two functions equivelant??? channel = phy_freq_to_channel(band, freq); rfc_apply_tx_power_offset(channel, poweroffset); trpc_update_vs_channel((int8_t)freq1); @@ -315,17 +293,17 @@ void phy_init(phy_cfg_tag *config) { phy_tcal_start(); } -uint8_t phy_vht_supported(){ +uint8_t phy_vht_supported() { if (MDM->version.vht) // TODO: verify this cond return 1; return ((MDM->version.chbw) >> 1) & 1; } -uint8_t phy_ldpc_rx_supported(void){ +uint8_t phy_ldpc_rx_supported(void) { return MDM->version.ldpcrx; } -uint8_t phy_ldpc_tx_supported(void){ +uint8_t phy_ldpc_tx_supported(void) { return MDM->version.ldpctx; } @@ -353,6 +331,6 @@ void phy_reset(void) { return ; } -void phy_stop(void){ +void phy_stop(void) { return ; } diff --git a/src/bl602_wifi/phy_bl602.h b/src/bl602_wifi/phy_bl602.h index c0758f3..2bf1a40 100644 --- a/src/bl602_wifi/phy_bl602.h +++ b/src/bl602_wifi/phy_bl602.h @@ -21,6 +21,13 @@ enum PHY_CHNL_BW_OTHER, }; +enum +{ + PHY_FORMATMOD_11B, + PHY_FORMATMOD_11G, + PHY_FORMATMOD_11N, +}; + struct phy_channel_info { /// PHY channel information 1 @@ -53,7 +60,6 @@ struct phy_env_tag phy_env[1]; // :75:20 void phy_config_rxgain(int offset); uint8_t phy_get_mac_freq(); void phy_get_channel(struct phy_channel_info *info, uint8_t index); -uint8_t phy_get_mac_freq(void); uint8_t phy_get_nss(void); void phy_get_version(uint32_t *version_1,uint32_t *version_2); void agc_config(void); @@ -62,4 +68,72 @@ void mpif_clk_init(void); uint8_t phy_vht_supported(); uint8_t phy_get_ntx(void); uint8_t phy_get_nss(void); +void phy_stop(void); +void phy_reset(void); +void phy_rc_isr(void); +uint8_t phy_mu_mimo_tx_supported(void); +uint8_t phy_mu_mimo_rx_supported(void); +void phy_mdm_isr(void); +uint8_t phy_ldpc_tx_supported(void); +uint8_t phy_ldpc_rx_supported(void); +void phy_init(phy_cfg_tag *config); +void phy_set_channel(uint8_t band,uint8_t type,uint16_t prim20_freq,uint16_t center1_freq, + uint16_t center2_freq,uint8_t index); +void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t chantype); + +void phy_powroffset_set(int8_t *power_offset); +void phy_get_trpc_idx(uint8_t formatmod,uint8_t mcs,int8_t power,uint8_t *idx); +void phy_get_rf_gain_idx_vs_mode(uint8_t mode,int8_t *power,uint8_t *idx); +void phy_get_rf_gain_idx(int8_t *power,uint8_t *idx); +void phy_get_rf_gain_capab(int8_t *max,int8_t *min); +uint8_t phy_bfmer_supported(void); +uint8_t phy_bfmee_supported(); +void mpif_clk_init(void); +void bz_phy_reset(void); + +// not sure if there functions are belong to phy_bl602 +// but they seem to be inlined in many funcs + +int static phy_freq_to_channel(uint8_t band, uint16_t freq) { + int base = 0; + if (band == 0) { + // 2.4GHz + if (freq == 2484) + return 14; + if (freq - 2407 > 65) + return 0; + base = -2407; + } else { + if (band == 1) { + // 5GHz + if (freq > 5825) + return 0; + base = -5000; + } else return 0; + } + return (((int)freq) + base) / 5; +} + + +uint16_t static phy_channel_to_freq(uint8_t band, int channel) { + int freq = 0; + if (band == 0) { + // 2.4GHz + if (channel > 14) { + return 0xffff; + } + if (channel == 14) { + return 2484; + } + freq = 2407; + } else { + // 5GHz + if (channel > 165) { + return 0xffff; + } + freq = 5000; + } + return channel * 5 + freq; +} + #endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_hal.h b/src/bl602_wifi/phy_hal.h new file mode 100644 index 0000000..71902e5 --- /dev/null +++ b/src/bl602_wifi/phy_hal.h @@ -0,0 +1,17 @@ +#ifndef _PHY_HAL_H_ +#define _PHY_HAL_H_ +#include +struct phy_hal_tag { + int16_t temperature; // +0 + uint8_t capcode; // +2 +}; // :6:8 + +//static struct phy_hal_tag hal_env; // :15:27 + +uint8_t hal_get_capcode(void); // :43:9 +void hal_set_capcode(uint32_t capcode); // :48:6 +void hal_set_capcode_asymm(uint32_t capcode_in, uint32_t capcode_out); // :55:6 +void hal_get_capcode_asymm(uint8_t *capcode_in, uint8_t *capcode_out); // :64:6 +bool hal_get_temperature(int16_t *temperature); // :75:5 +void hal_set_temperature(int16_t temperature); // :83:6 +#endif \ No newline at end of file diff --git a/src/bl602_wifi/utils.h b/src/bl602_wifi/utils.h new file mode 100644 index 0000000..fe930e2 --- /dev/null +++ b/src/bl602_wifi/utils.h @@ -0,0 +1,3 @@ +#ifndef __UTILS_H_ +#define ABS(x) (((x) > 0) ? (x) : (-(x))) +#endif \ No newline at end of file diff --git a/src/include/stdint.h b/src/include/stdint.h index 866d0cb..b71c7c3 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -7,8 +7,8 @@ typedef unsigned int uint32_t; typedef unsigned long long int uint64_t; typedef signed char int8_t; -typedef short intint16_t; +typedef short int16_t; typedef int int32_t; typedef long long int int64_t; - +typedef uint8_t bool; #endif \ No newline at end of file From e7b27cec4458e81148bd134bfd69645a6bcda3a4 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 21:49:47 -0500 Subject: [PATCH 037/148] fix error and warn --- src/bl602_wifi/hal_desc.h | 1 + src/bl602_wifi/phy.h | 8 ++++++++ src/bl602_wifi/phy_adapt.c | 2 +- src/bl602_wifi/phy_bl602.h | 10 +--------- 4 files changed, 11 insertions(+), 10 deletions(-) create mode 100644 src/bl602_wifi/phy.h diff --git a/src/bl602_wifi/hal_desc.h b/src/bl602_wifi/hal_desc.h index 6a68565..849e16b 100644 --- a/src/bl602_wifi/hal_desc.h +++ b/src/bl602_wifi/hal_desc.h @@ -2,6 +2,7 @@ #ifndef _HAL_DESC_H_ #define _HAL_DESC_H_ #include +#include "phy.h" struct tx_policy_tbl { uint32_t upatterntx; // +0 uint32_t phycntrlinfo1; // +4 diff --git a/src/bl602_wifi/phy.h b/src/bl602_wifi/phy.h new file mode 100644 index 0000000..db83a71 --- /dev/null +++ b/src/bl602_wifi/phy.h @@ -0,0 +1,8 @@ +#ifndef _PHY_H_ +#define _PHY_H_ +#include +struct phy_channel_info { + uint32_t info1; // +0 + uint32_t info2; // +4 +}; // :97:8 +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_adapt.c b/src/bl602_wifi/phy_adapt.c index 3f5d671..8235b71 100644 --- a/src/bl602_wifi/phy_adapt.c +++ b/src/bl602_wifi/phy_adapt.c @@ -136,7 +136,7 @@ float calc_ppm(rvec_t * rvec) { void pa_input(uint8_t id, struct rx_hd *rhd) { if (id < 4) { int ptr = pa_env[id].input_buffer_ptr; - rvec_t *rvec = &(rhd->recvec1a); + rvec_t *rvec = (rvec_t *)&(rhd->recvec1a); input_t *buffer = &(pa_env[id].input_buffer[ptr]); pa_env[id].last_update = rhd->tsflo; buffer->new = 1; diff --git a/src/bl602_wifi/phy_bl602.h b/src/bl602_wifi/phy_bl602.h index 2bf1a40..dfd8b48 100644 --- a/src/bl602_wifi/phy_bl602.h +++ b/src/bl602_wifi/phy_bl602.h @@ -1,6 +1,6 @@ #ifndef _PHY_BL602_H_ #include - +#include "phy.h" enum { /// 2.4GHz Band @@ -28,14 +28,6 @@ enum PHY_FORMATMOD_11N, }; -struct phy_channel_info -{ - /// PHY channel information 1 - uint32_t info1; - /// PHY channel information 2 - uint32_t info2; -}; - typedef struct phy_cfg_tag phy_cfg_tag; struct phy_cfg_tag { From 81745e56fde135869c2a96290512c90a7faf43ad Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 22:12:44 -0500 Subject: [PATCH 038/148] add offset fixed svd --- .../Bouffalo/BL602/Peripherals/soc602_reg.svd | 19921 ++++++++++++++++ 1 file changed, 19921 insertions(+) create mode 100644 components/bl602/bl602_std/bl602_std/Device/Bouffalo/BL602/Peripherals/soc602_reg.svd diff --git a/components/bl602/bl602_std/bl602_std/Device/Bouffalo/BL602/Peripherals/soc602_reg.svd b/components/bl602/bl602_std/bl602_std/Device/Bouffalo/BL602/Peripherals/soc602_reg.svd new file mode 100644 index 0000000..a04a85a --- /dev/null +++ b/components/bl602/bl602_std/bl602_std/Device/Bouffalo/BL602/Peripherals/soc602_reg.svd @@ -0,0 +1,19921 @@ + + + bouffalolab + bouffalolab + 602 + WiFi BT + high-performance, 32-bit RV32IMAFC core + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + 602 + little + + + + glb + glb. + 0x40000000 + glb + 32 + read-write + + 0 + 0x1000 + registers + + + + clk_cfg0 + clk_cfg0. + 0x0 + + + glb_id + 28 + 31 + + + chip_rdy + 27 + 27 + + + fclk_sw_state + 24 + 26 + + + reg_bclk_div + 16 + 23 + + + reg_hclk_div + 8 + 15 + + + hbn_root_clk_sel + 6 + 7 + + + reg_pll_sel + 4 + 5 + + + reg_bclk_en + 3 + 3 + + + reg_hclk_en + 2 + 2 + + + reg_fclk_en + 1 + 1 + + + reg_pll_en + 0 + 0 + + + + + clk_cfg1 + clk_cfg1. + 0x4 + + + ble_en + 24 + 24 + + + ble_clk_sel + 16 + 21 + + + wifi_mac_wt_div + 4 + 7 + + + wifi_mac_core_div + 0 + 3 + + + + + clk_cfg2 + clk_cfg2. + 0x8 + + + dma_clk_en + 24 + 31 + + + ir_clk_en + 23 + 23 + + + ir_clk_div + 16 + 21 + + + sf_clk_sel2 + 14 + 15 + + + sf_clk_sel + 12 + 13 + + + sf_clk_en + 11 + 11 + + + sf_clk_div + 8 + 10 + + + hbn_uart_clk_sel + 7 + 7 + + + uart_clk_en + 4 + 4 + + + uart_clk_div + 0 + 2 + + + + + clk_cfg3 + clk_cfg3. + 0xC + + + i2c_clk_en + 24 + 24 + + + i2c_clk_div + 16 + 23 + + + spi_clk_en + 8 + 8 + + + spi_clk_div + 0 + 4 + + + + + swrst_cfg0 + swrst_cfg0. + 0x10 + + + swrst_s30 + 8 + 8 + + + swrst_s20 + 4 + 4 + + + swrst_s01 + 1 + 1 + + + swrst_s00 + 0 + 0 + + + + + swrst_cfg1 + swrst_cfg1. + 0x14 + + + swrst_s1a7 + 23 + 23 + + + swrst_s1a6 + 22 + 22 + + + swrst_s1a5 + 21 + 21 + + + swrst_s1a4 + 20 + 20 + + + swrst_s1a3 + 19 + 19 + + + swrst_s1a2 + 18 + 18 + + + swrst_s1a1 + 17 + 17 + + + swrst_s1a0 + 16 + 16 + + + swrst_s1f + 15 + 15 + + + swrst_s1e + 14 + 14 + + + swrst_s1d + 13 + 13 + + + swrst_s1c + 12 + 12 + + + swrst_s1b + 11 + 11 + + + swrst_s1a + 10 + 10 + + + swrst_s19 + 9 + 9 + + + swrst_s18 + 8 + 8 + + + swrst_s17 + 7 + 7 + + + swrst_s16 + 6 + 6 + + + swrst_s15 + 5 + 5 + + + swrst_s14 + 4 + 4 + + + swrst_s13 + 3 + 3 + + + swrst_s12 + 2 + 2 + + + swrst_s11 + 1 + 1 + + + swrst_s10 + 0 + 0 + + + + + swrst_cfg2 + swrst_cfg2. + 0x18 + + + pka_clk_sel + 24 + 24 + + + reg_ctrl_reset_dummy + 4 + 7 + + + reg_ctrl_sys_reset + 2 + 2 + + + reg_ctrl_cpu_reset + 1 + 1 + + + reg_ctrl_pwron_rst + 0 + 0 + + + + + swrst_cfg3 + swrst_cfg3. + 0x1C + + + + cgen_cfg0 + cgen_cfg0. + 0x20 + + + cgen_m + 0 + 7 + + + + + cgen_cfg1 + cgen_cfg1. + 0x24 + + + cgen_s1a + 16 + 23 + + + cgen_s1 + 0 + 15 + + + + + cgen_cfg2 + cgen_cfg2. + 0x28 + + + cgen_s3 + 4 + 4 + + + cgen_s2 + 0 + 0 + + + + + cgen_cfg3 + cgen_cfg3. + 0x2C + + + + MBIST_CTL + MBIST_CTL. + 0x30 + + + reg_mbist_rst_n + 31 + 31 + + + wifi_mbist_mode + 4 + 4 + + + ocram_mbist_mode + 3 + 3 + + + tag_mbist_mode + 2 + 2 + + + hsram_mbist_mode + 1 + 1 + + + irom_mbist_mode + 0 + 0 + + + + + MBIST_STAT + MBIST_STAT. + 0x34 + + + wifi_mbist_fail + 20 + 20 + + + ocram_mbist_fail + 19 + 19 + + + tag_mbist_fail + 18 + 18 + + + hsram_mbist_fail + 17 + 17 + + + irom_mbist_fail + 16 + 16 + + + wifi_mbist_done + 4 + 4 + + + ocram_mbist_done + 3 + 3 + + + tag_mbist_done + 2 + 2 + + + hsram_mbist_done + 1 + 1 + + + irom_mbist_done + 0 + 0 + + + + + bmx_cfg1 + bmx_cfg1. + 0x50 + + + hbn_apb_cfg + 24 + 31 + + + pds_apb_cfg + 16 + 23 + + + hsel_option + 12 + 15 + + + bmx_gating_dis + 10 + 10 + + + bmx_busy_option_dis + 9 + 9 + + + bmx_err_en + 8 + 8 + + + bmx_arb_mode + 4 + 5 + + + bmx_timeout_en + 0 + 3 + + + + + bmx_cfg2 + bmx_cfg2. + 0x54 + + + bmx_dbg_sel + 28 + 31 + + + bmx_err_tz + 5 + 5 + + + bmx_err_dec + 4 + 4 + + + bmx_err_addr_dis + 0 + 0 + + + + + bmx_err_addr + bmx_err_addr. + 0x58 + + + bmx_err_addr + 0 + 31 + + + + + bmx_dbg_out + bmx_dbg_out. + 0x5C + + + bmx_dbg_out + 0 + 31 + + + + + rsv0 + rsv0. + 0x60 + + + rsvd_31_0 + 0 + 31 + + + + + rsv1 + rsv1. + 0x64 + + + rsvd_31_0 + 0 + 31 + + + + + rsv2 + rsv2. + 0x68 + + + rsvd_31_0 + 0 + 31 + + + + + rsv3 + rsv3. + 0x6C + + + rsvd_31_0 + 0 + 31 + + + + + sram_ret + sram_ret. + 0x70 + + + reg_sram_ret + 0 + 31 + + + + + sram_slp + sram_slp. + 0x74 + + + reg_sram_slp + 0 + 31 + + + + + sram_parm + sram_parm. + 0x78 + + + reg_sram_parm + 0 + 31 + + + + + seam_misc + seam_misc. + 0x7C + + + em_sel + 0 + 3 + + + + + glb_parm + glb_parm. + 0x80 + + + uart_swap_set + 24 + 26 + + + p7_jtag_use_io_2_5 + 23 + 23 + + + p6_sdio_use_io_0_5 + 22 + 22 + + + p5_dac_test_with_jtag + 21 + 21 + + + p4_adc_test_with_jtag + 20 + 20 + + + p3_cci_use_io_2_5 + 19 + 19 + + + p2_dac_test_with_cci + 18 + 18 + + + p1_adc_test_with_cci + 17 + 17 + + + reg_cci_use_sdio_pin + 16 + 16 + + + reg_cci_use_jtag_pin + 15 + 15 + + + reg_spi_0_swap + 13 + 13 + + + reg_spi_0_master_mode + 12 + 12 + + + sel_embedded_sflash + 9 + 9 + + + swap_sflash_io_3_io_0 + 8 + 8 + + + jtag_swap_set + 2 + 7 + + + reg_ext_rst_smt + 1 + 1 + + + reg_bd_en + 0 + 0 + + + + + CPU_CLK_CFG + CPU_CLK_CFG. + 0x90 + + + debug_ndreset_gate + 20 + 20 + + + cpu_rtc_sel + 19 + 19 + + + cpu_rtc_en + 18 + 18 + + + cpu_rtc_div + 0 + 16 + + + + + GPADC_32M_SRC_CTRL + GPADC_32M_SRC_CTRL. + 0xA4 + + + gpadc_32m_div_en + 8 + 8 + + + gpadc_32m_clk_sel + 7 + 7 + + + gpadc_32m_clk_div + 0 + 5 + + + + + DIG32K_WAKEUP_CTRL + DIG32K_WAKEUP_CTRL. + 0xA8 + + + reg_en_platform_wakeup + 31 + 31 + + + dig_clk_src_sel + 28 + 28 + + + dig_512k_comp + 25 + 25 + + + dig_512k_en + 24 + 24 + + + dig_512k_div + 16 + 22 + + + dig_32k_comp + 13 + 13 + + + dig_32k_en + 12 + 12 + + + dig_32k_div + 0 + 10 + + + + + WIFI_BT_COEX_CTRL + WIFI_BT_COEX_CTRL. + 0xAC + + + en_gpio_bt_coex + 12 + 12 + + + coex_bt_bw + 11 + 11 + + + coex_bt_pti + 7 + 10 + + + coex_bt_channel + 0 + 6 + + + + + UART_SIG_SEL_0 + UART_SIG_SEL_0. + 0xC0 + + + uart_sig_7_sel + 28 + 31 + + + uart_sig_6_sel + 24 + 27 + + + uart_sig_5_sel + 20 + 23 + + + uart_sig_4_sel + 16 + 19 + + + uart_sig_3_sel + 12 + 15 + + + uart_sig_2_sel + 8 + 11 + + + uart_sig_1_sel + 4 + 7 + + + uart_sig_0_sel + 0 + 3 + + + + + DBG_SEL_LL + DBG_SEL_LL. + 0xD0 + + + reg_dbg_ll_ctrl + 0 + 31 + + + + + DBG_SEL_LH + DBG_SEL_LH. + 0xD4 + + + reg_dbg_lh_ctrl + 0 + 31 + + + + + DBG_SEL_HL + DBG_SEL_HL. + 0xD8 + + + reg_dbg_hl_ctrl + 0 + 31 + + + + + DBG_SEL_HH + DBG_SEL_HH. + 0xDC + + + reg_dbg_hh_ctrl + 0 + 31 + + + + + debug + debug. + 0xE0 + + + debug_i + 1 + 31 + + + debug_oe + 0 + 0 + + + + + GPIO_CFGCTL0 + GPIO_CFGCTL0. + 0x100 + + + real_gpio_1_func_sel + 28 + 31 + + + reg_gpio_1_func_sel + 24 + 27 + + + reg_gpio_1_pd + 21 + 21 + + + reg_gpio_1_pu + 20 + 20 + + + reg_gpio_1_drv + 18 + 19 + + + reg_gpio_1_smt + 17 + 17 + + + reg_gpio_1_ie + 16 + 16 + + + real_gpio_0_func_sel + 12 + 15 + + + reg_gpio_0_func_sel + 8 + 11 + + + reg_gpio_0_pd + 5 + 5 + + + reg_gpio_0_pu + 4 + 4 + + + reg_gpio_0_drv + 2 + 3 + + + reg_gpio_0_smt + 1 + 1 + + + reg_gpio_0_ie + 0 + 0 + + + + + GPIO_CFGCTL1 + GPIO_CFGCTL1. + 0x104 + + + real_gpio_3_func_sel + 28 + 31 + + + reg_gpio_3_func_sel + 24 + 27 + + + reg_gpio_3_pd + 21 + 21 + + + reg_gpio_3_pu + 20 + 20 + + + reg_gpio_3_drv + 18 + 19 + + + reg_gpio_3_smt + 17 + 17 + + + reg_gpio_3_ie + 16 + 16 + + + real_gpio_2_func_sel + 12 + 15 + + + reg_gpio_2_func_sel + 8 + 11 + + + reg_gpio_2_pd + 5 + 5 + + + reg_gpio_2_pu + 4 + 4 + + + reg_gpio_2_drv + 2 + 3 + + + reg_gpio_2_smt + 1 + 1 + + + reg_gpio_2_ie + 0 + 0 + + + + + GPIO_CFGCTL2 + GPIO_CFGCTL2. + 0x108 + + + real_gpio_5_func_sel + 28 + 31 + + + reg_gpio_5_func_sel + 24 + 27 + + + reg_gpio_5_pd + 21 + 21 + + + reg_gpio_5_pu + 20 + 20 + + + reg_gpio_5_drv + 18 + 19 + + + reg_gpio_5_smt + 17 + 17 + + + reg_gpio_5_ie + 16 + 16 + + + real_gpio_4_func_sel + 12 + 15 + + + reg_gpio_4_func_sel + 8 + 11 + + + reg_gpio_4_pd + 5 + 5 + + + reg_gpio_4_pu + 4 + 4 + + + reg_gpio_4_drv + 2 + 3 + + + reg_gpio_4_smt + 1 + 1 + + + reg_gpio_4_ie + 0 + 0 + + + + + GPIO_CFGCTL3 + GPIO_CFGCTL3. + 0x10C + + + reg_gpio_7_func_sel + 24 + 27 + + + reg_gpio_7_pd + 21 + 21 + + + reg_gpio_7_pu + 20 + 20 + + + reg_gpio_7_drv + 18 + 19 + + + reg_gpio_7_smt + 17 + 17 + + + reg_gpio_7_ie + 16 + 16 + + + reg_gpio_6_func_sel + 8 + 11 + + + reg_gpio_6_pd + 5 + 5 + + + reg_gpio_6_pu + 4 + 4 + + + reg_gpio_6_drv + 2 + 3 + + + reg_gpio_6_smt + 1 + 1 + + + reg_gpio_6_ie + 0 + 0 + + + + + GPIO_CFGCTL4 + GPIO_CFGCTL4. + 0x110 + + + reg_gpio_9_func_sel + 24 + 27 + + + reg_gpio_9_pd + 21 + 21 + + + reg_gpio_9_pu + 20 + 20 + + + reg_gpio_9_drv + 18 + 19 + + + reg_gpio_9_smt + 17 + 17 + + + reg_gpio_9_ie + 16 + 16 + + + reg_gpio_8_func_sel + 8 + 11 + + + reg_gpio_8_pd + 5 + 5 + + + reg_gpio_8_pu + 4 + 4 + + + reg_gpio_8_drv + 2 + 3 + + + reg_gpio_8_smt + 1 + 1 + + + reg_gpio_8_ie + 0 + 0 + + + + + GPIO_CFGCTL5 + GPIO_CFGCTL5. + 0x114 + + + reg_gpio_11_func_sel + 24 + 27 + + + reg_gpio_11_pd + 21 + 21 + + + reg_gpio_11_pu + 20 + 20 + + + reg_gpio_11_drv + 18 + 19 + + + reg_gpio_11_smt + 17 + 17 + + + reg_gpio_11_ie + 16 + 16 + + + reg_gpio_10_func_sel + 8 + 11 + + + reg_gpio_10_pd + 5 + 5 + + + reg_gpio_10_pu + 4 + 4 + + + reg_gpio_10_drv + 2 + 3 + + + reg_gpio_10_smt + 1 + 1 + + + reg_gpio_10_ie + 0 + 0 + + + + + GPIO_CFGCTL6 + GPIO_CFGCTL6. + 0x118 + + + reg_gpio_13_func_sel + 24 + 27 + + + reg_gpio_13_pd + 21 + 21 + + + reg_gpio_13_pu + 20 + 20 + + + reg_gpio_13_drv + 18 + 19 + + + reg_gpio_13_smt + 17 + 17 + + + reg_gpio_13_ie + 16 + 16 + + + reg_gpio_12_func_sel + 8 + 11 + + + reg_gpio_12_pd + 5 + 5 + + + reg_gpio_12_pu + 4 + 4 + + + reg_gpio_12_drv + 2 + 3 + + + reg_gpio_12_smt + 1 + 1 + + + reg_gpio_12_ie + 0 + 0 + + + + + GPIO_CFGCTL7 + GPIO_CFGCTL7. + 0x11C + + + reg_gpio_15_func_sel + 24 + 27 + + + reg_gpio_15_pd + 21 + 21 + + + reg_gpio_15_pu + 20 + 20 + + + reg_gpio_15_drv + 18 + 19 + + + reg_gpio_15_smt + 17 + 17 + + + reg_gpio_15_ie + 16 + 16 + + + reg_gpio_14_func_sel + 8 + 11 + + + reg_gpio_14_pd + 5 + 5 + + + reg_gpio_14_pu + 4 + 4 + + + reg_gpio_14_drv + 2 + 3 + + + reg_gpio_14_smt + 1 + 1 + + + reg_gpio_14_ie + 0 + 0 + + + + + GPIO_CFGCTL8 + GPIO_CFGCTL8. + 0x120 + + + reg_gpio_17_func_sel + 24 + 27 + + + reg_gpio_17_pd + 21 + 21 + + + reg_gpio_17_pu + 20 + 20 + + + reg_gpio_17_drv + 18 + 19 + + + reg_gpio_17_smt + 17 + 17 + + + reg_gpio_17_ie + 16 + 16 + + + reg_gpio_16_func_sel + 8 + 11 + + + reg_gpio_16_pd + 5 + 5 + + + reg_gpio_16_pu + 4 + 4 + + + reg_gpio_16_drv + 2 + 3 + + + reg_gpio_16_smt + 1 + 1 + + + reg_gpio_16_ie + 0 + 0 + + + + + GPIO_CFGCTL9 + GPIO_CFGCTL9. + 0x124 + + + reg_gpio_19_func_sel + 24 + 27 + + + reg_gpio_19_pd + 21 + 21 + + + reg_gpio_19_pu + 20 + 20 + + + reg_gpio_19_drv + 18 + 19 + + + reg_gpio_19_smt + 17 + 17 + + + reg_gpio_19_ie + 16 + 16 + + + reg_gpio_18_func_sel + 8 + 11 + + + reg_gpio_18_pd + 5 + 5 + + + reg_gpio_18_pu + 4 + 4 + + + reg_gpio_18_drv + 2 + 3 + + + reg_gpio_18_smt + 1 + 1 + + + reg_gpio_18_ie + 0 + 0 + + + + + GPIO_CFGCTL10 + GPIO_CFGCTL10. + 0x128 + + + reg_gpio_21_func_sel + 24 + 27 + + + reg_gpio_21_pd + 21 + 21 + + + reg_gpio_21_pu + 20 + 20 + + + reg_gpio_21_drv + 18 + 19 + + + reg_gpio_21_smt + 17 + 17 + + + reg_gpio_21_ie + 16 + 16 + + + reg_gpio_20_func_sel + 8 + 11 + + + reg_gpio_20_pd + 5 + 5 + + + reg_gpio_20_pu + 4 + 4 + + + reg_gpio_20_drv + 2 + 3 + + + reg_gpio_20_smt + 1 + 1 + + + reg_gpio_20_ie + 0 + 0 + + + + + GPIO_CFGCTL11 + GPIO_CFGCTL11. + 0x12C + + + reg_gpio_23_pd + 21 + 21 + + + reg_gpio_23_pu + 20 + 20 + + + reg_gpio_23_drv + 18 + 19 + + + reg_gpio_23_smt + 17 + 17 + + + reg_gpio_23_ie + 16 + 16 + + + reg_gpio_22_func_sel + 8 + 11 + + + reg_gpio_22_pd + 5 + 5 + + + reg_gpio_22_pu + 4 + 4 + + + reg_gpio_22_drv + 2 + 3 + + + reg_gpio_22_smt + 1 + 1 + + + reg_gpio_22_ie + 0 + 0 + + + + + GPIO_CFGCTL12 + GPIO_CFGCTL12. + 0x130 + + + reg_gpio_25_pd + 21 + 21 + + + reg_gpio_25_pu + 20 + 20 + + + reg_gpio_25_drv + 18 + 19 + + + reg_gpio_25_smt + 17 + 17 + + + reg_gpio_25_ie + 16 + 16 + + + reg_gpio_24_pd + 5 + 5 + + + reg_gpio_24_pu + 4 + 4 + + + reg_gpio_24_drv + 2 + 3 + + + reg_gpio_24_smt + 1 + 1 + + + reg_gpio_24_ie + 0 + 0 + + + + + GPIO_CFGCTL13 + GPIO_CFGCTL13. + 0x134 + + + reg_gpio_27_pd + 21 + 21 + + + reg_gpio_27_pu + 20 + 20 + + + reg_gpio_27_drv + 18 + 19 + + + reg_gpio_27_smt + 17 + 17 + + + reg_gpio_27_ie + 16 + 16 + + + reg_gpio_26_pd + 5 + 5 + + + reg_gpio_26_pu + 4 + 4 + + + reg_gpio_26_drv + 2 + 3 + + + reg_gpio_26_smt + 1 + 1 + + + reg_gpio_26_ie + 0 + 0 + + + + + GPIO_CFGCTL14 + GPIO_CFGCTL14. + 0x138 + + + reg_gpio_28_pd + 5 + 5 + + + reg_gpio_28_pu + 4 + 4 + + + reg_gpio_28_drv + 2 + 3 + + + reg_gpio_28_smt + 1 + 1 + + + reg_gpio_28_ie + 0 + 0 + + + + + GPIO_CFGCTL30 + GPIO_CFGCTL30. + 0x180 + + + reg_gpio_22_i + 22 + 22 + + + reg_gpio_21_i + 21 + 21 + + + reg_gpio_20_i + 20 + 20 + + + reg_gpio_19_i + 19 + 19 + + + reg_gpio_18_i + 18 + 18 + + + reg_gpio_17_i + 17 + 17 + + + reg_gpio_16_i + 16 + 16 + + + reg_gpio_15_i + 15 + 15 + + + reg_gpio_14_i + 14 + 14 + + + reg_gpio_13_i + 13 + 13 + + + reg_gpio_12_i + 12 + 12 + + + reg_gpio_11_i + 11 + 11 + + + reg_gpio_10_i + 10 + 10 + + + reg_gpio_9_i + 9 + 9 + + + reg_gpio_8_i + 8 + 8 + + + reg_gpio_7_i + 7 + 7 + + + reg_gpio_6_i + 6 + 6 + + + reg_gpio_5_i + 5 + 5 + + + reg_gpio_4_i + 4 + 4 + + + reg_gpio_3_i + 3 + 3 + + + reg_gpio_2_i + 2 + 2 + + + reg_gpio_1_i + 1 + 1 + + + reg_gpio_0_i + 0 + 0 + + + + + GPIO_CFGCTL31 + GPIO_CFGCTL31. + 0x184 + + + + GPIO_CFGCTL32 + GPIO_CFGCTL32. + 0x188 + + + reg_gpio_22_o + 22 + 22 + + + reg_gpio_21_o + 21 + 21 + + + reg_gpio_20_o + 20 + 20 + + + reg_gpio_19_o + 19 + 19 + + + reg_gpio_18_o + 18 + 18 + + + reg_gpio_17_o + 17 + 17 + + + reg_gpio_16_o + 16 + 16 + + + reg_gpio_15_o + 15 + 15 + + + reg_gpio_14_o + 14 + 14 + + + reg_gpio_13_o + 13 + 13 + + + reg_gpio_12_o + 12 + 12 + + + reg_gpio_11_o + 11 + 11 + + + reg_gpio_10_o + 10 + 10 + + + reg_gpio_9_o + 9 + 9 + + + reg_gpio_8_o + 8 + 8 + + + reg_gpio_7_o + 7 + 7 + + + reg_gpio_6_o + 6 + 6 + + + reg_gpio_5_o + 5 + 5 + + + reg_gpio_4_o + 4 + 4 + + + reg_gpio_3_o + 3 + 3 + + + reg_gpio_2_o + 2 + 2 + + + reg_gpio_1_o + 1 + 1 + + + reg_gpio_0_o + 0 + 0 + + + + + GPIO_CFGCTL33 + GPIO_CFGCTL33. + 0x18C + + + + GPIO_CFGCTL34 + GPIO_CFGCTL34. + 0x190 + + + reg_gpio_22_oe + 22 + 22 + + + reg_gpio_21_oe + 21 + 21 + + + reg_gpio_20_oe + 20 + 20 + + + reg_gpio_19_oe + 19 + 19 + + + reg_gpio_18_oe + 18 + 18 + + + reg_gpio_17_oe + 17 + 17 + + + reg_gpio_16_oe + 16 + 16 + + + reg_gpio_15_oe + 15 + 15 + + + reg_gpio_14_oe + 14 + 14 + + + reg_gpio_13_oe + 13 + 13 + + + reg_gpio_12_oe + 12 + 12 + + + reg_gpio_11_oe + 11 + 11 + + + reg_gpio_10_oe + 10 + 10 + + + reg_gpio_9_oe + 9 + 9 + + + reg_gpio_8_oe + 8 + 8 + + + reg_gpio_7_oe + 7 + 7 + + + reg_gpio_6_oe + 6 + 6 + + + reg_gpio_5_oe + 5 + 5 + + + reg_gpio_4_oe + 4 + 4 + + + reg_gpio_3_oe + 3 + 3 + + + reg_gpio_2_oe + 2 + 2 + + + reg_gpio_1_oe + 1 + 1 + + + reg_gpio_0_oe + 0 + 0 + + + + + GPIO_CFGCTL35 + GPIO_CFGCTL35. + 0x194 + + + + GPIO_INT_MASK1 + GPIO_INT_MASK1. + 0x1A0 + + + reg_gpio_int_mask1 + 0 + 31 + + + + + GPIO_INT_STAT1 + GPIO_INT_STAT1. + 0x1A8 + + + gpio_int_stat1 + 0 + 31 + + + + + GPIO_INT_CLR1 + GPIO_INT_CLR1. + 0x1B0 + + + reg_gpio_int_clr1 + 0 + 31 + + + + + GPIO_INT_MODE_SET1 + GPIO_INT_MODE_SET1. + 0x1C0 + + + reg_gpio_int_mode_set1 + 0 + 31 + + + + + GPIO_INT_MODE_SET2 + GPIO_INT_MODE_SET2. + 0x1C4 + + + reg_gpio_int_mode_set2 + 0 + 31 + + + + + GPIO_INT_MODE_SET3 + GPIO_INT_MODE_SET3. + 0x1C8 + + + reg_gpio_int_mode_set3 + 0 + 31 + + + + + led_driver + led_driver. + 0x224 + + + pu_leddrv + 31 + 31 + + + ir_rx_gpio_sel + 8 + 9 + + + leddrv_ibias + 4 + 7 + + + led_din_polarity_sel + 2 + 2 + + + led_din_sel + 1 + 1 + + + led_din_reg + 0 + 0 + + + + + gpdac_ctrl + gpdac_ctrl. + 0x308 + + + gpdac_reserved + 24 + 31 + + + gpdac_test_sel + 9 + 11 + + + gpdac_ref_sel + 8 + 8 + + + gpdac_test_en + 7 + 7 + + + gpdacb_rstn_ana + 1 + 1 + + + gpdaca_rstn_ana + 0 + 0 + + + + + gpdac_actrl + gpdac_actrl. + 0x30C + + + gpdac_a_outmux + 20 + 22 + + + gpdac_a_rng + 18 + 19 + + + gpdac_ioa_en + 1 + 1 + + + gpdac_a_en + 0 + 0 + + + + + gpdac_bctrl + gpdac_bctrl. + 0x310 + + + gpdac_b_outmux + 20 + 22 + + + gpdac_b_rng + 18 + 19 + + + gpdac_iob_en + 1 + 1 + + + gpdac_b_en + 0 + 0 + + + + + gpdac_data + gpdac_data. + 0x314 + + + gpdac_a_data + 16 + 25 + + + gpdac_b_data + 0 + 9 + + + + + tzc_glb_ctrl_0 + tzc_glb_ctrl_0. + 0xF00 + + + tzc_glb_clk_lock + 31 + 31 + + + tzc_glb_mbist_lock + 30 + 30 + + + tzc_glb_dbg_lock + 29 + 29 + + + tzc_glb_bmx_lock + 28 + 28 + + + tzc_glb_l2c_lock + 27 + 27 + + + tzc_glb_sram_lock + 26 + 26 + + + tzc_glb_misc_lock + 25 + 25 + + + tzc_glb_ctrl_ungated_ap_lock + 15 + 15 + + + tzc_glb_ctrl_sys_reset_lock + 14 + 14 + + + tzc_glb_ctrl_cpu_reset_lock + 13 + 13 + + + tzc_glb_ctrl_pwron_rst_lock + 12 + 12 + + + tzc_glb_swrst_s30_lock + 8 + 8 + + + tzc_glb_swrst_s01_lock + 1 + 1 + + + tzc_glb_swrst_s00_lock + 0 + 0 + + + + + tzc_glb_ctrl_1 + tzc_glb_ctrl_1. + 0xF04 + + + tzc_glb_swrst_s1f_lock + 31 + 31 + + + tzc_glb_swrst_s1e_lock + 30 + 30 + + + tzc_glb_swrst_s1d_lock + 29 + 29 + + + tzc_glb_swrst_s1c_lock + 28 + 28 + + + tzc_glb_swrst_s1b_lock + 27 + 27 + + + tzc_glb_swrst_s1a_lock + 26 + 26 + + + tzc_glb_swrst_s19_lock + 25 + 25 + + + tzc_glb_swrst_s18_lock + 24 + 24 + + + tzc_glb_swrst_s17_lock + 23 + 23 + + + tzc_glb_swrst_s16_lock + 22 + 22 + + + tzc_glb_swrst_s15_lock + 21 + 21 + + + tzc_glb_swrst_s14_lock + 20 + 20 + + + tzc_glb_swrst_s13_lock + 19 + 19 + + + tzc_glb_swrst_s12_lock + 18 + 18 + + + tzc_glb_swrst_s11_lock + 17 + 17 + + + tzc_glb_swrst_s10_lock + 16 + 16 + + + tzc_glb_swrst_s2f_lock + 15 + 15 + + + tzc_glb_swrst_s2e_lock + 14 + 14 + + + tzc_glb_swrst_s2d_lock + 13 + 13 + + + tzc_glb_swrst_s2c_lock + 12 + 12 + + + tzc_glb_swrst_s2b_lock + 11 + 11 + + + tzc_glb_swrst_s2a_lock + 10 + 10 + + + tzc_glb_swrst_s29_lock + 9 + 9 + + + tzc_glb_swrst_s28_lock + 8 + 8 + + + tzc_glb_swrst_s27_lock + 7 + 7 + + + tzc_glb_swrst_s26_lock + 6 + 6 + + + tzc_glb_swrst_s25_lock + 5 + 5 + + + tzc_glb_swrst_s24_lock + 4 + 4 + + + tzc_glb_swrst_s23_lock + 3 + 3 + + + tzc_glb_swrst_s22_lock + 2 + 2 + + + tzc_glb_swrst_s21_lock + 1 + 1 + + + tzc_glb_swrst_s20_lock + 0 + 0 + + + + + tzc_glb_ctrl_2 + tzc_glb_ctrl_2. + 0xF08 + + + tzc_glb_gpio_28_lock + 28 + 28 + + + tzc_glb_gpio_27_lock + 27 + 27 + + + tzc_glb_gpio_26_lock + 26 + 26 + + + tzc_glb_gpio_25_lock + 25 + 25 + + + tzc_glb_gpio_24_lock + 24 + 24 + + + tzc_glb_gpio_23_lock + 23 + 23 + + + tzc_glb_gpio_22_lock + 22 + 22 + + + tzc_glb_gpio_21_lock + 21 + 21 + + + tzc_glb_gpio_20_lock + 20 + 20 + + + tzc_glb_gpio_19_lock + 19 + 19 + + + tzc_glb_gpio_18_lock + 18 + 18 + + + tzc_glb_gpio_17_lock + 17 + 17 + + + tzc_glb_gpio_16_lock + 16 + 16 + + + tzc_glb_gpio_15_lock + 15 + 15 + + + tzc_glb_gpio_14_lock + 14 + 14 + + + tzc_glb_gpio_13_lock + 13 + 13 + + + tzc_glb_gpio_12_lock + 12 + 12 + + + tzc_glb_gpio_11_lock + 11 + 11 + + + tzc_glb_gpio_10_lock + 10 + 10 + + + tzc_glb_gpio_9_lock + 9 + 9 + + + tzc_glb_gpio_8_lock + 8 + 8 + + + tzc_glb_gpio_7_lock + 7 + 7 + + + tzc_glb_gpio_6_lock + 6 + 6 + + + tzc_glb_gpio_5_lock + 5 + 5 + + + tzc_glb_gpio_4_lock + 4 + 4 + + + tzc_glb_gpio_3_lock + 3 + 3 + + + tzc_glb_gpio_2_lock + 2 + 2 + + + tzc_glb_gpio_1_lock + 1 + 1 + + + tzc_glb_gpio_0_lock + 0 + 0 + + + + + tzc_glb_ctrl_3 + tzc_glb_ctrl_3. + 0xF0C + + + + + + rf + rf. + 0x40001000 + rf + 32 + read-write + + 0 + 0x1000 + registers + + + + rf_rev + Silicon revision + 0x0 + + + hw_rev + 16 + 23 + + + fw_rev + 8 + 15 + + + rf_id + 0 + 7 + + + + + rf_fsm_ctrl_hw + Digital Control + 0x4 + + + rf_rc_state_value + 28 + 30 + + + rf_fsm_st_int_set + 24 + 24 + + + rf_fsm_st_int_clr + 20 + 20 + + + rf_fsm_st_int + 16 + 16 + + + rf_fsm_st_int_sel + 12 + 14 + + + rf_rc_state_dbg_en + 11 + 11 + + + rf_rc_state_dbg + 8 + 10 + + + rf_fsm_state + 4 + 6 + + + rf_fsm_t2r_cal_mode + 2 + 3 + + + rf_fsm_ctrl_en + 1 + 1 + + + + + rf_fsm_ctrl_sw + rfsm status reg + 0x8 + + + lo_unlocked + 20 + 20 + + + inc_cal_timeout + 16 + 16 + + + full_cal_en + 12 + 12 + + + rf_fsm_sw_st_vld + 8 + 8 + + + rf_fsm_sw_st + 0 + 4 + + + + + rfctrl_hw_en + Control logic switch + 0xC + + + adda_ctrl_hw + 12 + 12 + + + rbb_pkdet_out_rstn_ctrl_hw + 11 + 11 + + + rbb_pkdet_en_ctrl_hw + 10 + 10 + + + sdm_ctrl_hw + 9 + 9 + + + inc_fcal_ctrl_en_hw + 8 + 8 + + + inc_acal_ctrl_en_hw + 7 + 7 + + + lo_ctrl_hw + 6 + 6 + + + trxcal_ctrl_hw + 5 + 5 + + + rbb_bw_ctrl_hw + 4 + 4 + + + lna_ctrl_hw + 3 + 3 + + + tx_gain_ctrl_hw + 2 + 2 + + + rx_gain_ctrl_hw + 1 + 1 + + + pu_ctrl_hw + 0 + 0 + + + + + temp_comp + temp_comp. + 0x10 + + + temp_comp_en + 16 + 16 + + + const_fcal + 8 + 15 + + + const_acal + 0 + 7 + + + + + rfcal_status + rfcal_status. + 0x14 + + + dpd_status + 30 + 31 + + + tenscal_status + 28 + 29 + + + pwdet_cal_status + 26 + 27 + + + riqcal_status_resv + 24 + 25 + + + tiqcal_status_resv + 22 + 23 + + + lo_leakcal_status + 20 + 21 + + + rccal_status + 18 + 19 + + + tos_status + 16 + 17 + + + ros_status + 14 + 15 + + + clkpll_cal_status + 12 + 13 + + + inc_acal_status + 10 + 11 + + + inc_fcal_status + 8 + 9 + + + acal_status + 6 + 7 + + + fcal_status + 4 + 5 + + + adc_oscal_status + 2 + 3 + + + rcal_status + 0 + 1 + + + + + rfcal_status2 + rfcal_status2. + 0x18 + + + dl_rfcal_table_status + 0 + 1 + + + + + rfcal_ctrlen + Calibration mode register + 0x1C + + + dpd_en + 17 + 17 + + + tsencal_en + 16 + 16 + + + pwdet_cal_en + 15 + 15 + + + riqcal_en + 14 + 14 + + + tiqcal_en + 13 + 13 + + + lo_leakcal_en + 12 + 12 + + + rccal_en + 11 + 11 + + + toscal_en + 10 + 10 + + + roscal_en + 9 + 9 + + + clkpll_cal_en + 8 + 8 + + + roscal_inc_en + 7 + 7 + + + acal_inc_en + 6 + 6 + + + fcal_inc_en + 5 + 5 + + + acal_en + 4 + 4 + + + fcal_en + 3 + 3 + + + dl_rfcal_table_en + 2 + 2 + + + adc_oscal_en + 1 + 1 + + + rcal_en_resv + 0 + 0 + + + + + rfcal_stateen + rf calibration state enabl in full cal list + 0x20 + + + rfcal_level + 30 + 31 + + + dpd_sten + 16 + 16 + + + tsencal_sten + 15 + 15 + + + pwdet_cal_sten + 14 + 14 + + + riqcal_sten + 13 + 13 + + + tiqcal_sten + 12 + 12 + + + lo_leakcal_sten + 11 + 11 + + + rccal_sten + 10 + 10 + + + toscal_sten_resv + 9 + 9 + + + roscal_sten + 8 + 8 + + + clkpll_cal_sten + 7 + 7 + + + inc_acal_sten + 6 + 6 + + + inc_fcal_sten + 5 + 5 + + + acal_sten + 4 + 4 + + + fcal_sten + 3 + 3 + + + dl_rfcal_table_sten + 2 + 2 + + + adc_oscal_sten + 1 + 1 + + + rcal_sten_resv + 0 + 0 + + + + + saradc_resv + SARADC Control Registers + 0x24 + + + + rf_base_ctrl1 + ZRF Control register 0 + 0x28 + + + mbg_trim + 27 + 28 + + + pud_pa_dly + 14 + 15 + + + pud_iref_dly + 12 + 13 + + + pud_vco_dly + 10 + 11 + + + ppu_lead + 8 + 9 + + + lo_sdm_rst_dly + 2 + 3 + + + aupll_sdm_rst_dly + 0 + 1 + + + + + rf_base_ctrl2 + ZRF Control register 0 + 0x2C + + + + pucr1 + pucr1. + 0x30 + + + pu_tosdac + 31 + 31 + + + pu_pwrmx + 30 + 30 + + + pu_rosdac + 29 + 29 + + + pu_pkdet + 28 + 28 + + + trsw_en + 26 + 26 + + + pu_txbuf + 25 + 25 + + + pu_rxbuf + 24 + 24 + + + pu_osmx + 23 + 23 + + + pu_pfd + 22 + 22 + + + pu_fbdv + 21 + 21 + + + pu_vco + 20 + 20 + + + pu_dac + 19 + 19 + + + pu_tbb + 18 + 18 + + + pu_tmx + 17 + 17 + + + pu_pa + 16 + 16 + + + pu_op_atest + 15 + 15 + + + pu_adc + 14 + 14 + + + adc_clk_en + 13 + 13 + + + pu_adda_ldo + 12 + 12 + + + pu_rbb + 11 + 11 + + + pu_rmx + 10 + 10 + + + pu_rmxgm + 9 + 9 + + + pu_lna + 8 + 8 + + + pu_sfreg + 0 + 0 + + + + + pucr1_hw + read only from hardware logic + 0x34 + + + pu_tosdac_hw + 31 + 31 + + + pu_rosdac_hw + 29 + 29 + + + pu_pkdet_hw + 28 + 28 + + + trsw_en_hw + 26 + 26 + + + pu_txbuf_hw + 25 + 25 + + + pu_rxbuf_hw + 24 + 24 + + + pu_osmx_hw + 23 + 23 + + + pu_pfd_hw + 22 + 22 + + + pu_fbdv_hw + 21 + 21 + + + pu_vco_hw + 20 + 20 + + + pu_dac_hw + 19 + 19 + + + pu_tbb_hw + 18 + 18 + + + pu_tmx_hw + 17 + 17 + + + pu_pa_hw + 16 + 16 + + + pu_adc_hw + 14 + 14 + + + adc_clk_en_hw + 13 + 13 + + + pu_adda_ldo_hw + 12 + 12 + + + pu_rbb_hw + 11 + 11 + + + pu_rmx_hw + 10 + 10 + + + pu_rmxgm_hw + 9 + 9 + + + pu_lna_hw + 8 + 8 + + + pu_sfreg_hw + 0 + 0 + + + + + pucr2 + pucr2. + 0x38 + + + + pucr2_hw + pucr2_hw. + 0x3C + + + + ppu_ctrl_hw + ppu_ctrl_hw. + 0x40 + + + ppu_txbuf_hw + 25 + 25 + + + ppu_rxbuf_hw + 24 + 24 + + + ppu_osmx_hw + 23 + 23 + + + ppu_pfd_hw + 22 + 22 + + + ppu_fbdv_hw + 21 + 21 + + + ppu_vco_hw + 20 + 20 + + + ppu_rbb_hw + 11 + 11 + + + ppu_rmxgm_hw + 9 + 9 + + + ppu_lna_hw + 8 + 8 + + + + + pud_ctrl_hw + pud_ctrl_hw. + 0x44 + + + pud_vco_hw + 20 + 20 + + + + + trx_gain1 + gain control1 + 0x48 + + + gc_tbb_boost + 28 + 29 + + + gc_tbb + 20 + 24 + + + gc_tmx + 16 + 18 + + + gc_rbb2 + 12 + 14 + + + gc_rbb1 + 8 + 9 + + + gc_rmxgm + 4 + 5 + + + gc_lna + 0 + 2 + + + + + trx_gain_hw + trx gain hardware readback + 0x4C + + + gc_tbb_boost_hw + 28 + 29 + + + gc_tbb_hw + 20 + 24 + + + gc_tmx_hw + 16 + 18 + + + gc_rbb2_hw + 12 + 14 + + + gc_rbb1_hw + 8 + 9 + + + gc_rmxgm_hw + 4 + 5 + + + gc_lna_hw + 0 + 2 + + + + + ten_dc + dc test register + 0x50 + + + ten_lodist + 27 + 27 + + + ten_lf + 26 + 26 + + + ten_pfdcp + 25 + 25 + + + ten_vco + 24 + 24 + + + ten_dac_q + 22 + 22 + + + ten_dac_i + 21 + 21 + + + ten_adc + 20 + 20 + + + ten_tbb + 19 + 19 + + + ten_atest + 18 + 18 + + + ten_bq + 17 + 17 + + + ten_tia + 16 + 16 + + + ten_tmx + 15 + 15 + + + ten_pa + 14 + 14 + + + ten_rrf_1 + 13 + 13 + + + ten_rrf_0 + 12 + 12 + + + ten_clkpll_sfreg + 9 + 9 + + + ten_clkpll + 8 + 8 + + + dc_tp_clkpll_en + 4 + 4 + + + dc_tp_en + 3 + 3 + + + tmux + 0 + 2 + + + + + ten_dig + digital test register + 0x54 + + + rf_dtest_en + 23 + 23 + + + dtest_pull_down + 9 + 9 + + + dten_lo_fref + 8 + 8 + + + dten_lo_fsdm + 6 + 6 + + + dten_clkpll_fin + 5 + 5 + + + dten_clkpll_fref + 4 + 4 + + + dten_clkpll_fsdm + 3 + 3 + + + dten_clkpll_clk32m + 2 + 2 + + + dten_clkpll_clk96m + 1 + 1 + + + dten_clkpll_postdiv_clk + 0 + 0 + + + + + ten_ac + ac test register + 0x58 + + + atest_in_en_i + 23 + 23 + + + atest_in_en_q + 22 + 22 + + + atest_out_en_i + 21 + 21 + + + atest_out_en_q + 20 + 20 + + + atest_gain_r5 + 16 + 18 + + + atest_gain_r6 + 14 + 15 + + + atest_gain_r7 + 12 + 13 + + + atest_gain_r8 + 10 + 11 + + + atest_gain_r9 + 8 + 9 + + + atest_in_en + 6 + 6 + + + atest_in_trx_sw + 5 + 5 + + + atest_dac_en + 4 + 4 + + + atest_op_cc + 0 + 3 + + + + + pmip_mv2aon + pmip_mv2aon. + 0x5C + + + + cip + RX normal bias mode registers + 0x60 + + + vg13_sel + 2 + 3 + + + vg11_sel + 0 + 1 + + + + + pa1 + pa1. + 0x64 + + + pa_att_gc + 28 + 31 + + + pa_pwrmx_bm + 24 + 26 + + + pa_pwrmx_dac_pn_switch + 22 + 22 + + + pa_pwrmx_osdac + 18 + 21 + + + pa_lz_bias_en + 17 + 17 + + + pa_ib_fix + 16 + 16 + + + pa_half_on + 15 + 15 + + + pa_vbcas + 12 + 14 + + + pa_vbcore + 8 + 11 + + + pa_iet + 4 + 7 + + + pa_etb_en + 3 + 3 + + + pa_iaq + 0 + 2 + + + + + pa2 + RX normal bias mode registers + 0x68 + + + pa_ib_fix_hw + 17 + 17 + + + pa_half_on_hw + 16 + 16 + + + pa_vbcas_hw + 12 + 14 + + + pa_vbcore_hw + 8 + 11 + + + pa_iet_hw + 4 + 7 + + + pa_etb_en_hw + 3 + 3 + + + + + tmx + tmx. + 0x6C + + + tx_tsense_en + 16 + 16 + + + tmx_bm_cas_bulk + 12 + 14 + + + tmx_bm_cas + 8 + 10 + + + tmx_bm_sw + 4 + 6 + + + tmx_cs + 0 + 2 + + + + + tbb + tbb. + 0x70 + + + tbb_tosdac_i + 24 + 29 + + + tbb_tosdac_q + 16 + 21 + + + tbb_atest_out_en + 15 + 15 + + + tbb_iq_bias_short + 14 + 14 + + + tbb_cflt + 12 + 13 + + + tbb_vcm + 8 + 9 + + + tbb_bm_cg + 4 + 5 + + + tbb_bm_sf + 0 + 1 + + + + + lna + lna. + 0x74 + + + lna_lg_gsel + 24 + 26 + + + lna_cap_lg + 20 + 21 + + + lna_rfb_match + 16 + 18 + + + lna_load_csw_hw + 12 + 15 + + + lna_load_csw + 8 + 11 + + + lna_bm_hw + 4 + 7 + + + lna_bm + 0 + 3 + + + + + rmxgm + rmxgm. + 0x78 + + + rmxgm_10m_mode_en + 8 + 8 + + + rmxgm_bm + 4 + 6 + + + rmx_bm + 0 + 2 + + + + + rbb1 + rbb1. + 0x7C + + + rosdac_range + 31 + 31 + + + rosdac_i_hw + 24 + 29 + + + rosdac_q_hw + 16 + 21 + + + rosdac_i + 8 + 13 + + + rosdac_q + 0 + 5 + + + + + rbb2 + rbb2. + 0x80 + + + rbb_cap1_fc_i + 24 + 29 + + + rbb_cap1_fc_q + 16 + 21 + + + rbb_cap2_fc_i + 8 + 13 + + + rbb_cap2_fc_q + 0 + 5 + + + + + rbb3 + rbb3. + 0x84 + + + pwr_det_en + 31 + 31 + + + rxiqcal_en + 28 + 28 + + + rbb_bw + 24 + 25 + + + rbb_tia_iqbias_short + 21 + 21 + + + rbb_bq_iqbias_short + 20 + 20 + + + rbb_vcm + 16 + 17 + + + rbb_bm_op + 12 + 14 + + + rbb_deq + 8 + 9 + + + rbb_bt_fif_tune + 5 + 6 + + + rbb_bt_mode + 4 + 4 + + + rbb_bt_mode_hw + 0 + 0 + + + + + rbb4 + rbb4. + 0x88 + + + pkdet_out_latch + 24 + 24 + + + pkdet_out_raw + 20 + 20 + + + rbb_pkdet_en_hw + 16 + 16 + + + rbb_pkdet_out_rstn_hw + 12 + 12 + + + rbb_pkdet_en + 8 + 8 + + + rbb_pkdet_out_rstn + 4 + 4 + + + rbb_pkdet_vth + 0 + 3 + + + + + adda1 + adda1. + 0x8C + + + adda_ldo_dvdd_sel_hw + 24 + 26 + + + adda_ldo_dvdd_sel + 20 + 22 + + + adda_ldo_byps + 16 + 16 + + + dac_clk_sync_inv + 13 + 13 + + + dac_rccalsel + 12 + 12 + + + dac_clk_sel + 8 + 9 + + + dac_bias_sel + 4 + 5 + + + dac_dvdd_sel + 0 + 1 + + + + + adda2 + adda2. + 0x90 + + + adc_clk_div_sel + 28 + 28 + + + adc_clk_inv + 24 + 24 + + + adc_clk_sync_inv + 20 + 20 + + + adc_gt_rm + 16 + 16 + + + adc_sar_ascal_en + 12 + 12 + + + adc_dvdd_sel + 8 + 9 + + + adc_dly_ctl + 4 + 5 + + + adc_vref_sel + 0 + 1 + + + + + vco1 + vco1. + 0xA0 + + + lo_vco_idac_cw_hw + 24 + 28 + + + lo_vco_idac_cw + 16 + 20 + + + lo_vco_freq_cw_hw + 8 + 15 + + + lo_vco_freq_cw + 0 + 7 + + + + + vco2 + vco2. + 0xA4 + + + acal_inc_en_hw + 16 + 16 + + + acal_vco_ud + 12 + 12 + + + acal_vref_cw + 8 + 10 + + + lo_vco_short_idac_filter + 6 + 6 + + + lo_vco_short_vbias_filter + 5 + 5 + + + lo_vco_idac_boot + 4 + 4 + + + lo_vco_vbias_cw + 0 + 1 + + + + + vco3 + vco3. + 0xA8 + + + fcal_cnt_op + 16 + 31 + + + fcal_div + 0 + 15 + + + + + vco4 + vco4. + 0xAC + + + fcal_inc_vctrl_ud + 24 + 25 + + + fcal_cnt_rdy + 20 + 20 + + + fcal_inc_large_range + 16 + 16 + + + fcal_inc_en_hw + 8 + 8 + + + fcal_cnt_start + 4 + 4 + + + + + pfdcp + pfdcp. + 0xB0 + + + lo_pfd_rst_csd_hw + 29 + 29 + + + lo_pfd_rst_csd + 28 + 28 + + + lo_pfd_rvdd_boost + 24 + 24 + + + lo_cp_hiz + 20 + 20 + + + lo_cp_opamp_en + 16 + 16 + + + lo_cp_ota_en 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16 + 16 + + + lo_sdm_bypass + 12 + 12 + + + lo_sdm_dither_sel + 8 + 9 + + + lo_sdm_bypass_hw + 4 + 4 + + + lo_sdm_dither_sel_hw + 0 + 1 + + + + + sdm2 + sdm2. + 0xC4 + + + lo_sdmin + 0 + 29 + + + + + sdm3 + sdm3. + 0xC8 + + + lo_sdmin_hw + 0 + 29 + + + + + rf_resv_reg_0 + rf_resv_reg_0. + 0xEC + + + rf_reserved0 + 0 + 31 + + + + + rf_resv_reg_1 + rf_resv_reg_1. + 0xF0 + + + rf_reserved1 + 0 + 31 + + + + + rf_resv_reg_2 + rf_resv_reg_2. + 0xF4 + + + rf_reserved2 + 0 + 31 + + + + + rrf_gain_index1 + rrf_gain_index1. + 0xF8 + + + gain_ctrl5_gc_lna + 27 + 29 + + + gain_ctrl5_gc_rmxgm + 25 + 26 + + + gain_ctrl4_gc_lna + 22 + 24 + + + gain_ctrl4_gc_rmxgm + 20 + 21 + + + gain_ctrl3_gc_lna + 17 + 19 + + + gain_ctrl3_gc_rmxgm + 15 + 16 + + + gain_ctrl2_gc_lna + 12 + 14 + + + gain_ctrl2_gc_rmxgm + 10 + 11 + + + gain_ctrl1_gc_lna + 7 + 9 + + + gain_ctrl1_gc_rmxgm + 5 + 6 + + + gain_ctrl0_gc_lna + 2 + 4 + + + gain_ctrl0_gc_rmxgm + 0 + 1 + + + + + rrf_gain_index2 + rrf_gain_index2. + 0xFC + + + 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gain_ctrl1_gc_tbb + 16 + 20 + + + gain_ctrl0_gc_tbb_boost + 14 + 15 + + + gain_ctrl0_dac_bias_sel + 12 + 13 + + + gain_ctrl0_gc_tmx + 8 + 10 + + + gain_ctrl0_gc_tbb + 0 + 4 + + + + + tbb_gain_index2 + tbb_gain_index2. + 0x11C + + + gain_ctrl3_gc_tbb_boost + 30 + 31 + + + gain_ctrl3_dac_bias_sel + 28 + 29 + + + gain_ctrl3_gc_tmx + 24 + 26 + + + gain_ctrl3_gc_tbb + 16 + 20 + + + gain_ctrl2_gc_tbb_boost + 14 + 15 + + + gain_ctrl2_dac_bias_sel + 12 + 13 + + + gain_ctrl2_gc_tmx + 8 + 10 + + + gain_ctrl2_gc_tbb + 0 + 4 + + + + + tbb_gain_index3 + tbb_gain_index3. + 0x120 + + + gain_ctrl5_gc_tbb_boost + 30 + 31 + + + gain_ctrl5_dac_bias_sel + 28 + 29 + + + gain_ctrl5_gc_tmx + 24 + 26 + + + gain_ctrl5_gc_tbb + 16 + 20 + + + gain_ctrl4_gc_tbb_boost + 14 + 15 + + + gain_ctrl4_dac_bias_sel + 12 + 13 + + + gain_ctrl4_gc_tmx + 8 + 10 + + + gain_ctrl4_gc_tbb + 0 + 4 + + + + + tbb_gain_index4 + tbb_gain_index4. + 0x124 + + + gain_ctrl7_gc_tbb_boost + 30 + 31 + + + gain_ctrl7_dac_bias_sel + 28 + 29 + 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lo_cal_ctrl_hw5. + 0x14C + + + lo_vco_freq_cw_2440 + 24 + 31 + + + lo_vco_idac_cw_2440 + 16 + 20 + + + lo_vco_freq_cw_2436 + 8 + 15 + + + lo_vco_idac_cw_2436 + 0 + 4 + + + + + lo_cal_ctrl_hw6 + lo_cal_ctrl_hw6. + 0x150 + + + lo_vco_freq_cw_2448 + 24 + 31 + + + lo_vco_idac_cw_2448 + 16 + 20 + + + lo_vco_freq_cw_2444 + 8 + 15 + + + lo_vco_idac_cw_2444 + 0 + 4 + + + + + lo_cal_ctrl_hw7 + lo_cal_ctrl_hw7. + 0x154 + + + lo_vco_freq_cw_2456 + 24 + 31 + + + lo_vco_idac_cw_2456 + 16 + 20 + + + lo_vco_freq_cw_2452 + 8 + 15 + + + lo_vco_idac_cw_2452 + 0 + 4 + + + + + lo_cal_ctrl_hw8 + lo_cal_ctrl_hw8. + 0x158 + + + lo_vco_freq_cw_2464 + 24 + 31 + + + lo_vco_idac_cw_2464 + 16 + 20 + + + lo_vco_freq_cw_2460 + 8 + 15 + + + lo_vco_idac_cw_2460 + 0 + 4 + + + + + lo_cal_ctrl_hw9 + lo_cal_ctrl_hw9. + 0x15C + + + lo_vco_freq_cw_2472 + 24 + 31 + + + lo_vco_idac_cw_2472 + 16 + 20 + + + lo_vco_freq_cw_2468 + 8 + 15 + + + lo_vco_idac_cw_2468 + 0 + 4 + + + + + lo_cal_ctrl_hw10 + lo_cal_ctrl_hw10. + 0x160 + + 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0x17C + + + rx_iq_gain_comp_gc3 + 16 + 26 + + + rx_iq_phase_comp_gc3 + 0 + 9 + + + + + tosdac_ctrl_hw1 + tosdac_ctrl_hw1. + 0x180 + + + tbb_tosdac_q_gc1 + 24 + 29 + + + tbb_tosdac_i_gc1 + 16 + 21 + + + tbb_tosdac_q_gc0 + 8 + 13 + + + tbb_tosdac_i_gc0 + 0 + 5 + + + + + tosdac_ctrl_hw2 + tosdac_ctrl_hw2. + 0x184 + + + tbb_tosdac_q_gc3 + 24 + 29 + + + tbb_tosdac_i_gc3 + 16 + 21 + + + tbb_tosdac_q_gc2 + 8 + 13 + + + tbb_tosdac_i_gc2 + 0 + 5 + + + + + tosdac_ctrl_hw3 + tosdac_ctrl_hw3. + 0x188 + + + tbb_tosdac_q_gc5 + 24 + 29 + + + tbb_tosdac_i_gc5 + 16 + 21 + + + tbb_tosdac_q_gc4 + 8 + 13 + + + tbb_tosdac_i_gc4 + 0 + 5 + + + + + tosdac_ctrl_hw4 + tosdac_ctrl_hw4. + 0x18C + + + tbb_tosdac_q_gc7 + 24 + 29 + + + tbb_tosdac_i_gc7 + 16 + 21 + + + tbb_tosdac_q_gc6 + 8 + 13 + + + tbb_tosdac_i_gc6 + 0 + 5 + + + + + tx_iq_gain_hw0 + tx_iq_gain_hw0. + 0x190 + + + tx_iq_gain_comp_gc0 + 16 + 26 + + + tx_iq_phase_comp_gc0 + 0 + 9 + + + + + tx_iq_gain_hw1 + tx_iq_gain_hw1. + 0x194 + + + tx_iq_gain_comp_gc1 + 16 + 26 + + + tx_iq_phase_comp_gc1 + 0 + 9 + + + + + tx_iq_gain_hw2 + tx_iq_gain_hw2. + 0x198 + + + tx_iq_gain_comp_gc2 + 16 + 26 + + + tx_iq_phase_comp_gc2 + 0 + 9 + + + + + tx_iq_gain_hw3 + tx_iq_gain_hw3. + 0x19C + + + tx_iq_gain_comp_gc3 + 16 + 26 + + + tx_iq_phase_comp_gc3 + 0 + 9 + + + + + tx_iq_gain_hw4 + tx_iq_gain_hw4. + 0x1A0 + + + tx_iq_gain_comp_gc4 + 16 + 26 + + + tx_iq_phase_comp_gc4 + 0 + 9 + + + + + tx_iq_gain_hw5 + tx_iq_gain_hw5. + 0x1A4 + + + tx_iq_gain_comp_gc5 + 16 + 26 + + + tx_iq_phase_comp_gc5 + 0 + 9 + + + + + tx_iq_gain_hw6 + tx_iq_gain_hw6. + 0x1A8 + + + tx_iq_gain_comp_gc6 + 16 + 26 + + + tx_iq_phase_comp_gc6 + 0 + 9 + + + + + tx_iq_gain_hw7 + tx_iq_gain_hw7. + 0x1AC + + + tx_iq_gain_comp_gc7 + 16 + 26 + + + tx_iq_phase_comp_gc7 + 0 + 9 + + + + + lo_sdm_ctrl_hw1 + lo_sdm_ctrl_hw1. + 0x1B0 + + + lo_sdm_dither_sel_wlan_2484 + 26 + 27 + + + lo_sdm_dither_sel_wlan_2472 + 24 + 25 + + + lo_sdm_dither_sel_wlan_2467 + 22 + 23 + + + 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lo_sdm_dither_sel_ble_2410 + 8 + 9 + + + lo_sdm_dither_sel_ble_2408 + 6 + 7 + + + lo_sdm_dither_sel_ble_2406 + 4 + 5 + + + lo_sdm_dither_sel_ble_2404 + 2 + 3 + + + lo_sdm_dither_sel_ble_2402 + 0 + 1 + + + + + lo_sdm_ctrl_hw3 + lo_sdm_ctrl_hw3. + 0x1B8 + + + lo_sdm_dither_sel_ble_2464 + 30 + 31 + + + lo_sdm_dither_sel_ble_2462 + 28 + 29 + + + lo_sdm_dither_sel_ble_2460 + 26 + 27 + + + lo_sdm_dither_sel_ble_2458 + 24 + 25 + + + lo_sdm_dither_sel_ble_2456 + 22 + 23 + + + lo_sdm_dither_sel_ble_2454 + 20 + 21 + + + lo_sdm_dither_sel_ble_2452 + 18 + 19 + + + lo_sdm_dither_sel_ble_2450 + 16 + 17 + + + lo_sdm_dither_sel_ble_2448 + 14 + 15 + + + lo_sdm_dither_sel_ble_2446 + 12 + 13 + + + lo_sdm_dither_sel_ble_2444 + 10 + 11 + + + lo_sdm_dither_sel_ble_2442 + 8 + 9 + + + lo_sdm_dither_sel_ble_2440 + 6 + 7 + + + lo_sdm_dither_sel_ble_2438 + 4 + 5 + + + lo_sdm_dither_sel_ble_2436 + 2 + 3 + + + lo_sdm_dither_sel_ble_2434 + 0 + 1 + + + + + lo_sdm_ctrl_hw4 + lo_sdm_ctrl_hw4. + 0x1BC + + + lo_sdm_dither_sel_ble_tx + 16 + 17 + + + lo_sdm_dither_sel_ble_2480 + 14 + 15 + + + lo_sdm_dither_sel_ble_2478 + 12 + 13 + + + lo_sdm_dither_sel_ble_2476 + 10 + 11 + + + lo_sdm_dither_sel_ble_2474 + 8 + 9 + + + lo_sdm_dither_sel_ble_2472 + 6 + 7 + + + lo_sdm_dither_sel_ble_2470 + 4 + 5 + + + lo_sdm_dither_sel_ble_2468 + 2 + 3 + + + lo_sdm_dither_sel_ble_2466 + 0 + 1 + + + + + lo_sdm_ctrl_hw5 + lo_sdm_ctrl_hw5. + 0x1C0 + + + lo_sdm_bypass_mode + 12 + 17 + + + lo_center_freq_mhz + 0 + 11 + + + + + lo_sdm_ctrl_hw6 + lo_sdm_ctrl_hw6. + 0x1C4 + + + lo_sdmin_center + 0 + 28 + + + + + lo_sdm_ctrl_hw7 + lo_sdm_ctrl_hw7. + 0x1C8 + + + lo_sdmin_1m + 0 + 19 + + + + + lo_sdm_ctrl_hw8 + lo_sdm_ctrl_hw8. + 0x1CC + + + lo_sdmin_if + 0 + 19 + + + + + rbb_bw_ctrl_hw + rbb_bw_ctrl_hw. + 0x1D0 + + + rbb_bt_mode_ble + 0 + 0 + + + + + singen_ctrl0 + singen_ctrl0. + 0x20C + + + singen_en + 31 + 31 + + + singen_clkdiv_n + 29 + 30 + + + singen_unsign_en + 28 + 28 + + + singen_inc_step0 + 16 + 25 + + + singen_inc_step1 + 0 + 9 + + + + + singen_ctrl1 + singen_ctrl1. + 0x210 + + + singen_mode_i + 28 + 31 + + + singen_clkdiv_i + 16 + 25 + + + singen_mode_q + 12 + 15 + + + singen_clkdiv_q + 0 + 9 + + + + + singen_ctrl2 + singen_ctrl2. + 0x214 + + + singen_start_addr0_i + 22 + 31 + + + singen_start_addr1_i + 12 + 21 + + + singen_gain_i + 0 + 10 + + + + + singen_ctrl3 + singen_ctrl3. + 0x218 + + + singen_start_addr0_q + 22 + 31 + + + singen_start_addr1_q + 12 + 21 + + + singen_gain_q + 0 + 10 + + + + + singen_ctrl4 + singen_ctrl4. + 0x21C + + + singen_fix_en_i + 28 + 28 + + + singen_fix_i + 16 + 27 + + + singen_fix_en_q + 12 + 12 + + + singen_fix_q + 0 + 11 + + + + + rfif_dfe_ctrl0 + rfif_dfe_ctrl0. + 0x220 + + + test_sel + 28 + 31 + + + bbmode_4s_en + 27 + 27 + + + bbmode_4s + 26 + 26 + + + wifimode_4s_en + 25 + 25 + + + wifimode_4s + 23 + 24 + + + rf_ch_ind_ble_4s_en + 22 + 22 + + + rf_ch_ind_ble_4s + 15 + 21 + + + pad_dac_clkout_inv_en + 14 + 14 + + + pad_adc_clkout_inv_en + 13 + 13 + + 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rf_data_temp_3 + 0 + 31 + + + + + rf_sram_ctrl0 + rf_sram_ctrl0. + 0x23C + + + rf_sram_ext_clr + 19 + 19 + + + rf_sram_swap + 18 + 18 + + + rf_sram_link_mode + 16 + 17 + + + rf_sram_link_dly + 0 + 15 + + + + + rf_sram_ctrl1 + rf_sram_ctrl1. + 0x240 + + + rf_sram_adc_done_cnt + 16 + 31 + + + rf_sram_adc_sts_clr + 3 + 3 + + + rf_sram_adc_loop_en + 2 + 2 + + + rf_sram_adc_en + 1 + 1 + + + rf_sram_adc_done + 0 + 0 + + + + + rf_sram_ctrl2 + rf_sram_ctrl2. + 0x244 + + + rf_sram_adc_addr_start + 16 + 31 + + + rf_sram_adc_addr_end + 0 + 15 + + + + + rf_sram_ctrl3 + rf_sram_ctrl3. + 0x248 + + + rf_sram_adc_sts + 0 + 31 + + + + + rf_sram_ctrl4 + rf_sram_ctrl4. + 0x24C + + + rf_sram_dac_done_cnt + 16 + 31 + + + rf_sram_dac_sts_clr + 3 + 3 + + + rf_sram_dac_loop_en + 2 + 2 + + + rf_sram_dac_en + 1 + 1 + + + rf_sram_dac_done + 0 + 0 + + + + + rf_sram_ctrl5 + rf_sram_ctrl5. + 0x250 + + + rf_sram_dac_addr_start + 16 + 31 + + + rf_sram_dac_addr_end + 0 + 15 + + + + + rf_sram_ctrl6 + rf_sram_ctrl6. + 0x254 + + + rf_sram_dac_sts + 0 + 31 + + + + + rf_ical_ctrl0 + rf_ical_ctrl0. + 0x258 + + + rf_ical_f_ud_inv_en + 31 + 31 + + + rf_ical_a_ud_inv_en + 30 + 30 + + + rf_ical_f_cnt_n + 20 + 29 + + + rf_ical_a_cnt_n + 10 + 19 + + + rf_ical_r_cnt_n + 0 + 9 + + + + + rf_ical_ctrl1 + rf_ical_ctrl1. + 0x25C + + + rf_ical_r_os_i + 20 + 29 + + + rf_ical_r_os_q + 10 + 19 + + + rf_ical_r_avg_n + 0 + 4 + + + + + rf_ical_ctrl2 + rf_ical_ctrl2. + 0x260 + + + rf_ical_period_n + 0 + 15 + + + + + rf_fsm_ctrl0 + rf_fsm_ctrl0. + 0x264 + + + rf_ch_ind_wifi + 0 + 11 + + + + + rf_fsm_ctrl1 + rf_fsm_ctrl1. + 0x268 + + + rf_fsm_pu_pa_dly_n + 20 + 29 + + + rf_fsm_lo_rdy_sbclr + 19 + 19 + + + rf_fsm_lo_rdy_4s_1 + 18 + 18 + + + rf_fsm_lo_rdy_rst + 17 + 17 + + + rf_fsm_lo_rdy + 16 + 16 + + + rf_fsm_lo_time + 0 + 15 + + + + + rf_fsm_ctrl2 + rf_fsm_ctrl2. + 0x26C + + + rf_fsm_dfe_rx_dly_n + 20 + 29 + + + rf_fsm_dfe_tx_dly_n + 10 + 19 + + + rf_trx_ble_4s_en + 6 + 6 + + + rf_trx_sw_ble_4s + 5 + 5 + + + rf_trx_en_ble_4s + 4 + 4 + + + rf_fsm_st_dbg_en + 3 + 3 + + + rf_fsm_st_dbg + 0 + 2 + + + + + rf_pkdet_ctrl0 + rf_pkdet_ctrl0. + 0x270 + + + pkdet_out_mode + 5 + 5 + + + pkdet_out_cnt_en + 4 + 4 + + + pkdet_out_cnt_sts + 0 + 3 + + + + + dfe_ctrl_0 + dfe_ctrl_0. + 0x600 + + + tx_dvga_gain_ctrl_hw + 31 + 31 + + + tx_dvga_gain_qdb + 24 + 30 + + + tx_iqc_gain_en + 23 + 23 + + + tx_iqc_gain + 12 + 22 + + + tx_iqc_phase_en + 10 + 10 + + + tx_iqc_phase + 0 + 9 + + + + + dfe_ctrl_1 + dfe_ctrl_1. + 0x604 + + + tx_dac_iq_swap + 31 + 31 + + + tx_dac_dat_format + 30 + 30 + + + tx_dac_os_q + 16 + 27 + + + tx_dac_os_i + 0 + 11 + + + + + dfe_ctrl_2 + dfe_ctrl_2. + 0x608 + + + rx_adc_iq_swap + 31 + 31 + + + rx_adc_dat_format + 30 + 30 + + + rx_adc_low_pow_en + 29 + 29 + + + rx_adc_dce_flt_en + 28 + 28 + + + rx_adc_os_q + 16 + 25 + + + rx_adc_os_i + 0 + 9 + + + + + dfe_ctrl_3 + dfe_ctrl_3. + 0x60C + + + rx_adc_4s_q_en + 26 + 26 + + + rx_adc_4s_q_val + 16 + 25 + + + rx_adc_4s_i_en + 10 + 10 + + + rx_adc_4s_i_val + 0 + 9 + + + + + dfe_ctrl_4 + dfe_ctrl_4. + 0x610 + + + rx_pf_i_en + 31 + 31 + + + rx_pf_q_en + 30 + 30 + + + rx_pf_th1 + 16 + 25 + + + rx_pf_th2 + 0 + 9 + + + + + dfe_ctrl_5 + dfe_ctrl_5. + 0x614 + + + rx_iqc_gain_en + 23 + 23 + + + rx_iqc_gain + 12 + 22 + + + rx_iqc_phase_en + 10 + 10 + + + rx_iqc_phase + 0 + 9 + + + + + dfe_ctrl_6 + dfe_ctrl_6. + 0x618 + + + rx_pm_in_sel + 30 + 31 + + + rx_pm_en + 29 + 29 + + + rx_pm_done + 28 + 28 + + + rx_pm_freqshift_en + 20 + 20 + + + rx_pm_freqshift_cw + 0 + 19 + + + + + dfe_ctrl_7 + dfe_ctrl_7. + 0x61C + + + rx_pm_acc_len + 16 + 31 + + + rx_pm_start_ofs + 0 + 15 + + + + + dfe_ctrl_8 + dfe_ctrl_8. + 0x620 + + + rx_pm_iqacc_i + 0 + 24 + + + + + dfe_ctrl_9 + dfe_ctrl_9. + 0x624 + + + rx_pm_iqacc_q + 0 + 24 + + + + + dfe_ctrl_10 + dfe_ctrl_10. + 0x628 + + + dfe_dac_raw_q + 16 + 26 + + + dfe_dac_raw_i + 0 + 10 + + + + + dfe_ctrl_11 + dfe_ctrl_11. + 0x62C + + + dfe_adc_raw_q + 16 + 25 + + + dfe_adc_raw_i + 0 + 9 + + + + + dfe_ctrl_12 + dfe_ctrl_12. + 0x630 + + + tx_dvga_gain_qdb_gc3 + 24 + 30 + + + tx_dvga_gain_qdb_gc2 + 16 + 22 + + + tx_dvga_gain_qdb_gc1 + 8 + 14 + + + tx_dvga_gain_qdb_gc0 + 0 + 6 + + + + + dfe_ctrl_13 + dfe_ctrl_13. + 0x634 + + + tx_dvga_gain_qdb_gc7 + 24 + 30 + + + tx_dvga_gain_qdb_gc6 + 16 + 22 + + + tx_dvga_gain_qdb_gc5 + 8 + 14 + + + tx_dvga_gain_qdb_gc4 + 0 + 6 + + + + + dfe_ctrl_14 + dfe_ctrl_14. + 0x638 + + + tx_dvga_gain_qdb_gc11 + 24 + 30 + + + tx_dvga_gain_qdb_gc10 + 16 + 22 + + + tx_dvga_gain_qdb_gc9 + 8 + 14 + + + tx_dvga_gain_qdb_gc8 + 0 + 6 + + + + + dfe_ctrl_15 + dfe_ctrl_15. + 0x63C + + + tx_dvga_gain_qdb_gc15 + 24 + 30 + + + tx_dvga_gain_qdb_gc14 + 16 + 22 + + + tx_dvga_gain_qdb_gc13 + 8 + 14 + + + tx_dvga_gain_qdb_gc12 + 0 + 6 + + + + + dfe_ctrl_16 + dfe_ctrl_16. + 0x640 + + + rf_tbb_ind_gc7 + 28 + 30 + + + rf_tbb_ind_gc6 + 24 + 26 + + + rf_tbb_ind_gc5 + 20 + 22 + + + rf_tbb_ind_gc4 + 16 + 18 + + + rf_tbb_ind_gc3 + 12 + 14 + + + rf_tbb_ind_gc2 + 8 + 10 + + + rf_tbb_ind_gc1 + 4 + 6 + + + rf_tbb_ind_gc0 + 0 + 2 + + + + + dfe_ctrl_17 + dfe_ctrl_17. + 0x644 + + + rf_tbb_ind_gc15 + 28 + 30 + + + rf_tbb_ind_gc14 + 24 + 26 + + + rf_tbb_ind_gc13 + 20 + 22 + + + rf_tbb_ind_gc12 + 16 + 18 + + + rf_tbb_ind_gc11 + 12 + 14 + + + rf_tbb_ind_gc10 + 8 + 10 + + + rf_tbb_ind_gc9 + 4 + 6 + + + rf_tbb_ind_gc8 + 0 + 2 + + + + + dfe_ctrl_18 + dfe_ctrl_18. + 0x648 + + + tx_dvga_gain_qdb_ble_gc2 + 16 + 22 + + + tx_dvga_gain_qdb_ble_gc1 + 8 + 14 + + + tx_dvga_gain_qdb_ble_gc0 + 0 + 6 + + + + + + + gpip + gpip. + 0x40002000 + gpip + 32 + read-write + + 0 + 0x1000 + registers + + + + gpadc_config + gpadc_config. + 0x0 + + + rsvd_31_24 + 24 + 31 + + + gpadc_fifo_thl + 22 + 23 + + + gpadc_fifo_data_count + 16 + 21 + + + gpadc_fifo_underrun_mask + 14 + 14 + + + gpadc_fifo_overrun_mask + 13 + 13 + + + gpadc_rdy_mask + 12 + 12 + + + gpadc_fifo_underrun_clr + 10 + 10 + + + gpadc_fifo_overrun_clr + 9 + 9 + + + gpadc_rdy_clr + 8 + 8 + + + gpadc_fifo_underrun + 6 + 6 + + + gpadc_fifo_overrun + 5 + 5 + + + gpadc_rdy + 4 + 4 + + + gpadc_fifo_full + 3 + 3 + + + gpadc_fifo_ne + 2 + 2 + + + gpadc_fifo_clr + 1 + 1 + + + gpadc_dma_en + 0 + 0 + + + + + gpadc_dma_rdata + gpadc_dma_rdata. + 0x4 + + + rsvd_31_26 + 26 + 31 + + + gpadc_dma_rdata + 0 + 25 + + + + + gpdac_config + gpdac_config. + 0x40 + + + rsvd_31_24 + 24 + 31 + + + gpdac_ch_b_sel + 20 + 23 + + + gpdac_ch_a_sel + 16 + 19 + + + gpdac_mode + 8 + 10 + + + dsm_mode + 4 + 5 + + + gpdac_en2 + 1 + 1 + + + gpdac_en + 0 + 0 + + + + + gpdac_dma_config + gpdac_dma_config. + 0x44 + + + gpdac_dma_format + 4 + 5 + + + gpdac_dma_tx_en + 0 + 0 + + + + + gpdac_dma_wdata + gpdac_dma_wdata. + 0x48 + + + gpdac_dma_wdata + 0 + 31 + + + + + gpdac_tx_fifo_status + gpdac_tx_fifo_status. + 0x4C + + + TxFifoWrPtr + 8 + 9 + + + TxFifoRdPtr + 4 + 6 + + + tx_cs + 2 + 3 + + + tx_fifo_full + 1 + 1 + + + tx_fifo_empty + 0 + 0 + + + + + + + sec_dbg + sec_dbg. + 0x40003000 + sec_dbg + 32 + read-write + + 0 + 0x1000 + registers + + + + sd_chip_id_low + sd_chip_id_low. + 0x0 + + + sd_chip_id_low + 0 + 31 + + + + + sd_chip_id_high + sd_chip_id_high. + 0x4 + + + sd_chip_id_high + 0 + 31 + + + + + sd_wifi_mac_low + sd_wifi_mac_low. + 0x8 + + + sd_wifi_mac_low + 0 + 31 + + + + + sd_wifi_mac_high + sd_wifi_mac_high. + 0xC + + + sd_wifi_mac_high + 0 + 31 + + + + + sd_dbg_pwd_low + sd_dbg_pwd_low. + 0x10 + + + sd_dbg_pwd_low + 0 + 31 + + + + + sd_dbg_pwd_high + sd_dbg_pwd_high. + 0x14 + + + sd_dbg_pwd_high + 0 + 31 + + + + + sd_status + sd_status. + 0x18 + + + sd_dbg_ena + 28 + 31 + + + sd_dbg_mode + 24 + 27 + + + sd_dbg_pwd_cnt + 4 + 23 + + + sd_dbg_cci_clk_sel + 3 + 3 + + + sd_dbg_cci_read_en + 2 + 2 + + + sd_dbg_pwd_trig + 1 + 1 + + + sd_dbg_pwd_busy + 0 + 0 + + + + + sd_dbg_reserved + sd_dbg_reserved. + 0x1C + + + sd_dbg_reserved + 0 + 31 + + + + + + + sec_eng + sec_eng. + 0x40004000 + sec_eng + 32 + read-write + + 0 + 0x1000 + registers + + + + se_sha_0_ctrl + se_sha_0_ctrl. + 0x0 + + + se_sha_0_msg_len + 16 + 31 + + + se_sha_0_link_mode + 15 + 15 + + + se_sha_0_int_mask + 11 + 11 + + + se_sha_0_int_set_1t + 10 + 10 + + + se_sha_0_int_clr_1t + 9 + 9 + + + se_sha_0_int + 8 + 8 + + + se_sha_0_hash_sel + 6 + 6 + + + se_sha_0_en + 5 + 5 + + + se_sha_0_mode + 2 + 4 + + + se_sha_0_trig_1t + 1 + 1 + + + se_sha_0_busy + 0 + 0 + + + + + se_sha_0_msa + se_sha_0_msa. + 0x4 + + + se_sha_0_msa + 0 + 31 + + + + + se_sha_0_status + se_sha_0_status. + 0x8 + + + se_sha_0_status + 0 + 31 + + + + + se_sha_0_endian + se_sha_0_endian. + 0xC + + + se_sha_0_dout_endian + 0 + 0 + + + + + se_sha_0_hash_l_0 + se_sha_0_hash_l_0. + 0x10 + + + se_sha_0_hash_l_0 + 0 + 31 + + + + + se_sha_0_hash_l_1 + se_sha_0_hash_l_1. + 0x14 + + + se_sha_0_hash_l_1 + 0 + 31 + + + + + se_sha_0_hash_l_2 + se_sha_0_hash_l_2. + 0x18 + + + se_sha_0_hash_l_2 + 0 + 31 + + + + + se_sha_0_hash_l_3 + se_sha_0_hash_l_3. + 0x1C + + + se_sha_0_hash_l_3 + 0 + 31 + + + + + se_sha_0_hash_l_4 + se_sha_0_hash_l_4. + 0x20 + + + se_sha_0_hash_l_4 + 0 + 31 + + + + + se_sha_0_hash_l_5 + se_sha_0_hash_l_5. + 0x24 + + + se_sha_0_hash_l_5 + 0 + 31 + + + + + se_sha_0_hash_l_6 + se_sha_0_hash_l_6. + 0x28 + + + se_sha_0_hash_l_6 + 0 + 31 + + + + + se_sha_0_hash_l_7 + se_sha_0_hash_l_7. + 0x2C + + + se_sha_0_hash_l_7 + 0 + 31 + + + + + se_sha_0_hash_h_0 + se_sha_0_hash_h_0. + 0x30 + + + se_sha_0_hash_h_0 + 0 + 31 + + + + + se_sha_0_hash_h_1 + se_sha_0_hash_h_1. + 0x34 + + + se_sha_0_hash_h_1 + 0 + 31 + + + + + se_sha_0_hash_h_2 + se_sha_0_hash_h_2. + 0x38 + + + se_sha_0_hash_h_2 + 0 + 31 + + + + + se_sha_0_hash_h_3 + se_sha_0_hash_h_3. + 0x3C + + + se_sha_0_hash_h_3 + 0 + 31 + + + + + se_sha_0_hash_h_4 + se_sha_0_hash_h_4. + 0x40 + + + se_sha_0_hash_h_4 + 0 + 31 + + + + + se_sha_0_hash_h_5 + se_sha_0_hash_h_5. + 0x44 + + + se_sha_0_hash_h_5 + 0 + 31 + + + + + se_sha_0_hash_h_6 + se_sha_0_hash_h_6. + 0x48 + + + se_sha_0_hash_h_6 + 0 + 31 + + + + + se_sha_0_hash_h_7 + se_sha_0_hash_h_7. + 0x4C + + + se_sha_0_hash_h_7 + 0 + 31 + + + + + se_sha_0_link + se_sha_0_link. + 0x50 + + + se_sha_0_lca + 0 + 31 + + + + + se_sha_0_ctrl_prot + se_sha_0_ctrl_prot. + 0xFC + + + se_sha_id1_en + 2 + 2 + + + se_sha_id0_en + 1 + 1 + + + se_sha_prot_en + 0 + 0 + + + + + se_aes_0_ctrl + se_aes_0_ctrl. + 0x100 + + + se_aes_0_msg_len + 16 + 31 + + + se_aes_0_link_mode + 15 + 15 + + + se_aes_0_iv_sel + 14 + 14 + + + se_aes_0_block_mode + 12 + 13 + + + se_aes_0_int_mask + 11 + 11 + + + se_aes_0_int_set_1t + 10 + 10 + + + se_aes_0_int_clr_1t + 9 + 9 + + + se_aes_0_int + 8 + 8 + + + se_aes_0_hw_key_en + 7 + 7 + + + se_aes_0_dec_key_sel + 6 + 6 + + + se_aes_0_dec_en + 5 + 5 + + + se_aes_0_mode + 3 + 4 + + + se_aes_0_en + 2 + 2 + + + se_aes_0_trig_1t + 1 + 1 + + + se_aes_0_busy + 0 + 0 + + + + + se_aes_0_msa + se_aes_0_msa. + 0x104 + + + se_aes_0_msa + 0 + 31 + + + + + se_aes_0_mda + se_aes_0_mda. + 0x108 + + + se_aes_0_mda + 0 + 31 + + + + + se_aes_0_status + se_aes_0_status. + 0x10C + + + se_aes_0_status + 0 + 31 + + + + + se_aes_0_iv_0 + se_aes_0_iv_0. + 0x110 + + + se_aes_0_iv_0 + 0 + 31 + + + + + se_aes_0_iv_1 + se_aes_0_iv_1. + 0x114 + + + se_aes_0_iv_1 + 0 + 31 + + + + + se_aes_0_iv_2 + se_aes_0_iv_2. + 0x118 + + + se_aes_0_iv_2 + 0 + 31 + + + + + se_aes_0_iv_3 + se_aes_0_iv_3. + 0x11C + + + se_aes_0_iv_3 + 0 + 31 + + + + + se_aes_0_key_0 + se_aes_0_key_0. + 0x120 + + + se_aes_0_key_0 + 0 + 31 + + + + + se_aes_0_key_1 + se_aes_0_key_1. + 0x124 + + + se_aes_0_key_1 + 0 + 31 + + + + + se_aes_0_key_2 + se_aes_0_key_2. + 0x128 + + + se_aes_0_key_2 + 0 + 31 + + + + + se_aes_0_key_3 + se_aes_0_key_3. + 0x12C + + + se_aes_0_key_3 + 0 + 31 + + + + + se_aes_0_key_4 + se_aes_0_key_4. + 0x130 + + + se_aes_0_key_4 + 0 + 31 + + + + + se_aes_0_key_5 + se_aes_0_key_5. + 0x134 + + + se_aes_0_key_5 + 0 + 31 + + + + + se_aes_0_key_6 + se_aes_0_key_6. + 0x138 + + + se_aes_0_key_6 + 0 + 31 + + + + + se_aes_0_key_7 + se_aes_0_key_7. + 0x13C + + + se_aes_0_key_7 + 0 + 31 + + + + + se_aes_0_key_sel_0 + se_aes_0_key_sel_0. + 0x140 + + + se_aes_0_key_sel_0 + 0 + 1 + + + + + se_aes_0_key_sel_1 + se_aes_0_key_sel_1. + 0x144 + + + se_aes_0_key_sel_1 + 0 + 1 + + + + + se_aes_0_endian + se_aes_0_endian. + 0x148 + + + se_aes_0_ctr_len + 30 + 31 + + + se_aes_0_iv_endian + 3 + 3 + + + se_aes_0_key_endian + 2 + 2 + + + se_aes_0_din_endian + 1 + 1 + + + se_aes_0_dout_endian + 0 + 0 + + + + + se_aes_0_sboot + se_aes_0_sboot. + 0x14C + + + se_aes_0_sboot_key_sel + 0 + 0 + + + + + se_aes_0_link + se_aes_0_link. + 0x150 + + + se_aes_0_lca + 0 + 31 + + + + + se_aes_0_ctrl_prot + se_aes_0_ctrl_prot. + 0x1FC + + + se_aes_id1_en + 2 + 2 + + + se_aes_id0_en + 1 + 1 + + + se_aes_prot_en + 0 + 0 + + + + + se_trng_0_ctrl_0 + se_trng_0_ctrl_0. + 0x200 + + + se_trng_0_manual_en + 15 + 15 + + + se_trng_0_manual_reseed + 14 + 14 + + + se_trng_0_manual_fun_sel + 13 + 13 + + + se_trng_0_int_mask + 11 + 11 + + + se_trng_0_int_set_1t + 10 + 10 + + + se_trng_0_int_clr_1t + 9 + 9 + + + se_trng_0_int + 8 + 8 + + + se_trng_0_ht_error + 4 + 4 + + + se_trng_0_dout_clr_1t + 3 + 3 + + + se_trng_0_en + 2 + 2 + + + se_trng_0_trig_1t + 1 + 1 + + + se_trng_0_busy + 0 + 0 + + + + + se_trng_0_status + se_trng_0_status. + 0x204 + + + se_trng_0_status + 0 + 31 + + + + + se_trng_0_dout_0 + se_trng_0_dout_0. + 0x208 + + + se_trng_0_dout_0 + 0 + 31 + + + + + se_trng_0_dout_1 + se_trng_0_dout_1. + 0x20C + + + se_trng_0_dout_1 + 0 + 31 + + + + + se_trng_0_dout_2 + se_trng_0_dout_2. + 0x210 + + + se_trng_0_dout_2 + 0 + 31 + + + + + se_trng_0_dout_3 + se_trng_0_dout_3. + 0x214 + + + se_trng_0_dout_3 + 0 + 31 + + + + + se_trng_0_dout_4 + se_trng_0_dout_4. + 0x218 + + + se_trng_0_dout_4 + 0 + 31 + + + + + se_trng_0_dout_5 + se_trng_0_dout_5. + 0x21C + + + se_trng_0_dout_5 + 0 + 31 + + + + + se_trng_0_dout_6 + se_trng_0_dout_6. + 0x220 + + + se_trng_0_dout_6 + 0 + 31 + + + + + se_trng_0_dout_7 + se_trng_0_dout_7. + 0x224 + + + se_trng_0_dout_7 + 0 + 31 + + + + + se_trng_0_test + se_trng_0_test. + 0x228 + + + se_trng_0_ht_alarm_n + 4 + 11 + + + se_trng_0_ht_dis + 3 + 3 + + + se_trng_0_cp_bypass + 2 + 2 + + + se_trng_0_cp_test_en + 1 + 1 + + + se_trng_0_test_en + 0 + 0 + + + + + se_trng_0_ctrl_1 + se_trng_0_ctrl_1. + 0x22C + + + se_trng_0_reseed_n_lsb + 0 + 31 + + + + + se_trng_0_ctrl_2 + se_trng_0_ctrl_2. + 0x230 + + + se_trng_0_reseed_n_msb + 0 + 15 + + + + + se_trng_0_ctrl_3 + se_trng_0_ctrl_3. + 0x234 + + + se_trng_0_rosc_en + 31 + 31 + + + se_trng_0_ht_od_en + 26 + 26 + + + se_trng_0_ht_apt_c + 16 + 25 + + + se_trng_0_ht_rct_c + 8 + 15 + + + se_trng_0_cp_ratio + 0 + 7 + + + + + se_trng_0_test_out_0 + se_trng_0_test_out_0. + 0x240 + + + se_trng_0_test_out_0 + 0 + 31 + + + + + se_trng_0_test_out_1 + se_trng_0_test_out_1. + 0x244 + + + se_trng_0_test_out_1 + 0 + 31 + + + + + se_trng_0_test_out_2 + se_trng_0_test_out_2. + 0x248 + + + se_trng_0_test_out_2 + 0 + 31 + + + + + se_trng_0_test_out_3 + se_trng_0_test_out_3. + 0x24C + + + se_trng_0_test_out_3 + 0 + 31 + + + + + se_trng_0_ctrl_prot + se_trng_0_ctrl_prot. + 0x2FC + + + se_trng_id1_en + 2 + 2 + + + se_trng_id0_en + 1 + 1 + + + se_trng_prot_en + 0 + 0 + + + + + se_pka_0_ctrl_0 + se_pka_0_ctrl_0. + 0x300 + + + se_pka_0_status + 17 + 31 + + + se_pka_0_status_clr_1t + 16 + 16 + + + se_pka_0_ram_clr_md + 13 + 13 + + + se_pka_0_endian + 12 + 12 + + + se_pka_0_int_mask + 11 + 11 + + + se_pka_0_int_set + 10 + 10 + + + se_pka_0_int_clr_1t + 9 + 9 + + + se_pka_0_int + 8 + 8 + + + se_pka_0_prot_md + 4 + 7 + + + se_pka_0_en + 3 + 3 + + + se_pka_0_busy + 2 + 2 + + + se_pka_0_done_clr_1t + 1 + 1 + + + se_pka_0_done + 0 + 0 + + + + + se_pka_0_seed + se_pka_0_seed. + 0x30C + + + se_pka_0_seed + 0 + 31 + + + + + se_pka_0_ctrl_1 + se_pka_0_ctrl_1. + 0x310 + + + se_pka_0_hbypass + 3 + 3 + + + se_pka_0_hburst + 0 + 2 + + + + + se_pka_0_rw + se_pka_0_rw. + 0x340 + + + + se_pka_0_rw_burst + se_pka_0_rw_burst. + 0x360 + + + + se_pka_0_ctrl_prot + se_pka_0_ctrl_prot. + 0x3FC + + + se_pka_id1_en + 2 + 2 + + + se_pka_id0_en + 1 + 1 + + + se_pka_prot_en + 0 + 0 + + + + + se_cdet_0_ctrl_0 + se_cdet_0_ctrl_0. + 0x400 + + + se_cdet_0_g_loop_min + 24 + 31 + + + se_cdet_0_g_loop_max + 16 + 23 + + + se_cdet_0_status + 2 + 15 + + + se_cdet_0_error + 1 + 1 + + + se_cdet_0_en + 0 + 0 + + + + + se_cdet_0_ctrl_1 + se_cdet_0_ctrl_1. + 0x404 + + + se_cdet_0_g_slp_n + 16 + 23 + + + se_cdet_0_t_dly_n + 8 + 15 + + + se_cdet_0_t_loop_n + 0 + 7 + + + + + se_cdet_0_ctrl_prot + se_cdet_0_ctrl_prot. + 0x4FC + + + se_cdet_id1_en + 2 + 2 + + + se_cdet_id0_en + 1 + 1 + + + se_cdet_prot_en + 0 + 0 + + + + + se_gmac_0_ctrl_0 + se_gmac_0_ctrl_0. + 0x500 + + + se_gmac_0_x_endian + 14 + 14 + + + se_gmac_0_h_endian + 13 + 13 + + + se_gmac_0_t_endian + 12 + 12 + + + se_gmac_0_int_mask + 11 + 11 + + + se_gmac_0_int_set_1t + 10 + 10 + + + se_gmac_0_int_clr_1t + 9 + 9 + + + se_gmac_0_int + 8 + 8 + + + se_gmac_0_en + 2 + 2 + + + se_gmac_0_trig_1t + 1 + 1 + + + se_gmac_0_busy + 0 + 0 + + + + + se_gmac_0_lca + se_gmac_0_lca. + 0x504 + + + se_gmac_0_lca + 0 + 31 + + + + + se_gmac_0_status + se_gmac_0_status. + 0x508 + + + se_gmac_0_status + 0 + 31 + + + + + se_gmac_0_ctrl_prot + se_gmac_0_ctrl_prot. + 0x5FC + + + se_gmac_id1_en + 2 + 2 + + + se_gmac_id0_en + 1 + 1 + + + se_gmac_prot_en + 0 + 0 + + + + + se_ctrl_prot_rd + se_ctrl_prot_rd. + 0xF00 + + + se_dbg_dis + 31 + 31 + + + se_gmac_id1_en_rd + 22 + 22 + + + se_gmac_id0_en_rd + 21 + 21 + + + se_gmac_prot_en_rd + 20 + 20 + + + se_cdet_id1_en_rd + 18 + 18 + + + se_cdet_id0_en_rd + 17 + 17 + + + se_cdet_prot_en_rd + 16 + 16 + + + se_pka_id1_en_rd + 14 + 14 + + + se_pka_id0_en_rd + 13 + 13 + + + se_pka_prot_en_rd + 12 + 12 + + + se_trng_id1_en_rd + 10 + 10 + + + se_trng_id0_en_rd + 9 + 9 + + + se_trng_prot_en_rd + 8 + 8 + + + se_aes_id1_en_rd + 6 + 6 + + + se_aes_id0_en_rd + 5 + 5 + + + se_aes_prot_en_rd + 4 + 4 + + + se_sha_id1_en_rd + 2 + 2 + + + se_sha_id0_en_rd + 1 + 1 + + + se_sha_prot_en_rd + 0 + 0 + + + + + se_ctrl_reserved_0 + se_ctrl_reserved_0. + 0xF04 + + + se_ctrl_reserved_0 + 0 + 31 + + + + + se_ctrl_reserved_1 + se_ctrl_reserved_1. + 0xF08 + + + se_ctrl_reserved_1 + 0 + 31 + + + + + se_ctrl_reserved_2 + se_ctrl_reserved_2. + 0xF0C + + + se_ctrl_reserved_2 + 0 + 31 + + + + + + + tzc_sec + tzc_sec. + 0x40005000 + tzc_sec + 32 + read-write + + 0 + 0x1000 + registers + + + + tzc_rom_ctrl + tzc_rom_ctrl. + 0x40 + + + tzc_sboot_done + 28 + 31 + + + tzc_rom1_r1_lock + 27 + 27 + + + tzc_rom1_r0_lock + 26 + 26 + + + tzc_rom0_r1_lock + 25 + 25 + + + tzc_rom0_r0_lock + 24 + 24 + + + tzc_rom1_r1_en + 19 + 19 + + + tzc_rom1_r0_en + 18 + 18 + + + tzc_rom0_r1_en + 17 + 17 + + + tzc_rom0_r0_en + 16 + 16 + + + tzc_rom1_r1_id1_en + 11 + 11 + + + tzc_rom1_r0_id1_en + 10 + 10 + + + tzc_rom0_r1_id1_en + 9 + 9 + + + tzc_rom0_r0_id1_en + 8 + 8 + + + tzc_rom1_r1_id0_en + 3 + 3 + + + tzc_rom1_r0_id0_en + 2 + 2 + + + tzc_rom0_r1_id0_en + 1 + 1 + + + tzc_rom0_r0_id0_en + 0 + 0 + + + + + tzc_rom0_r0 + tzc_rom0_r0. + 0x44 + + + tzc_rom0_r0_start + 16 + 31 + + + tzc_rom0_r0_end + 0 + 15 + + + + + tzc_rom0_r1 + tzc_rom0_r1. + 0x48 + + + tzc_rom0_r1_start + 16 + 31 + + + tzc_rom0_r1_end + 0 + 15 + + + + + tzc_rom1_r0 + tzc_rom1_r0. + 0x4C + + + tzc_rom1_r0_start + 16 + 31 + + + tzc_rom1_r0_end + 0 + 15 + + + + + tzc_rom1_r1 + tzc_rom1_r1. + 0x50 + + + tzc_rom1_r1_start + 16 + 31 + + + tzc_rom1_r1_end + 0 + 15 + + + + + + + tzc_nsec + tzc_nsec. + 0x40006000 + tzc_nsec + 32 + read-write + + 0 + 0x1000 + registers + + + + tzc_rom_ctrl + tzc_rom_ctrl. + 0x40 + + + tzc_sboot_done + 28 + 31 + + + tzc_rom1_r1_lock + 27 + 27 + + + tzc_rom1_r0_lock + 26 + 26 + + + tzc_rom0_r1_lock + 25 + 25 + + + tzc_rom0_r0_lock + 24 + 24 + + + tzc_rom1_r1_en + 19 + 19 + + + tzc_rom1_r0_en + 18 + 18 + + + tzc_rom0_r1_en + 17 + 17 + + + tzc_rom0_r0_en + 16 + 16 + + + tzc_rom1_r1_id1_en + 11 + 11 + + + tzc_rom1_r0_id1_en + 10 + 10 + + + tzc_rom0_r1_id1_en + 9 + 9 + + + tzc_rom0_r0_id1_en + 8 + 8 + + + tzc_rom1_r1_id0_en + 3 + 3 + + + tzc_rom1_r0_id0_en + 2 + 2 + + + tzc_rom0_r1_id0_en + 1 + 1 + + + tzc_rom0_r0_id0_en + 0 + 0 + + + + + tzc_rom0_r0 + tzc_rom0_r0. + 0x44 + + + tzc_rom0_r0_start + 16 + 31 + + + tzc_rom0_r0_end + 0 + 15 + + + + + tzc_rom0_r1 + tzc_rom0_r1. + 0x48 + + + tzc_rom0_r1_start + 16 + 31 + + + tzc_rom0_r1_end + 0 + 15 + + + + + tzc_rom1_r0 + tzc_rom1_r0. + 0x4C + + + tzc_rom1_r0_start + 16 + 31 + + + tzc_rom1_r0_end + 0 + 15 + + + + + tzc_rom1_r1 + tzc_rom1_r1. + 0x50 + + + tzc_rom1_r1_start + 16 + 31 + + + tzc_rom1_r1_end + 0 + 15 + + + + + + + ef_data_0 + ef_data_0. + 0x40007000 + ef_data_0 + 32 + read-write + + 0 + 0x1000 + registers + + + + ef_cfg_0 + ef_cfg_0. + 0x0 + + + ef_dbg_mode + 28 + 31 + + + ef_dbg_jtag_0_dis + 26 + 27 + + + ef_dbg_jtag_1_dis + 24 + 25 + + + ef_efuse_dbg_dis + 23 + 23 + + + ef_se_dbg_dis + 22 + 22 + + + ef_cpu_rst_dbg_dis + 21 + 21 + + + ef_cpu1_dis + 20 + 20 + + + ef_sf_dis + 19 + 19 + + + ef_cam_dis + 18 + 18 + + + ef_0_key_enc_en + 17 + 17 + + + ef_wifi_dis + 16 + 16 + + + ef_ble_dis + 15 + 15 + + + ef_sdu_dis + 14 + 14 + + + ef_sw_usage_1 + 12 + 13 + + + ef_boot_sel + 8 + 11 + + + ef_cpu0_enc_en + 7 + 7 + + + ef_cpu1_enc_en + 6 + 6 + + + ef_sboot_en + 4 + 5 + + + ef_sboot_sign_mode + 2 + 3 + + + ef_sf_aes_mode + 0 + 1 + + + + + ef_dbg_pwd_low + ef_dbg_pwd_low. + 0x4 + + + ef_dbg_pwd_low + 0 + 31 + + + + + ef_dbg_pwd_high + ef_dbg_pwd_high. + 0x8 + + + ef_dbg_pwd_high + 0 + 31 + + + + + ef_ana_trim_0 + ef_ana_trim_0. + 0xC + + + ef_ana_trim_0 + 0 + 31 + + + + + ef_sw_usage_0 + ef_sw_usage_0. + 0x10 + + + ef_sw_usage_0 + 0 + 31 + + + + + ef_wifi_mac_low + ef_wifi_mac_low. + 0x14 + + + ef_wifi_mac_low + 0 + 31 + + + + + ef_wifi_mac_high + ef_wifi_mac_high. + 0x18 + + + ef_wifi_mac_high + 0 + 31 + + + + + ef_key_slot_0_w0 + ef_key_slot_0_w0. + 0x1C + + + ef_key_slot_0_w0 + 0 + 31 + + + + + ef_key_slot_0_w1 + ef_key_slot_0_w1. + 0x20 + + + ef_key_slot_0_w1 + 0 + 31 + + + + + ef_key_slot_0_w2 + ef_key_slot_0_w2. + 0x24 + + + ef_key_slot_0_w2 + 0 + 31 + + + + + ef_key_slot_0_w3 + ef_key_slot_0_w3. + 0x28 + + + ef_key_slot_0_w3 + 0 + 31 + + + + + ef_key_slot_1_w0 + ef_key_slot_1_w0. + 0x2C + + + ef_key_slot_1_w0 + 0 + 31 + + + + + ef_key_slot_1_w1 + ef_key_slot_1_w1. + 0x30 + + + ef_key_slot_1_w1 + 0 + 31 + + + + + ef_key_slot_1_w2 + ef_key_slot_1_w2. + 0x34 + + + ef_key_slot_1_w2 + 0 + 31 + + + + + ef_key_slot_1_w3 + ef_key_slot_1_w3. + 0x38 + + + ef_key_slot_1_w3 + 0 + 31 + + + + + ef_key_slot_2_w0 + ef_key_slot_2_w0. + 0x3C + + + ef_key_slot_2_w0 + 0 + 31 + + + + + ef_key_slot_2_w1 + ef_key_slot_2_w1. + 0x40 + + + ef_key_slot_2_w1 + 0 + 31 + + + + + ef_key_slot_2_w2 + ef_key_slot_2_w2. + 0x44 + + + ef_key_slot_2_w2 + 0 + 31 + + + + + ef_key_slot_2_w3 + ef_key_slot_2_w3. + 0x48 + + + ef_key_slot_2_w3 + 0 + 31 + + + + + ef_key_slot_3_w0 + ef_key_slot_3_w0. + 0x4C + + + ef_key_slot_3_w0 + 0 + 31 + + + + + ef_key_slot_3_w1 + ef_key_slot_3_w1. + 0x50 + + + ef_key_slot_3_w1 + 0 + 31 + + + + + ef_key_slot_3_w2 + ef_key_slot_3_w2. + 0x54 + + + ef_key_slot_3_w2 + 0 + 31 + + + + + ef_key_slot_3_w3 + ef_key_slot_3_w3. + 0x58 + + + ef_key_slot_3_w3 + 0 + 31 + + + + + ef_key_slot_4_w0 + ef_key_slot_4_w0. + 0x5C + + + ef_key_slot_4_w0 + 0 + 31 + + + + + ef_key_slot_4_w1 + ef_key_slot_4_w1. + 0x60 + + + ef_key_slot_4_w1 + 0 + 31 + + + + + ef_key_slot_4_w2 + ef_key_slot_4_w2. + 0x64 + + + ef_key_slot_4_w2 + 0 + 31 + + + + + ef_key_slot_4_w3 + ef_key_slot_4_w3. + 0x68 + + + ef_key_slot_4_w3 + 0 + 31 + + + + + ef_key_slot_5_w0 + ef_key_slot_5_w0. + 0x6C + + + ef_key_slot_5_w0 + 0 + 31 + + + + + ef_key_slot_5_w1 + ef_key_slot_5_w1. + 0x70 + + + ef_key_slot_5_w1 + 0 + 31 + + + + + ef_key_slot_5_w2 + ef_key_slot_5_w2. + 0x74 + + + ef_key_slot_5_w2 + 0 + 31 + + + + + ef_key_slot_5_w3 + ef_key_slot_5_w3. + 0x78 + + + ef_key_slot_5_w3 + 0 + 31 + + + + + ef_data_0_lock + ef_data_0_lock. + 0x7C + + + rd_lock_key_slot_5 + 31 + 31 + + + rd_lock_key_slot_4 + 30 + 30 + + + rd_lock_key_slot_3 + 29 + 29 + + + rd_lock_key_slot_2 + 28 + 28 + + + rd_lock_key_slot_1 + 27 + 27 + + + rd_lock_key_slot_0 + 26 + 26 + + + rd_lock_dbg_pwd + 25 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reg_key_slot_10_w0 + reg_key_slot_10_w0. + 0xC0 + + + + reg_key_slot_10_w1 + reg_key_slot_10_w1. + 0xC4 + + + + reg_key_slot_10_w2 + reg_key_slot_10_w2. + 0xC8 + + + + reg_key_slot_10_w3 + reg_key_slot_10_w3. + 0xCC + + + + reg_key_slot_11_w0 + reg_key_slot_11_w0. + 0xD0 + + + + reg_key_slot_11_w1 + reg_key_slot_11_w1. + 0xD4 + + + + reg_key_slot_11_w2 + reg_key_slot_11_w2. + 0xD8 + + + + reg_key_slot_11_w3 + reg_key_slot_11_w3. + 0xDC + + + + reg_data_1_lock + reg_data_1_lock. + 0xE0 + + + rd_lock_key_slot_9 + 29 + 29 + + + rd_lock_key_slot_8 + 28 + 28 + + + rd_lock_key_slot_7 + 27 + 27 + + + rd_lock_key_slot_6 + 26 + 26 + + + RESERVED_25_16 + 16 + 25 + + + wr_lock_key_slot_9 + 13 + 13 + + + wr_lock_key_slot_8 + 12 + 12 + + + wr_lock_key_slot_7 + 11 + 11 + + + wr_lock_key_slot_6 + 10 + 10 + + + RESERVED_9_0 + 0 + 9 + + + + + + + ef_ctrl + ef_ctrl. + 0x40007000 + ef_ctrl + 32 + read-write + + 0 + 0x1000 + registers + + + + ef_if_ctrl_0 + ef_if_ctrl_0. + 0x800 + + + ef_if_prot_code_cyc + 24 + 31 + + + ef_if_0_int_set + 22 + 22 + + + ef_if_0_int_clr + 21 + 21 + + + ef_if_0_int + 20 + 20 + + + ef_if_cyc_modify_lock + 19 + 19 + + + ef_if_auto_rd_en + 18 + 18 + + + ef_clk_sahb_data_gate + 17 + 17 + + + ef_if_por_dig + 16 + 16 + + + ef_if_prot_code_ctrl + 8 + 15 + + + ef_clk_sahb_data_sel + 7 + 7 + + + ef_if_0_cyc_modify + 6 + 6 + + + ef_if_0_manual_en + 5 + 5 + + + ef_if_0_trig + 4 + 4 + + + ef_if_0_rw + 3 + 3 + + + ef_if_0_busy + 2 + 2 + + + ef_if_0_autoload_done + 1 + 1 + + + ef_if_0_autoload_p1_done + 0 + 0 + + + + + ef_if_cyc_0 + ef_if_cyc_0. + 0x804 + + + ef_if_cyc_pd_cs_s + 24 + 31 + + + ef_if_cyc_cs + 18 + 23 + + + ef_if_cyc_rd_adr + 12 + 17 + + + ef_if_cyc_rd_dat + 6 + 11 + + + ef_if_cyc_rd_dmy + 0 + 5 + + + + + ef_if_cyc_1 + ef_if_cyc_1. + 0x808 + + + ef_if_cyc_pd_cs_h + 26 + 31 + + + ef_if_cyc_ps_cs + 20 + 25 + + + ef_if_cyc_wr_adr + 14 + 19 + + + ef_if_cyc_pp + 6 + 13 + + + ef_if_cyc_pi + 0 + 5 + + + + + ef_if_0_manual + ef_if_0_manual. + 0x80C + + + ef_if_prot_code_manual + 24 + 31 + + + ef_if_0_q + 16 + 23 + + + ef_if_csb + 15 + 15 + + + ef_if_load + 14 + 14 + + + ef_if_pgenb + 13 + 13 + + + ef_if_strobe + 12 + 12 + + + ef_if_ps + 11 + 11 + + + ef_if_pd + 10 + 10 + + + ef_if_a + 0 + 9 + + + + + ef_if_0_status + ef_if_0_status. + 0x810 + + + ef_if_0_status + 0 + 31 + + + + + ef_if_cfg_0 + ef_if_cfg_0. + 0x814 + + + ef_if_dbg_mode + 28 + 31 + + + ef_if_dbg_jtag_0_dis + 26 + 27 + + + ef_if_dbg_jtag_1_dis + 24 + 25 + + + ef_if_efuse_dbg_dis + 23 + 23 + + + ef_if_se_dbg_dis + 22 + 22 + + + ef_if_cpu_rst_dbg_dis + 21 + 21 + + + ef_if_cpu1_dis + 20 + 20 + + + ef_if_sf_dis + 19 + 19 + + + ef_if_cam_dis + 18 + 18 + + + ef_if_0_key_enc_en + 17 + 17 + + + ef_if_wifi_dis + 16 + 16 + + + ef_if_ble_dis + 15 + 15 + + + ef_if_sdu_dis + 14 + 14 + + + ef_if_sw_usage_1 + 12 + 13 + + + ef_if_boot_sel + 8 + 11 + + + ef_if_cpu0_enc_en + 7 + 7 + + + ef_if_cpu1_enc_en + 6 + 6 + + + ef_if_sboot_en + 4 + 5 + + + ef_if_sboot_sign_mode + 2 + 3 + + + ef_if_sf_aes_mode + 0 + 1 + + + + + ef_sw_cfg_0 + ef_sw_cfg_0. + 0x818 + + + ef_sw_dbg_mode + 28 + 31 + + + ef_sw_dbg_jtag_0_dis + 26 + 27 + + + ef_sw_dbg_jtag_1_dis + 24 + 25 + + + ef_sw_efuse_dbg_dis + 23 + 23 + + + ef_sw_se_dbg_dis + 22 + 22 + + + ef_sw_cpu_rst_dbg_dis + 21 + 21 + + + ef_sw_cpu1_dis + 20 + 20 + + + ef_sw_sf_dis + 19 + 19 + + + ef_sw_cam_dis + 18 + 18 + + + ef_sw_0_key_enc_en + 17 + 17 + + + ef_sw_wifi_dis + 16 + 16 + + + ef_sw_ble_dis + 15 + 15 + + + ef_sw_sdu_dis + 14 + 14 + + + ef_sw_sw_usage_1 + 12 + 13 + + + ef_sw_cpu0_enc_en + 7 + 7 + + + ef_sw_cpu1_enc_en + 6 + 6 + + + ef_sw_sboot_en + 4 + 5 + + + ef_sw_sboot_sign_mode + 2 + 3 + + + ef_sw_sf_aes_mode + 0 + 1 + + + + + ef_reserved + ef_reserved. + 0x81C + + + ef_reserved + 0 + 31 + + + + + ef_if_ana_trim_0 + ef_if_ana_trim_0. + 0x820 + + + ef_if_ana_trim_0 + 0 + 31 + + + + + ef_if_sw_usage_0 + ef_if_sw_usage_0. + 0x824 + + + ef_if_sw_usage_0 + 0 + 31 + + + + + ef_crc_ctrl_0 + ef_crc_ctrl_0. + 0xA00 + + + ef_crc_slp_n + 16 + 31 + + + ef_crc_lock + 11 + 11 + + + ef_crc_int_set + 10 + 10 + + + ef_crc_int_clr + 9 + 9 + + + ef_crc_int + 8 + 8 + + + ef_crc_din_endian + 7 + 7 + + + ef_crc_dout_endian + 6 + 6 + + + ef_crc_dout_inv_en + 5 + 5 + + + ef_crc_error + 4 + 4 + + + ef_crc_mode + 3 + 3 + + + ef_crc_en + 2 + 2 + + + ef_crc_trig + 1 + 1 + + + ef_crc_busy + 0 + 0 + + + + + ef_crc_ctrl_1 + ef_crc_ctrl_1. + 0xA04 + + + ef_crc_data_0_en + 0 + 31 + + + + + ef_crc_ctrl_2 + ef_crc_ctrl_2. + 0xA08 + + + ef_crc_data_1_en + 0 + 31 + + + + + ef_crc_ctrl_3 + ef_crc_ctrl_3. + 0xA0C + + + ef_crc_iv + 0 + 31 + + + + + ef_crc_ctrl_4 + ef_crc_ctrl_4. + 0xA10 + + + ef_crc_golden + 0 + 31 + + + + + ef_crc_ctrl_5 + ef_crc_ctrl_5. + 0xA14 + + + ef_crc_dout + 0 + 31 + + + + + + + cci + cci. + 0x40008000 + cci + 32 + read-write + + 0 + 0x1000 + registers + + + + cci_cfg + cci_cfg. + 0x0 + + + reg_mcci_clk_inv + 9 + 9 + + + reg_scci_clk_inv + 8 + 8 + + + cfg_cci1_pre_read + 7 + 7 + + + reg_div_m_cci_sclk + 5 + 6 + + + reg_m_cci_sclk_en + 4 + 4 + + + cci_mas_hw_mode + 3 + 3 + + + cci_mas_sel_cci2 + 2 + 2 + + + cci_slv_sel_cci2 + 1 + 1 + + + cci_en + 0 + 0 + + + + + cci_addr + cci_addr. + 0x4 + + + apb_cci_addr + 0 + 31 + + + + + cci_wdata + cci_wdata. + 0x8 + + + apb_cci_wdata + 0 + 31 + + + + + cci_rdata + cci_rdata. + 0xC + + + apb_cci_rdata + 0 + 31 + + + + + cci_ctl + cci_ctl. + 0x10 + + + ahb_state + 2 + 3 + + + cci_read_flag + 1 + 1 + + + cci_write_flag + 0 + 0 + + + + + + + l1c + l1c. + 0x40009000 + l1c + 32 + read-write + + 0 + 0x1000 + registers + + + + l1c_config + l1c_config. + 0x0 + + + wrap_dis + 26 + 26 + + + early_resp_dis + 25 + 25 + + + l1c_bmx_busy_option_dis + 24 + 24 + + + l1c_bmx_timeout_en + 20 + 23 + + + l1c_bmx_arb_mode + 16 + 17 + + + l1c_bmx_err_en + 15 + 15 + + + l1c_bypass + 14 + 14 + + + irom_2t_access + 12 + 12 + + + l1c_way_dis + 8 + 11 + + + l1c_invalid_done + 3 + 3 + + + l1c_invalid_en + 2 + 2 + + + l1c_cnt_en + 1 + 1 + + + l1c_cacheable + 0 + 0 + + + + + hit_cnt_lsb + hit_cnt_lsb. + 0x4 + + + hit_cnt_lsb + 0 + 31 + + + + + hit_cnt_msb + hit_cnt_msb. + 0x8 + + + hit_cnt_msb + 0 + 31 + + + + + miss_cnt + miss_cnt. + 0xC + + + miss_cnt + 0 + 31 + + + + + l1c_range + l1c_range. + 0x10 + + + + l1c_bmx_err_addr_en + l1c_bmx_err_addr_en. + 0x200 + + + l1c_hsel_option + 16 + 19 + + + l1c_bmx_err_tz + 5 + 5 + + + l1c_bmx_err_dec + 4 + 4 + + + l1c_bmx_err_addr_dis + 0 + 0 + + + + + l1c_bmx_err_addr + l1c_bmx_err_addr. + 0x204 + + + l1c_bmx_err_addr + 0 + 31 + + + + + irom1_misr_dataout_0 + irom1_misr_dataout_0. + 0x208 + + + irom1_misr_dataout_0 + 0 + 31 + + + + + irom1_misr_dataout_1 + irom1_misr_dataout_1. + 0x20C + + + + cpu_clk_gate + cpu_clk_gate. + 0x210 + + + force_e21_clock_on_2 + 2 + 2 + + + force_e21_clock_on_1 + 1 + 1 + + + force_e21_clock_on_0 + 0 + 0 + + + + + + + uart + uart. + 0x4000A000 + uart + 32 + read-write + + 0 + 0x1000 + registers + + + + utx_config + utx_config. + 0x0 + + + cr_utx_len + 16 + 31 + + + cr_utx_bit_cnt_p + 12 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+ + + urx_rto_timer + urx_rto_timer. + 0x18 + + + cr_urx_rto_value + 0 + 7 + + + + + uart_int_sts + UART interrupt status + 0x20 + + + urx_fer_int + 7 + 7 + + + utx_fer_int + 6 + 6 + + + urx_pce_int + 5 + 5 + + + urx_rto_int + 4 + 4 + + + urx_fifo_int + 3 + 3 + + + utx_fifo_int + 2 + 2 + + + urx_end_int + 1 + 1 + + + utx_end_int + 0 + 0 + + + + + uart_int_mask + UART interrupt mask + 0x24 + + + cr_urx_fer_mask + 7 + 7 + + + cr_utx_fer_mask + 6 + 6 + + + cr_urx_pce_mask + 5 + 5 + + + cr_urx_rto_mask + 4 + 4 + + + cr_urx_fifo_mask + 3 + 3 + + + cr_utx_fifo_mask + 2 + 2 + + + cr_urx_end_mask + 1 + 1 + + + cr_utx_end_mask + 0 + 0 + + + + + uart_int_clear + UART interrupt clear + 0x28 + + + rsvd_7 + 7 + 7 + + + rsvd_6 + 6 + 6 + + + cr_urx_pce_clr + 5 + 5 + + + cr_urx_rto_clr + 4 + 4 + + + rsvd_3 + 3 + 3 + + + rsvd_2 + 2 + 2 + + + cr_urx_end_clr + 1 + 1 + + + cr_utx_end_clr + 0 + 0 + + + + + uart_int_en + UART interrupt enable + 0x2C + + + cr_urx_fer_en + 7 + 7 + + + cr_utx_fer_en + 6 + 6 + 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xtal_capcode_extra_aon + 2 + 2 + + + xtal_bk_aon + 0 + 1 + + + + + tsen + tsen. + 0x888 + + + xtal_rdy_int_sel_aon + 30 + 31 + + + xtal_inn_cfg_en_aon + 29 + 29 + + + xtal_rdy + 28 + 28 + + + tsen_refcode_rfcal + 16 + 27 + + + tsen_refcode_corner + 0 + 11 + + + + + acomp0_ctrl + acomp0_ctrl. + 0x900 + + + acomp0_muxen + 26 + 26 + + + acomp0_pos_sel + 22 + 25 + + + acomp0_neg_sel + 18 + 21 + + + acomp0_level_sel + 12 + 17 + + + acomp0_bias_prog + 10 + 11 + + + acomp0_hyst_selp + 7 + 9 + + + acomp0_hyst_seln + 4 + 6 + + + acomp0_en + 0 + 0 + + + + + acomp1_ctrl + acomp1_ctrl. + 0x904 + + + acomp1_muxen + 26 + 26 + + + acomp1_pos_sel + 22 + 25 + + + acomp1_neg_sel + 18 + 21 + + + acomp1_level_sel + 12 + 17 + + + acomp1_bias_prog + 10 + 11 + + + acomp1_hyst_selp + 7 + 9 + + + acomp1_hyst_seln + 4 + 6 + + + acomp1_en + 0 + 0 + + + + + acomp_ctrl + acomp_ctrl. + 0x908 + + + acomp_reserved + 24 + 31 + + + acomp0_out_raw + 19 + 19 + + + acomp1_out_raw + 17 + 17 + + + acomp0_test_sel + 12 + 13 + + + acomp1_test_sel + 10 + 11 + + + acomp0_test_en + 9 + 9 + + + acomp1_test_en + 8 + 8 + + + acomp0_rstn_ana + 1 + 1 + + + acomp1_rstn_ana + 0 + 0 + + + + + gpadc_reg_cmd + gpadc_reg_cmd. + 0x90C + + + gpadc_sen_test_en + 30 + 30 + + + gpadc_sen_sel + 28 + 29 + + + gpadc_chip_sen_pu + 27 + 27 + + + gpadc_micboost_32db_en + 23 + 23 + + + gpadc_mic_pga2_gain + 21 + 22 + + + gpadc_mic1_diff + 20 + 20 + + + gpadc_mic2_diff + 19 + 19 + + + gpadc_dwa_en + 18 + 18 + + + gpadc_byp_micboost + 16 + 16 + + + gpadc_micpga_en + 15 + 15 + + + gpadc_micbias_en + 14 + 14 + + + gpadc_neg_gnd + 13 + 13 + + + gpadc_pos_sel + 8 + 12 + + + gpadc_neg_sel + 3 + 7 + + + gpadc_soft_rst + 2 + 2 + + + gpadc_conv_start + 1 + 1 + + + gpadc_global_en + 0 + 0 + + + + + gpadc_reg_config1 + gpadc_reg_config1. + 0x910 + + + gpadc_v18_sel + 29 + 30 + + + gpadc_v11_sel + 27 + 28 + + + gpadc_dither_en + 26 + 26 + + + gpadc_scan_en + 25 + 25 + + + gpadc_scan_length + 21 + 24 + + + gpadc_clk_div_ratio + 18 + 20 + + + gpadc_clk_ana_inv + 17 + 17 + + + gpadc_res_sel + 2 + 4 + + + gpadc_cont_conv_en + 1 + 1 + + + gpadc_cal_os_en + 0 + 0 + + + + + gpadc_reg_config2 + gpadc_reg_config2. + 0x914 + + + gpadc_tsvbe_low + 31 + 31 + + + gpadc_dly_sel + 28 + 30 + + + gpadc_pga1_gain + 25 + 27 + + + gpadc_pga2_gain + 22 + 24 + + + gpadc_test_sel + 19 + 21 + + + gpadc_test_en + 18 + 18 + + + gpadc_bias_sel + 17 + 17 + + + gpadc_chop_mode + 15 + 16 + + + gpadc_pga_vcmi_en + 14 + 14 + + + gpadc_pga_en + 13 + 13 + + + gpadc_pga_os_cal + 9 + 12 + + + gpadc_pga_vcm + 7 + 8 + + + gpadc_ts_en + 6 + 6 + + + gpadc_tsext_sel + 5 + 5 + + + gpadc_vbat_en + 4 + 4 + + + gpadc_vref_sel + 3 + 3 + + + gpadc_diff_mode + 2 + 2 + + + + + gpadc_reg_scn_pos1 + adc converation sequence 1 + 0x918 + + + gpadc_scan_pos_5 + 25 + 29 + + + gpadc_scan_pos_4 + 20 + 24 + + + gpadc_scan_pos_3 + 15 + 19 + + + gpadc_scan_pos_2 + 10 + 14 + + + gpadc_scan_pos_1 + 5 + 9 + + + gpadc_scan_pos_0 + 0 + 4 + + + + + gpadc_reg_scn_pos2 + adc converation sequence 2 + 0x91C + + + gpadc_scan_pos_11 + 25 + 29 + + + gpadc_scan_pos_10 + 20 + 24 + + + gpadc_scan_pos_9 + 15 + 19 + + + gpadc_scan_pos_8 + 10 + 14 + + + gpadc_scan_pos_7 + 5 + 9 + + + gpadc_scan_pos_6 + 0 + 4 + + + + + gpadc_reg_scn_neg1 + adc converation sequence 3 + 0x920 + + + gpadc_scan_neg_5 + 25 + 29 + + + gpadc_scan_neg_4 + 20 + 24 + + + gpadc_scan_neg_3 + 15 + 19 + + + gpadc_scan_neg_2 + 10 + 14 + + + gpadc_scan_neg_1 + 5 + 9 + + + gpadc_scan_neg_0 + 0 + 4 + + + + + gpadc_reg_scn_neg2 + adc converation sequence 4 + 0x924 + + + gpadc_scan_neg_11 + 25 + 29 + + + gpadc_scan_neg_10 + 20 + 24 + + + gpadc_scan_neg_9 + 15 + 19 + + + gpadc_scan_neg_8 + 10 + 14 + + + gpadc_scan_neg_7 + 5 + 9 + + + gpadc_scan_neg_6 + 0 + 4 + + + + + gpadc_reg_status + gpadc_reg_status. + 0x928 + + + gpadc_reserved + 16 + 31 + + + gpadc_data_rdy + 0 + 0 + + + + + gpadc_reg_isr + gpadc_reg_isr. + 0x92C + + + gpadc_pos_satur_mask + 9 + 9 + + + gpadc_neg_satur_mask + 8 + 8 + + + gpadc_pos_satur_clr + 5 + 5 + + + gpadc_neg_satur_clr + 4 + 4 + + + gpadc_pos_satur + 1 + 1 + + + gpadc_neg_satur + 0 + 0 + + + + + gpadc_reg_result + gpadc_reg_result. + 0x930 + + + gpadc_data_out + 0 + 25 + + + + + gpadc_reg_raw_result + gpadc_reg_raw_result. + 0x934 + + + gpadc_raw_data + 0 + 11 + + + + + gpadc_reg_define + gpadc_reg_define. + 0x938 + + + gpadc_os_cal_data + 0 + 15 + + + + + hbncore_resv0 + hbncore_resv0. + 0x93C + + + hbncore_resv0_data + 0 + 31 + + + + + hbncore_resv1 + hbncore_resv1. + 0x940 + + + hbncore_resv1_data + 0 + 31 + + + + + + + From 17a12b1d5f517e719996f02bd9172d3016ca8c5a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 22:18:08 -0500 Subject: [PATCH 039/148] bug fix for field iterator --- script/svd2c.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/script/svd2c.py b/script/svd2c.py index 8eaa3d9..906c035 100755 --- a/script/svd2c.py +++ b/script/svd2c.py @@ -23,7 +23,7 @@ r_name = r.find('name').text r_offset = int(r.find('addressOffset').text, 16) Reg(r_name, r_offset + baseAddress) - for f in p.iter('field'): + for f in r.iter('field'): f_name = f.find('name').text lsb = int(f.find('lsb').text) msb = int(f.find('msb').text) From e3d7c8ff1417d257d47c23d4fa49810670cfc76e Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 22:24:09 -0500 Subject: [PATCH 040/148] add phy_hal --- src/bl602_wifi/phy_hal.c | 43 +++++ src/bl602_wifi/phy_hal.h | 3 +- src/include/soc/AON.h | 397 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 441 insertions(+), 2 deletions(-) create mode 100644 src/bl602_wifi/phy_hal.c create mode 100644 src/include/soc/AON.h diff --git a/src/bl602_wifi/phy_hal.c b/src/bl602_wifi/phy_hal.c new file mode 100644 index 0000000..2a7f6ca --- /dev/null +++ b/src/bl602_wifi/phy_hal.c @@ -0,0 +1,43 @@ +#include "phy_hal.h" +#include + +static struct phy_hal_tag hal_env; + +uint8_t hal_get_capcode(void) { + return AON->xtal_cfg.xtal_capcode_in_aon; +} + +void hal_set_capcode(uint32_t capcode) { + /* + AON->xtal_cfg.xtal_capcode_out_aon = capcode; + AON->xtal_cfg.xtal_capcode_in_aon = capcode; + */ + AON->xtal_cfg.value = (capcode & 0x3f) << 0x10 | (capcode & 0x3f) << 0x16 | AON->xtal_cfg.value & 0xf000ffff; +} + +void hal_set_capcode_asymm(uint32_t capcode_in, uint32_t capcode_out) { + /* + AON->xtal_cfg.xtal_capcode_out_aon = capcode_out; + AON->xtal_cfg.xtal_capcode_in_aon = capcode_in; + */ + + AON->xtal_cfg.value = (capcode_out & 0x3f) << 0x10 | (capcode_in & 0x3f) << 0x16 | AON->xtal_cfg.value & 0xf000ffff; +} + +void hal_get_capcode_asymm(uint8_t *capcode_in, uint8_t *capcode_out) { + if (capcode_in) { + *capcode_in = AON->xtal_cfg.xtal_capcode_in_aon; + } + if (capcode_out) { + *capcode_out = AON->xtal_cfg.xtal_capcode_out_aon; + } +} + +bool hal_get_temperature(int16_t *temperature) { + *temperature = hal_env.temperature; +} + +void hal_set_temperature(int16_t temperature) { + hal_env.temperature = temperature; +} + diff --git a/src/bl602_wifi/phy_hal.h b/src/bl602_wifi/phy_hal.h index 71902e5..eee906c 100644 --- a/src/bl602_wifi/phy_hal.h +++ b/src/bl602_wifi/phy_hal.h @@ -1,13 +1,12 @@ #ifndef _PHY_HAL_H_ #define _PHY_HAL_H_ #include + struct phy_hal_tag { int16_t temperature; // +0 uint8_t capcode; // +2 }; // :6:8 -//static struct phy_hal_tag hal_env; // :15:27 - uint8_t hal_get_capcode(void); // :43:9 void hal_set_capcode(uint32_t capcode); // :48:6 void hal_set_capcode_asymm(uint32_t capcode_in, uint32_t capcode_out); // :55:6 diff --git a/src/include/soc/AON.h b/src/include/soc/AON.h new file mode 100644 index 0000000..4089f3b --- /dev/null +++ b/src/include/soc/AON.h @@ -0,0 +1,397 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + uint8_t pad0[0x800]; + union { + uint32_t value; + struct { + uint32_t aon_resv : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 4; + uint32_t pu_aon_dc_tbuf : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad1 : 7; + uint32_t ldo11_rt_pulldown : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ldo11_rt_pulldown_sel : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t sw_pu_ldo11_rt : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad2 : 9; + }; + } aon; // @ 0x800 + union { + uint32_t value; + struct { + uint32_t tmux_aon : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t ten_aon : 1; // @ 4 -- 4 # 0xffffffef + uint32_t dten_xtal32k : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t ten_xtal32k : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad1 : 1; + uint32_t ten_vddcore_aon : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t ten_ldo11soc_aon : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t ten_dcdc18_0_aon : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t ten_dcdc18_1_aon : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t ten_bg_sys_aon : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad2 : 3; + uint32_t ten_ldo15rf_aon : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t ten_xtal_aon : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t dten_xtal_aon : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ten_mbg_aon : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ten_cip_misc_aon : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad3 : 11; + }; + } aon_common; // @ 0x804 + union { + uint32_t value; + struct { + uint32_t sw_soc_en_aon : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sw_wb_en_aon : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; + }; + } aon_misc; // @ 0x808 + uint8_t pad1[0x4]; + union { + uint32_t value; + struct { + uint32_t pmip_resv : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pu_bg_sys_aon : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad0 : 3; + uint32_t bg_sys_start_ctrl_aon : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad1 : 19; + }; + } bg_sys_top; // @ 0x810 + union { + uint32_t value; + struct { + uint32_t pad0 : 1; + uint32_t dcdc18_vout_sel_aon : 5; // @ 5 -- 1 # 0xffffffc1 + uint32_t pad1 : 2; + uint32_t dcdc18_vpfm_aon : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t dcdc18_osc_2m_mode_aon : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad2 : 3; + uint32_t dcdc18_osc_freq_trim_aon : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t dcdc18_slope_curr_sel_aon : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t dcdc18_stop_osc_aon : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t dcdc18_slow_osc_aon : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t dcdc18_osc_inhibit_t2_aon : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t dcdc18_sstart_time_aon : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t pad3 : 1; + uint32_t dcdc18_rdy_aon : 1; // @ 31 -- 31 # 0x7fffffff + }; + } dcdc18_top_0; // @ 0x814 + union { + uint32_t value; + struct { + uint32_t dcdc18_force_cs_zvs_aon : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t dcdc18_cs_delay_aon : 3; // @ 3 -- 1 # 0xfffffff1 + uint32_t dcdc18_zvs_td_opt_aon : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad0 : 1; + uint32_t dcdc18_nonoverlap_td_aon : 5; // @ 12 -- 8 # 0xffffe0ff + uint32_t pad1 : 3; + uint32_t dcdc18_rc_sel_aon : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t dcdc18_chf_sel_aon : 4; // @ 23 -- 20 # 0xff0fffff + uint32_t dcdc18_cfb_sel_aon : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t dcdc18_en_antiring_aon : 1; // @ 28 -- 28 # 0xefffffff + uint32_t dcdc18_pulldown_aon : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad2 : 2; + }; + } dcdc18_top_1; // @ 0x818 + union { + uint32_t value; + struct { + uint32_t pu_ldo11soc_aon : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t ldo11soc_sstart_sel_aon : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t ldo11soc_sstart_delay_aon : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t ldo11soc_pulldown_aon : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t ldo11soc_pulldown_sel_aon : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t ldo11soc_vth_sel_aon : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pad2 : 10; + uint32_t ldo11soc_cc_aon : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad3 : 2; + uint32_t ldo11soc_rdy_aon : 1; // @ 28 -- 28 # 0xefffffff + uint32_t ldo11soc_power_good_aon : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pu_vddcore_misc_aon : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t pmip_dc_tp_out_en_aon : 1; // @ 31 -- 31 # 0x7fffffff + }; + } ldo11soc_and_dctest; // @ 0x81c + union { + uint32_t value; + struct { + uint32_t pu_ir_psw_aon : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } psw_irrcv; // @ 0x820 + uint8_t pad2[0x5c]; + union { + uint32_t value; + struct { + uint32_t pu_mbg_aon : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pu_ldo15rf_aon : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pu_sfreg_aon : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 1; + uint32_t pu_xtal_buf_aon : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pu_xtal_aon : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 2; + uint32_t ldo15rf_sstart_sel_aon : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t ldo15rf_sstart_delay_aon : 2; // @ 10 -- 9 # 0xfffff9ff + uint32_t pad2 : 1; + uint32_t ldo15rf_pulldown_aon : 1; // @ 12 -- 12 # 0xffffefff + uint32_t ldo15rf_pulldown_sel_aon : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad3 : 2; + uint32_t ldo15rf_vout_sel_aon : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad4 : 5; + uint32_t ldo15rf_cc_aon : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad5 : 2; + uint32_t ldo15rf_bypass_aon : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad6 : 3; + }; + } rf_top_aon; // @ 0x880 + union { + uint32_t value; + struct { + uint32_t xtal_bk_aon : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t xtal_capcode_extra_aon : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t xtal_ext_sel_aon : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t xtal_buf_en_aon : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t xtal_buf_hp_aon : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t xtal_fast_startup_aon : 1; // @ 12 -- 12 # 0xffffefff + uint32_t xtal_sleep_aon : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t xtal_amp_ctrl_aon : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t xtal_capcode_out_aon : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t xtal_capcode_in_aon : 6; // @ 27 -- 22 # 0xf03fffff + uint32_t xtal_gm_boost_aon : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t xtal_rdy_sel_aon : 2; // @ 31 -- 30 # 0x3fffffff + }; + } xtal_cfg; // @ 0x884 + union { + uint32_t value; + struct { + uint32_t tsen_refcode_corner : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 4; + uint32_t tsen_refcode_rfcal : 12; // @ 27 -- 16 # 0xf000ffff + uint32_t xtal_rdy : 1; // @ 28 -- 28 # 0xefffffff + uint32_t xtal_inn_cfg_en_aon : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t xtal_rdy_int_sel_aon : 2; // @ 31 -- 30 # 0x3fffffff + }; + } tsen; // @ 0x888 + uint8_t pad3[0x74]; + union { + uint32_t value; + struct { + uint32_t acomp0_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t acomp0_hyst_seln : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t acomp0_hyst_selp : 3; // @ 9 -- 7 # 0xfffffc7f + uint32_t acomp0_bias_prog : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t acomp0_level_sel : 6; // @ 17 -- 12 # 0xfffc0fff + uint32_t acomp0_neg_sel : 4; // @ 21 -- 18 # 0xffc3ffff + uint32_t acomp0_pos_sel : 4; // @ 25 -- 22 # 0xfc3fffff + uint32_t acomp0_muxen : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad1 : 5; + }; + } acomp0_ctrl; // @ 0x900 + union { + uint32_t value; + struct { + uint32_t acomp1_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t acomp1_hyst_seln : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t acomp1_hyst_selp : 3; // @ 9 -- 7 # 0xfffffc7f + uint32_t acomp1_bias_prog : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t acomp1_level_sel : 6; // @ 17 -- 12 # 0xfffc0fff + uint32_t acomp1_neg_sel : 4; // @ 21 -- 18 # 0xffc3ffff + uint32_t acomp1_pos_sel : 4; // @ 25 -- 22 # 0xfc3fffff + uint32_t acomp1_muxen : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad1 : 5; + }; + } acomp1_ctrl; // @ 0x904 + union { + uint32_t value; + struct { + uint32_t acomp1_rstn_ana : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t acomp0_rstn_ana : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 6; + uint32_t acomp1_test_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t acomp0_test_en : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t acomp1_test_sel : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t acomp0_test_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pad1 : 3; + uint32_t acomp1_out_raw : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pad2 : 1; + uint32_t acomp0_out_raw : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pad3 : 4; + uint32_t acomp_reserved : 8; // @ 31 -- 24 # 0xffffff + }; + } acomp_ctrl; // @ 0x908 + union { + uint32_t value; + struct { + uint32_t gpadc_global_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpadc_conv_start : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t gpadc_soft_rst : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t gpadc_neg_sel : 5; // @ 7 -- 3 # 0xffffff07 + uint32_t gpadc_pos_sel : 5; // @ 12 -- 8 # 0xffffe0ff + uint32_t gpadc_neg_gnd : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t gpadc_micbias_en : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t gpadc_micpga_en : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t gpadc_byp_micboost : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 1; + uint32_t gpadc_dwa_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t gpadc_mic2_diff : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t gpadc_mic1_diff : 1; // @ 20 -- 20 # 0xffefffff + uint32_t gpadc_mic_pga2_gain : 2; // @ 22 -- 21 # 0xff9fffff + uint32_t gpadc_micboost_32db_en : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad1 : 3; + uint32_t gpadc_chip_sen_pu : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t gpadc_sen_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t gpadc_sen_test_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t pad2 : 1; + }; + } gpadc_reg_cmd; // @ 0x90c + union { + uint32_t value; + struct { + uint32_t gpadc_cal_os_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpadc_cont_conv_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t gpadc_res_sel : 3; // @ 4 -- 2 # 0xffffffe3 + uint32_t pad0 : 12; + uint32_t gpadc_clk_ana_inv : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t gpadc_clk_div_ratio : 3; // @ 20 -- 18 # 0xffe3ffff + uint32_t gpadc_scan_length : 4; // @ 24 -- 21 # 0xfe1fffff + uint32_t gpadc_scan_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t gpadc_dither_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t gpadc_v11_sel : 2; // @ 28 -- 27 # 0xe7ffffff + uint32_t gpadc_v18_sel : 2; // @ 30 -- 29 # 0x9fffffff + uint32_t pad1 : 1; + }; + } gpadc_reg_config1; // @ 0x910 + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t gpadc_diff_mode : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t gpadc_vref_sel : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t gpadc_vbat_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t gpadc_tsext_sel : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t gpadc_ts_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t gpadc_pga_vcm : 2; // @ 8 -- 7 # 0xfffffe7f + uint32_t gpadc_pga_os_cal : 4; // @ 12 -- 9 # 0xffffe1ff + uint32_t gpadc_pga_en : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t gpadc_pga_vcmi_en : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t gpadc_chop_mode : 2; // @ 16 -- 15 # 0xfffe7fff + uint32_t gpadc_bias_sel : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t gpadc_test_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t gpadc_test_sel : 3; // @ 21 -- 19 # 0xffc7ffff + uint32_t gpadc_pga2_gain : 3; // @ 24 -- 22 # 0xfe3fffff + uint32_t gpadc_pga1_gain : 3; // @ 27 -- 25 # 0xf1ffffff + uint32_t gpadc_dly_sel : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t gpadc_tsvbe_low : 1; // @ 31 -- 31 # 0x7fffffff + }; + } gpadc_reg_config2; // @ 0x914 + union { + uint32_t value; + struct { + uint32_t gpadc_scan_pos_0 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t gpadc_scan_pos_1 : 5; // @ 9 -- 5 # 0xfffffc1f + uint32_t gpadc_scan_pos_2 : 5; // @ 14 -- 10 # 0xffff83ff + uint32_t gpadc_scan_pos_3 : 5; // @ 19 -- 15 # 0xfff07fff + uint32_t gpadc_scan_pos_4 : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t gpadc_scan_pos_5 : 5; // @ 29 -- 25 # 0xc1ffffff + uint32_t pad0 : 2; + }; + } gpadc_reg_scn_pos1; // @ 0x918 + union { + uint32_t value; + struct { + uint32_t gpadc_scan_pos_6 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t gpadc_scan_pos_7 : 5; // @ 9 -- 5 # 0xfffffc1f + uint32_t gpadc_scan_pos_8 : 5; // @ 14 -- 10 # 0xffff83ff + uint32_t gpadc_scan_pos_9 : 5; // @ 19 -- 15 # 0xfff07fff + uint32_t gpadc_scan_pos_10 : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t gpadc_scan_pos_11 : 5; // @ 29 -- 25 # 0xc1ffffff + uint32_t pad0 : 2; + }; + } gpadc_reg_scn_pos2; // @ 0x91c + union { + uint32_t value; + struct { + uint32_t gpadc_scan_neg_0 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t gpadc_scan_neg_1 : 5; // @ 9 -- 5 # 0xfffffc1f + uint32_t gpadc_scan_neg_2 : 5; // @ 14 -- 10 # 0xffff83ff + uint32_t gpadc_scan_neg_3 : 5; // @ 19 -- 15 # 0xfff07fff + uint32_t gpadc_scan_neg_4 : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t gpadc_scan_neg_5 : 5; // @ 29 -- 25 # 0xc1ffffff + uint32_t pad0 : 2; + }; + } gpadc_reg_scn_neg1; // @ 0x920 + union { + uint32_t value; + struct { + uint32_t gpadc_scan_neg_6 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t gpadc_scan_neg_7 : 5; // @ 9 -- 5 # 0xfffffc1f + uint32_t gpadc_scan_neg_8 : 5; // @ 14 -- 10 # 0xffff83ff + uint32_t gpadc_scan_neg_9 : 5; // @ 19 -- 15 # 0xfff07fff + uint32_t gpadc_scan_neg_10 : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t gpadc_scan_neg_11 : 5; // @ 29 -- 25 # 0xc1ffffff + uint32_t pad0 : 2; + }; + } gpadc_reg_scn_neg2; // @ 0x924 + union { + uint32_t value; + struct { + uint32_t gpadc_data_rdy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 15; + uint32_t gpadc_reserved : 16; // @ 31 -- 16 # 0xffff + }; + } gpadc_reg_status; // @ 0x928 + union { + uint32_t value; + struct { + uint32_t gpadc_neg_satur : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpadc_pos_satur : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 2; + uint32_t gpadc_neg_satur_clr : 1; // @ 4 -- 4 # 0xffffffef + uint32_t gpadc_pos_satur_clr : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 2; + uint32_t gpadc_neg_satur_mask : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t gpadc_pos_satur_mask : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad2 : 22; + }; + } gpadc_reg_isr; // @ 0x92c + union { + uint32_t value; + struct { + uint32_t gpadc_data_out : 26; // @ 25 -- 0 # 0xfc000000 + uint32_t pad0 : 6; + }; + } gpadc_reg_result; // @ 0x930 + union { + uint32_t value; + struct { + uint32_t gpadc_raw_data : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 20; + }; + } gpadc_reg_raw_result; // @ 0x934 + union { + uint32_t value; + struct { + uint32_t gpadc_os_cal_data : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } gpadc_reg_define; // @ 0x938 + union { + uint32_t value; + struct { + uint32_t hbncore_resv0_data : 32; // @ 31 -- 0 # 0x0 + }; + } hbncore_resv0; // @ 0x93c + union { + uint32_t value; + struct { + uint32_t hbncore_resv1_data : 32; // @ 31 -- 0 # 0x0 + }; + } hbncore_resv1; // @ 0x940 + }; +} AON_regs; +#define AON_BASE 0x4000f000 +#define AON ((AON_regs* volatile)(AON_BASE)) \ No newline at end of file From da8f1d5786f69af2877ebb7c19b81915771b3919 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sat, 24 Jul 2021 23:21:59 -0500 Subject: [PATCH 041/148] add phy_helper --- src/bl602_wifi/phy_adapt.h | 3 + src/bl602_wifi/phy_helper.c | 134 +++ src/bl602_wifi/phy_helper.h | 39 + src/bl602_wifi/utils.h | 2 + src/include/soc/glb.h | 968 ++++++++++++++++++ src/include/soc/rf.h | 1921 +++++++++++++++++++++++++++++++++++ 6 files changed, 3067 insertions(+) create mode 100644 src/bl602_wifi/phy_helper.c create mode 100644 src/bl602_wifi/phy_helper.h create mode 100644 src/include/soc/glb.h create mode 100644 src/include/soc/rf.h diff --git a/src/bl602_wifi/phy_adapt.h b/src/bl602_wifi/phy_adapt.h index 7fbe645..33e074e 100644 --- a/src/bl602_wifi/phy_adapt.h +++ b/src/bl602_wifi/phy_adapt.h @@ -91,4 +91,7 @@ void pa_input(uint8_t id, struct rx_hd *rhd); int8_t pa_alloc(uint32_t vif_addr); void pa_reset(uint8_t id); void pa_free(uint8_t id); + +float calc_ppm_dsss(uint8_t rxv_freqoff); +float calc_ppm_ofdm(uint16_t rxv_freqoff); #endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_helper.c b/src/bl602_wifi/phy_helper.c new file mode 100644 index 0000000..45a5c1f --- /dev/null +++ b/src/bl602_wifi/phy_helper.c @@ -0,0 +1,134 @@ +#include "phy_helper.h" +#include +#include +#include +#include + +#include "utils.h" + +static char *rc_state_str[8] = { + "RC_IDLE", + "RC_RX2ON", + "RC_TX2ON", + "RC_RXON", + "RC_TX2PAON", + "UNKNOWN", + "UNKNOWN", + "RC_TXPAON", +}; + +static char *rf_state_str[8] = { + "RF_PD", + "RF_SB", + "RF_LO", + "RF_RX", + "RF_TX", + "RF_T2RI", + "RF_R2T", + "RF_MS", +}; + +static struct dump_data_t dump_data_poll[18]; // :86:27 +static uint8_t dump_data_ptr; // :87:16 + +int bl60x_check_mac_status(int * is_ok) { + int ok = 0; + for (int i = 0; i < dump_data_ptr; i++) { + if (dump_data_poll[i].mac_debugRegHWSM2 != 0x8801e000) { + ok = 1; + break; + } + } + * is_ok = ok; +} + +void helper_channel_monitor(uint32_t chanfreq, timer_func_ptr * timer_func, int nrepeats, int mon_time_ms) { + // no code + return ; +} + +void helper_record_all_states(char * func_name) { + int id = dump_data_ptr; + dump_data_poll[id].func_name = func_name; + dump_data_poll[id].time = MAC_CORE->MONOTONIC_COUNTER_2_LO.value; + + helper_record_rc_rf_states(&dump_data_poll[id].rc_state, &dump_data_poll[id].rf_state); + + dump_data_poll[id].mac_debugRegHWSM1 = MAC_CORE->DEBUG_HWSM_1.value; + dump_data_poll[id].mac_debugRegHWSM2 = MAC_CORE->DEBUG_HWSM_2.value; + + MAC_CORE->DEBUG_PORT_SEL.debugPortSel1 = 0x31; + MAC_CORE->DEBUG_PORT_SEL.debugPortSel2 = 0; + + *(uint32_t*)(&dump_data_poll[id].mac_debugPortCoex) = MAC_CORE->DEBUG_PORT_VALUE.value; + + MAC_CORE->DEBUG_PORT_SEL.debugPortSel1 = 0xb; + MAC_CORE->DEBUG_PORT_SEL.debugPortSel2 = 0x2f; + + *(uint32_t*)(&dump_data_poll[id].mac_debugPortMacPhyIf) = MAC_CORE->DEBUG_PORT_VALUE.value; + + SYSCTRL->r074 = 0x33a; + SYSCTRL->diag_conf.diag_sel = 0x14; + + GLB->DBG_SEL_LL.value = 0x4; + GLB->DBG_SEL_LH.value = 0x40000004; + GLB->DBG_SEL_HL.value = 0x80000004; + GLB->DBG_SEL_HH.value = 0xc0000004; + + GLB->debug.debug_oe = 0; + + uint32_t debug = GLB->debug.value; + + dump_data_poll[id].phy_debugPortTDTX = (uint16_t)(debug >> 1); + dump_data_poll[id].phy_debugPortMainFSM = (uint16_t)(debug >> 0x11); + + SYSCTRL->r074 = 0xb09; + + GLB->debug.debug_oe = 0; + debug = GLB->debug.value; + dump_data_poll[id].phy_debugPortDSSSCCK1 = (uint16_t)(debug >> 1); + dump_data_poll[id].phy_debugPortDSSSCCKTx = (uint16_t)(debug >> 0x11); + dump_data_ptr = (dump_data_ptr + 1) & 0xf; +} + +void helper_record_dump(void) { + puts("========= helper_record_dump\r\n"); + for (int i = 0; i < dump_data_ptr; i++) { + struct dump_data_t *data = &dump_data_poll[i]; + printf("[%d] time %ld, func %s\r\n", i, data->time, data->func_name); + printf("MAC: %08lx: rxControlCs %d,txControlCs %d,macControlCs %d\r\n", + data->mac_debugRegHWSM2, + data->mac_debugRegHWSM2 & 0x3f, + data->mac_debugRegHWSM2 >> 8 & 0x1ff, + data->mac_debugRegHWSM2 >> 24 & 0xff + ); + printf("MAC: Coex %04x,Backoff %04x,MPIF %04x,MPIF2 %04x\r\n", + (uint32_t)data->mac_debugPortCoex, + (uint32_t)data->mac_debugPortBackoff, + (uint32_t)data->mac_debugPortMacPhyIf, + (uint32_t)data->mac_debugPortMacPhyIf2 + ); + printf("PHY: MainFSM %04x,TDTX %04x,DSSSCCK1 %04x,DSSSCCKTx %04x\r\n", + (uint32_t)data->phy_debugPortMainFSM, + (uint32_t)data->phy_debugPortTDTX, + (uint32_t)data->phy_debugPortDSSSCCK1, + (uint32_t)data->phy_debugPortDSSSCCKTx + ); + + printf("RFC: RC %s, RF %s\r\n", rc_state_str[data->rc_state], rf_state_str[data->rf_state]); + } + printf("\r\n\r\n"); +} + +void helper_record_rc_rf_states(uint32_t * rc_state, uint32_t * rf_state) { + RF->rfif_dfe_ctrl0.value = RF->rfif_dfe_ctrl0.value & 0xfffffff | 0x10000000; + uint32_t x = RF->rfif_test_read.value; + RF->rfif_dfe_ctrl0.value = RF->rfif_dfe_ctrl0.value & 0xfffffff | 0x20000000; + x = RF->rfif_test_read.value; + *rc_state = x >> 0x1c & 7; + *rf_state = x >> 0x19 & 7; +} + +void helper_record_reset(void) { + dump_data_ptr = 0; +} diff --git a/src/bl602_wifi/phy_helper.h b/src/bl602_wifi/phy_helper.h new file mode 100644 index 0000000..81c9cb2 --- /dev/null +++ b/src/bl602_wifi/phy_helper.h @@ -0,0 +1,39 @@ +#ifndef _PHY_HELPER_H_ +#define _PHY_HELPER_H_ +#include + +typedef long long (*timer_func_ptr)(void*); // :237:21 + +struct HWStateMachineReg { + uint32_t rxControl:6; // +0 + uint32_t reserved_7_6:2; // +0 + uint32_t txControl:9; // +0 + uint32_t reserved_23_17:7; // +0 + uint32_t macControl:8; // +0 +}; // :59:8 + +struct dump_data_t { + uint32_t time; // +0 + const char *func_name; // +4 + uint32_t rc_state; // +8 + uint32_t rf_state; // +12 + uint32_t mac_debugRegHWSM1; // +16 + uint32_t mac_debugRegHWSM2; // +20 + uint16_t mac_debugPortCoex; // +24 + uint16_t mac_debugPortBackoff; // +26 + uint16_t mac_debugPortMacPhyIf; // +28 + uint16_t mac_debugPortMacPhyIf2; // +30 + uint16_t phy_debugPortMainFSM; // +32 + uint16_t phy_debugPortTDTX; // +34 + uint16_t phy_debugPortDSSSCCK1; // +36 + uint16_t phy_debugPortDSSSCCKTx; // +38 +}; // :68:8 + +int bl60x_check_mac_status(int * is_ok); +void helper_channel_monitor(uint32_t chanfreq, timer_func_ptr * timer_func, int nrepeats, int mon_time_ms); +void helper_record_all_states(char * func_name); +void helper_record_dump(void); +void helper_record_rc_rf_states(uint32_t * rc_state, uint32_t * rf_state); +void helper_record_reset(void); + +#endif \ No newline at end of file diff --git a/src/bl602_wifi/utils.h b/src/bl602_wifi/utils.h index fe930e2..68cdca3 100644 --- a/src/bl602_wifi/utils.h +++ b/src/bl602_wifi/utils.h @@ -1,3 +1,5 @@ #ifndef __UTILS_H_ #define ABS(x) (((x) > 0) ? (x) : (-(x))) +int puts(char *s); +int printf(char *fmt,...); #endif \ No newline at end of file diff --git a/src/include/soc/glb.h b/src/include/soc/glb.h new file mode 100644 index 0000000..6fb5e34 --- /dev/null +++ b/src/include/soc/glb.h @@ -0,0 +1,968 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t reg_pll_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_fclk_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_hclk_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t reg_bclk_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t reg_pll_sel : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t hbn_root_clk_sel : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t reg_hclk_div : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t reg_bclk_div : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t fclk_sw_state : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t chip_rdy : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t glb_id : 4; // @ 31 -- 28 # 0xfffffff + }; + } clk_cfg0; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t wifi_mac_core_div : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t wifi_mac_wt_div : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t pad0 : 8; + uint32_t ble_clk_sel : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad1 : 2; + uint32_t ble_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad2 : 7; + }; + } clk_cfg1; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t uart_clk_div : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t uart_clk_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 2; + uint32_t hbn_uart_clk_sel : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t sf_clk_div : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t sf_clk_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t sf_clk_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t sf_clk_sel2 : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t ir_clk_div : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 1; + uint32_t ir_clk_en : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t dma_clk_en : 8; // @ 31 -- 24 # 0xffffff + }; + } clk_cfg2; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t spi_clk_div : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t spi_clk_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 7; + uint32_t i2c_clk_div : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t i2c_clk_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad2 : 7; + }; + } clk_cfg3; // @ 0xc + union { + uint32_t value; + struct { + uint32_t swrst_s00 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t swrst_s01 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 2; + uint32_t swrst_s20 : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t swrst_s30 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad2 : 23; + }; + } swrst_cfg0; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t swrst_s10 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t swrst_s11 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t swrst_s12 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t swrst_s13 : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t swrst_s14 : 1; // @ 4 -- 4 # 0xffffffef + uint32_t swrst_s15 : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t swrst_s16 : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t swrst_s17 : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t swrst_s18 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t swrst_s19 : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t swrst_s1a : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t swrst_s1b : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t swrst_s1c : 1; // @ 12 -- 12 # 0xffffefff + uint32_t swrst_s1d : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t swrst_s1e : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t swrst_s1f : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t swrst_s1a0 : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t swrst_s1a1 : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t swrst_s1a2 : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t swrst_s1a3 : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t swrst_s1a4 : 1; // @ 20 -- 20 # 0xffefffff + uint32_t swrst_s1a5 : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t swrst_s1a6 : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t swrst_s1a7 : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad0 : 8; + }; + } swrst_cfg1; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t reg_ctrl_pwron_rst : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_ctrl_cpu_reset : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_ctrl_sys_reset : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 1; + uint32_t reg_ctrl_reset_dummy : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t pad1 : 16; + uint32_t pka_clk_sel : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad2 : 7; + }; + } swrst_cfg2; // @ 0x18 + uint32_t swrst_cfg3; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t cgen_m : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } cgen_cfg0; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t cgen_s1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t cgen_s1a : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad0 : 8; + }; + } cgen_cfg1; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t cgen_s2 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t cgen_s3 : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 27; + }; + } cgen_cfg2; // @ 0x28 + uint32_t cgen_cfg3; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t irom_mbist_mode : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t hsram_mbist_mode : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tag_mbist_mode : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t ocram_mbist_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t wifi_mbist_mode : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 26; + uint32_t reg_mbist_rst_n : 1; // @ 31 -- 31 # 0x7fffffff + }; + } MBIST_CTL; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t irom_mbist_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t hsram_mbist_done : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tag_mbist_done : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t ocram_mbist_done : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t wifi_mbist_done : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 11; + uint32_t irom_mbist_fail : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t hsram_mbist_fail : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t tag_mbist_fail : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ocram_mbist_fail : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t wifi_mbist_fail : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad1 : 11; + }; + } MBIST_STAT; // @ 0x34 + uint8_t pad0[0x18]; + union { + uint32_t value; + struct { + uint32_t bmx_timeout_en : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t bmx_arb_mode : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad0 : 2; + uint32_t bmx_err_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t bmx_busy_option_dis : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t bmx_gating_dis : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad1 : 1; + uint32_t hsel_option : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t pds_apb_cfg : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t hbn_apb_cfg : 8; // @ 31 -- 24 # 0xffffff + }; + } bmx_cfg1; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t bmx_err_addr_dis : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t bmx_err_dec : 1; // @ 4 -- 4 # 0xffffffef + uint32_t bmx_err_tz : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 22; + uint32_t bmx_dbg_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } bmx_cfg2; // @ 0x54 + union { + uint32_t value; + struct { + uint32_t bmx_err_addr : 32; // @ 31 -- 0 # 0x0 + }; + } bmx_err_addr; // @ 0x58 + union { + uint32_t value; + struct { + uint32_t bmx_dbg_out : 32; // @ 31 -- 0 # 0x0 + }; + } bmx_dbg_out; // @ 0x5c + union { + uint32_t value; + struct { + uint32_t rsvd_31_0 : 32; // @ 31 -- 0 # 0x0 + }; + } rsv0; // @ 0x60 + union { + uint32_t value; + struct { + uint32_t rsvd_31_0 : 32; // @ 31 -- 0 # 0x0 + }; + } rsv1; // @ 0x64 + union { + uint32_t value; + struct { + uint32_t rsvd_31_0 : 32; // @ 31 -- 0 # 0x0 + }; + } rsv2; // @ 0x68 + union { + uint32_t value; + struct { + uint32_t rsvd_31_0 : 32; // @ 31 -- 0 # 0x0 + }; + } rsv3; // @ 0x6c + union { + uint32_t value; + struct { + uint32_t reg_sram_ret : 32; // @ 31 -- 0 # 0x0 + }; + } sram_ret; // @ 0x70 + union { + uint32_t value; + struct { + uint32_t reg_sram_slp : 32; // @ 31 -- 0 # 0x0 + }; + } sram_slp; // @ 0x74 + union { + uint32_t value; + struct { + uint32_t reg_sram_parm : 32; // @ 31 -- 0 # 0x0 + }; + } sram_parm; // @ 0x78 + union { + uint32_t value; + struct { + uint32_t em_sel : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t pad0 : 28; + }; + } seam_misc; // @ 0x7c + union { + uint32_t value; + struct { + uint32_t reg_bd_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_ext_rst_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t jtag_swap_set : 6; // @ 7 -- 2 # 0xffffff03 + uint32_t swap_sflash_io_3_io_0 : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t sel_embedded_sflash : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 2; + uint32_t reg_spi_0_master_mode : 1; // @ 12 -- 12 # 0xffffefff + uint32_t reg_spi_0_swap : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad1 : 1; + uint32_t reg_cci_use_jtag_pin : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t reg_cci_use_sdio_pin : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t p1_adc_test_with_cci : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t p2_dac_test_with_cci : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t p3_cci_use_io_2_5 : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t p4_adc_test_with_jtag : 1; // @ 20 -- 20 # 0xffefffff + uint32_t p5_dac_test_with_jtag : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t p6_sdio_use_io_0_5 : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t p7_jtag_use_io_2_5 : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t uart_swap_set : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad2 : 5; + }; + } glb_parm; // @ 0x80 + uint8_t pad1[0xc]; + union { + uint32_t value; + struct { + uint32_t cpu_rtc_div : 17; // @ 16 -- 0 # 0xfffe0000 + uint32_t pad0 : 1; + uint32_t cpu_rtc_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t cpu_rtc_sel : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t debug_ndreset_gate : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad1 : 11; + }; + } CPU_CLK_CFG; // @ 0x90 + uint8_t pad2[0x10]; + union { + uint32_t value; + struct { + uint32_t gpadc_32m_clk_div : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 1; + uint32_t gpadc_32m_clk_sel : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t gpadc_32m_div_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 23; + }; + } GPADC_32M_SRC_CTRL; // @ 0xa4 + union { + uint32_t value; + struct { + uint32_t dig_32k_div : 11; // @ 10 -- 0 # 0xfffff800 + uint32_t pad0 : 1; + uint32_t dig_32k_en : 1; // @ 12 -- 12 # 0xffffefff + uint32_t dig_32k_comp : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad1 : 2; + uint32_t dig_512k_div : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 1; + uint32_t dig_512k_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t dig_512k_comp : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t pad3 : 2; + uint32_t dig_clk_src_sel : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad4 : 2; + uint32_t reg_en_platform_wakeup : 1; // @ 31 -- 31 # 0x7fffffff + }; + } DIG32K_WAKEUP_CTRL; // @ 0xa8 + union { + uint32_t value; + struct { + uint32_t coex_bt_channel : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t coex_bt_pti : 4; // @ 10 -- 7 # 0xfffff87f + uint32_t coex_bt_bw : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t en_gpio_bt_coex : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad0 : 19; + }; + } WIFI_BT_COEX_CTRL; // @ 0xac + uint8_t pad3[0x10]; + union { + uint32_t value; + struct { + uint32_t uart_sig_0_sel : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t uart_sig_1_sel : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t uart_sig_2_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t uart_sig_3_sel : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t uart_sig_4_sel : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t uart_sig_5_sel : 4; // @ 23 -- 20 # 0xff0fffff + uint32_t uart_sig_6_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t uart_sig_7_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } UART_SIG_SEL_0; // @ 0xc0 + uint8_t pad4[0xc]; + union { + uint32_t value; + struct { + uint32_t reg_dbg_ll_ctrl : 32; // @ 31 -- 0 # 0x0 + }; + } DBG_SEL_LL; // @ 0xd0 + union { + uint32_t value; + struct { + uint32_t reg_dbg_lh_ctrl : 32; // @ 31 -- 0 # 0x0 + }; + } DBG_SEL_LH; // @ 0xd4 + union { + uint32_t value; + struct { + uint32_t reg_dbg_hl_ctrl : 32; // @ 31 -- 0 # 0x0 + }; + } DBG_SEL_HL; // @ 0xd8 + union { + uint32_t value; + struct { + uint32_t reg_dbg_hh_ctrl : 32; // @ 31 -- 0 # 0x0 + }; + } DBG_SEL_HH; // @ 0xdc + union { + uint32_t value; + struct { + uint32_t debug_oe : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t debug_i : 31; // @ 31 -- 1 # 0x1 + }; + } debug; // @ 0xe0 + uint8_t pad5[0x1c]; + union { + uint32_t value; + struct { + uint32_t reg_gpio_0_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_0_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_0_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_0_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_0_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_0_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t real_gpio_0_func_sel : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t reg_gpio_1_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_1_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_1_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_1_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_1_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad1 : 2; + uint32_t reg_gpio_1_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t real_gpio_1_func_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } GPIO_CFGCTL0; // @ 0x100 + union { + uint32_t value; + struct { + uint32_t reg_gpio_2_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_2_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_2_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_2_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_2_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_2_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t real_gpio_2_func_sel : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t reg_gpio_3_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_3_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_3_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_3_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_3_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad1 : 2; + uint32_t reg_gpio_3_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t real_gpio_3_func_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } GPIO_CFGCTL1; // @ 0x104 + union { + uint32_t value; + struct { + uint32_t reg_gpio_4_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_4_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_4_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_4_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_4_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_4_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t real_gpio_4_func_sel : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t reg_gpio_5_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_5_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_5_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_5_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_5_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad1 : 2; + uint32_t reg_gpio_5_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t real_gpio_5_func_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } GPIO_CFGCTL2; // @ 0x108 + union { + uint32_t value; + struct { + uint32_t reg_gpio_6_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_6_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_6_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_6_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_6_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_6_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_7_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_7_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_7_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_7_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_7_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_7_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL3; // @ 0x10c + union { + uint32_t value; + struct { + uint32_t reg_gpio_8_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_8_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_8_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_8_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_8_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_8_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_9_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_9_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_9_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_9_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_9_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_9_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL4; // @ 0x110 + union { + uint32_t value; + struct { + uint32_t reg_gpio_10_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_10_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_10_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_10_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_10_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_10_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_11_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_11_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_11_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_11_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_11_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_11_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL5; // @ 0x114 + union { + uint32_t value; + struct { + uint32_t reg_gpio_12_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_12_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_12_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_12_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_12_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_12_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_13_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_13_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_13_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_13_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_13_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_13_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL6; // @ 0x118 + union { + uint32_t value; + struct { + uint32_t reg_gpio_14_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_14_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_14_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_14_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_14_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_14_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_15_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_15_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_15_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_15_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_15_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_15_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL7; // @ 0x11c + union { + uint32_t value; + struct { + uint32_t reg_gpio_16_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_16_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_16_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_16_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_16_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_16_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_17_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_17_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_17_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_17_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_17_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_17_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL8; // @ 0x120 + union { + uint32_t value; + struct { + uint32_t reg_gpio_18_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_18_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_18_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_18_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_18_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_18_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_19_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_19_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_19_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_19_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_19_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_19_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL9; // @ 0x124 + union { + uint32_t value; + struct { + uint32_t reg_gpio_20_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_20_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_20_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_20_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_20_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_20_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_21_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_21_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_21_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_21_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_21_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t reg_gpio_21_func_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t pad3 : 4; + }; + } GPIO_CFGCTL10; // @ 0x128 + union { + uint32_t value; + struct { + uint32_t reg_gpio_22_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_22_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_22_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_22_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_22_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t reg_gpio_22_func_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t reg_gpio_23_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_23_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_23_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_23_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_23_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 10; + }; + } GPIO_CFGCTL11; // @ 0x12c + union { + uint32_t value; + struct { + uint32_t reg_gpio_24_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_24_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_24_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_24_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_24_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 10; + uint32_t reg_gpio_25_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_25_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_25_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_25_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_25_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad1 : 10; + }; + } GPIO_CFGCTL12; // @ 0x130 + union { + uint32_t value; + struct { + uint32_t reg_gpio_26_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_26_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_26_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_26_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_26_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 10; + uint32_t reg_gpio_27_ie : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_27_smt : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_27_drv : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t reg_gpio_27_pu : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_27_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad1 : 10; + }; + } GPIO_CFGCTL13; // @ 0x134 + union { + uint32_t value; + struct { + uint32_t reg_gpio_28_ie : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_28_smt : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_28_drv : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t reg_gpio_28_pu : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_28_pd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 26; + }; + } GPIO_CFGCTL14; // @ 0x138 + uint8_t pad6[0x44]; + union { + uint32_t value; + struct { + uint32_t reg_gpio_0_i : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_1_i : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_2_i : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t reg_gpio_3_i : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t reg_gpio_4_i : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_5_i : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t reg_gpio_6_i : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t reg_gpio_7_i : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t reg_gpio_8_i : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t reg_gpio_9_i : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t reg_gpio_10_i : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t reg_gpio_11_i : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t reg_gpio_12_i : 1; // @ 12 -- 12 # 0xffffefff + uint32_t reg_gpio_13_i : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t reg_gpio_14_i : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t reg_gpio_15_i : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t reg_gpio_16_i : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_17_i : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_18_i : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t reg_gpio_19_i : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t reg_gpio_20_i : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_21_i : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t reg_gpio_22_i : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad0 : 9; + }; + } GPIO_CFGCTL30; // @ 0x180 + uint32_t GPIO_CFGCTL31; // @ 0x184 + union { + uint32_t value; + struct { + uint32_t reg_gpio_0_o : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_1_o : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_2_o : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t reg_gpio_3_o : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t reg_gpio_4_o : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_5_o : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t reg_gpio_6_o : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t reg_gpio_7_o : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t reg_gpio_8_o : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t reg_gpio_9_o : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t reg_gpio_10_o : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t reg_gpio_11_o : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t reg_gpio_12_o : 1; // @ 12 -- 12 # 0xffffefff + uint32_t reg_gpio_13_o : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t reg_gpio_14_o : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t reg_gpio_15_o : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t reg_gpio_16_o : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_17_o : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_18_o : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t reg_gpio_19_o : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t reg_gpio_20_o : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_21_o : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t reg_gpio_22_o : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad0 : 9; + }; + } GPIO_CFGCTL32; // @ 0x188 + uint32_t GPIO_CFGCTL33; // @ 0x18c + union { + uint32_t value; + struct { + uint32_t reg_gpio_0_oe : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t reg_gpio_1_oe : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t reg_gpio_2_oe : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t reg_gpio_3_oe : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t reg_gpio_4_oe : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_gpio_5_oe : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t reg_gpio_6_oe : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t reg_gpio_7_oe : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t reg_gpio_8_oe : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t reg_gpio_9_oe : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t reg_gpio_10_oe : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t reg_gpio_11_oe : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t reg_gpio_12_oe : 1; // @ 12 -- 12 # 0xffffefff + uint32_t reg_gpio_13_oe : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t reg_gpio_14_oe : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t reg_gpio_15_oe : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t reg_gpio_16_oe : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t reg_gpio_17_oe : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t reg_gpio_18_oe : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t reg_gpio_19_oe : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t reg_gpio_20_oe : 1; // @ 20 -- 20 # 0xffefffff + uint32_t reg_gpio_21_oe : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t reg_gpio_22_oe : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad0 : 9; + }; + } GPIO_CFGCTL34; // @ 0x190 + uint32_t GPIO_CFGCTL35; // @ 0x194 + uint8_t pad7[0x8]; + union { + uint32_t value; + struct { + uint32_t reg_gpio_int_mask1 : 32; // @ 31 -- 0 # 0x0 + }; + } GPIO_INT_MASK1; // @ 0x1a0 + uint8_t pad8[0x4]; + union { + uint32_t value; + struct { + uint32_t gpio_int_stat1 : 32; // @ 31 -- 0 # 0x0 + }; + } GPIO_INT_STAT1; // @ 0x1a8 + uint8_t pad9[0x4]; + union { + uint32_t value; + struct { + uint32_t reg_gpio_int_clr1 : 32; // @ 31 -- 0 # 0x0 + }; + } GPIO_INT_CLR1; // @ 0x1b0 + uint8_t pad10[0xc]; + union { + uint32_t value; + struct { + uint32_t reg_gpio_int_mode_set1 : 32; // @ 31 -- 0 # 0x0 + }; + } GPIO_INT_MODE_SET1; // @ 0x1c0 + union { + uint32_t value; + struct { + uint32_t reg_gpio_int_mode_set2 : 32; // @ 31 -- 0 # 0x0 + }; + } GPIO_INT_MODE_SET2; // @ 0x1c4 + union { + uint32_t value; + struct { + uint32_t reg_gpio_int_mode_set3 : 32; // @ 31 -- 0 # 0x0 + }; + } GPIO_INT_MODE_SET3; // @ 0x1c8 + uint8_t pad11[0x58]; + union { + uint32_t value; + struct { + uint32_t led_din_reg : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t led_din_sel : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t led_din_polarity_sel : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 1; + uint32_t leddrv_ibias : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t ir_rx_gpio_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 21; + uint32_t pu_leddrv : 1; // @ 31 -- 31 # 0x7fffffff + }; + } led_driver; // @ 0x224 + uint8_t pad12[0xe0]; + union { + uint32_t value; + struct { + uint32_t gpdaca_rstn_ana : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpdacb_rstn_ana : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 5; + uint32_t gpdac_test_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t gpdac_ref_sel : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t gpdac_test_sel : 3; // @ 11 -- 9 # 0xfffff1ff + uint32_t pad1 : 12; + uint32_t gpdac_reserved : 8; // @ 31 -- 24 # 0xffffff + }; + } gpdac_ctrl; // @ 0x308 + union { + uint32_t value; + struct { + uint32_t gpdac_a_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpdac_ioa_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 16; + uint32_t gpdac_a_rng : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t gpdac_a_outmux : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad1 : 9; + }; + } gpdac_actrl; // @ 0x30c + union { + uint32_t value; + struct { + uint32_t gpdac_b_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpdac_iob_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 16; + uint32_t gpdac_b_rng : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t gpdac_b_outmux : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad1 : 9; + }; + } gpdac_bctrl; // @ 0x310 + union { + uint32_t value; + struct { + uint32_t gpdac_b_data : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t gpdac_a_data : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 6; + }; + } gpdac_data; // @ 0x314 + uint8_t pad13[0xbe8]; + union { + uint32_t value; + struct { + uint32_t tzc_glb_swrst_s00_lock : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tzc_glb_swrst_s01_lock : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 6; + uint32_t tzc_glb_swrst_s30_lock : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 3; + uint32_t tzc_glb_ctrl_pwron_rst_lock : 1; // @ 12 -- 12 # 0xffffefff + uint32_t tzc_glb_ctrl_cpu_reset_lock : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t tzc_glb_ctrl_sys_reset_lock : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t pad2 : 9; + uint32_t tzc_glb_misc_lock : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t tzc_glb_sram_lock : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t tzc_glb_l2c_lock : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t tzc_glb_bmx_lock : 1; // @ 28 -- 28 # 0xefffffff + uint32_t tzc_glb_dbg_lock : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t tzc_glb_mbist_lock : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t tzc_glb_clk_lock : 1; // @ 31 -- 31 # 0x7fffffff + }; + } tzc_glb_ctrl_0; // @ 0xf00 + union { + uint32_t value; + struct { + uint32_t tzc_glb_swrst_s20_lock : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tzc_glb_swrst_s21_lock : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tzc_glb_swrst_s22_lock : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t tzc_glb_swrst_s23_lock : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t tzc_glb_swrst_s24_lock : 1; // @ 4 -- 4 # 0xffffffef + uint32_t tzc_glb_swrst_s25_lock : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t tzc_glb_swrst_s26_lock : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t tzc_glb_swrst_s27_lock : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t tzc_glb_swrst_s28_lock : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t tzc_glb_swrst_s29_lock : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t tzc_glb_swrst_s2a_lock : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t tzc_glb_swrst_s2b_lock : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t tzc_glb_swrst_s2c_lock : 1; // @ 12 -- 12 # 0xffffefff + uint32_t tzc_glb_swrst_s2d_lock : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t tzc_glb_swrst_s2e_lock : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t tzc_glb_swrst_s2f_lock : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t tzc_glb_swrst_s10_lock : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t tzc_glb_swrst_s11_lock : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t tzc_glb_swrst_s12_lock : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t tzc_glb_swrst_s13_lock : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t tzc_glb_swrst_s14_lock : 1; // @ 20 -- 20 # 0xffefffff + uint32_t tzc_glb_swrst_s15_lock : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t tzc_glb_swrst_s16_lock : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t tzc_glb_swrst_s17_lock : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t tzc_glb_swrst_s18_lock : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t tzc_glb_swrst_s19_lock : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t tzc_glb_swrst_s1a_lock : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t tzc_glb_swrst_s1b_lock : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t tzc_glb_swrst_s1c_lock : 1; // @ 28 -- 28 # 0xefffffff + uint32_t tzc_glb_swrst_s1d_lock : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t tzc_glb_swrst_s1e_lock : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t tzc_glb_swrst_s1f_lock : 1; // @ 31 -- 31 # 0x7fffffff + }; + } tzc_glb_ctrl_1; // @ 0xf04 + union { + uint32_t value; + struct { + uint32_t tzc_glb_gpio_0_lock : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tzc_glb_gpio_1_lock : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tzc_glb_gpio_2_lock : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t tzc_glb_gpio_3_lock : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t tzc_glb_gpio_4_lock : 1; // @ 4 -- 4 # 0xffffffef + uint32_t tzc_glb_gpio_5_lock : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t tzc_glb_gpio_6_lock : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t tzc_glb_gpio_7_lock : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t tzc_glb_gpio_8_lock : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t tzc_glb_gpio_9_lock : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t tzc_glb_gpio_10_lock : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t tzc_glb_gpio_11_lock : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t tzc_glb_gpio_12_lock : 1; // @ 12 -- 12 # 0xffffefff + uint32_t tzc_glb_gpio_13_lock : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t tzc_glb_gpio_14_lock : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t tzc_glb_gpio_15_lock : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t tzc_glb_gpio_16_lock : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t tzc_glb_gpio_17_lock : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t tzc_glb_gpio_18_lock : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t tzc_glb_gpio_19_lock : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t tzc_glb_gpio_20_lock : 1; // @ 20 -- 20 # 0xffefffff + uint32_t tzc_glb_gpio_21_lock : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t tzc_glb_gpio_22_lock : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t tzc_glb_gpio_23_lock : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t tzc_glb_gpio_24_lock : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t tzc_glb_gpio_25_lock : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t tzc_glb_gpio_26_lock : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t tzc_glb_gpio_27_lock : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t tzc_glb_gpio_28_lock : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad0 : 3; + }; + } tzc_glb_ctrl_2; // @ 0xf08 + uint32_t tzc_glb_ctrl_3; // @ 0xf0c + }; +} glb_regs; +#define GLB_BASE 0x40000000 +#define GLB ((glb_regs* volatile)(GLB_BASE)) \ No newline at end of file diff --git a/src/include/soc/rf.h b/src/include/soc/rf.h new file mode 100644 index 0000000..a0061d4 --- /dev/null +++ b/src/include/soc/rf.h @@ -0,0 +1,1921 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t rf_id : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t fw_rev : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t hw_rev : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad0 : 8; + }; + } rf_rev; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t pad0 : 1; + uint32_t rf_fsm_ctrl_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rf_fsm_t2r_cal_mode : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t rf_fsm_state : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t rf_rc_state_dbg : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t rf_rc_state_dbg_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t rf_fsm_st_int_sel : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad2 : 1; + uint32_t rf_fsm_st_int : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad3 : 3; + uint32_t rf_fsm_st_int_clr : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad4 : 3; + uint32_t rf_fsm_st_int_set : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad5 : 3; + uint32_t rf_rc_state_value : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad6 : 1; + }; + } rf_fsm_ctrl_hw; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t rf_fsm_sw_st : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t rf_fsm_sw_st_vld : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 3; + uint32_t full_cal_en : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad2 : 3; + uint32_t inc_cal_timeout : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad3 : 3; + uint32_t lo_unlocked : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad4 : 11; + }; + } rf_fsm_ctrl_sw; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t pu_ctrl_hw : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rx_gain_ctrl_hw : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tx_gain_ctrl_hw : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t lna_ctrl_hw : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t rbb_bw_ctrl_hw : 1; // @ 4 -- 4 # 0xffffffef + uint32_t trxcal_ctrl_hw : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t lo_ctrl_hw : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t inc_acal_ctrl_en_hw : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t inc_fcal_ctrl_en_hw : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t sdm_ctrl_hw : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t rbb_pkdet_en_ctrl_hw : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t rbb_pkdet_out_rstn_ctrl_hw : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t adda_ctrl_hw : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad0 : 19; + }; + } rfctrl_hw_en; // @ 0xc + union { + uint32_t value; + struct { + uint32_t const_acal : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t const_fcal : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t temp_comp_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 15; + }; + } temp_comp; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t rcal_status : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t adc_oscal_status : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t fcal_status : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t acal_status : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t inc_fcal_status : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t inc_acal_status : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t clkpll_cal_status : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t ros_status : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t tos_status : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t rccal_status : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t lo_leakcal_status : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t tiqcal_status_resv : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t riqcal_status_resv : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pwdet_cal_status : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t tenscal_status : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t dpd_status : 2; // @ 31 -- 30 # 0x3fffffff + }; + } rfcal_status; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t dl_rfcal_table_status : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 30; + }; + } rfcal_status2; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t rcal_en_resv : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t adc_oscal_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t dl_rfcal_table_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t fcal_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t acal_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t fcal_inc_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t acal_inc_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t roscal_inc_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t clkpll_cal_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t roscal_en : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t toscal_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t rccal_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t lo_leakcal_en : 1; // @ 12 -- 12 # 0xffffefff + uint32_t tiqcal_en : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t riqcal_en : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pwdet_cal_en : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t tsencal_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t dpd_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pad0 : 14; + }; + } rfcal_ctrlen; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t rcal_sten_resv : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t adc_oscal_sten : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t dl_rfcal_table_sten : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t fcal_sten : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t acal_sten : 1; // @ 4 -- 4 # 0xffffffef + uint32_t inc_fcal_sten : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t inc_acal_sten : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t clkpll_cal_sten : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t roscal_sten : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t toscal_sten_resv : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t rccal_sten : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t lo_leakcal_sten : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t tiqcal_sten : 1; // @ 12 -- 12 # 0xffffefff + uint32_t riqcal_sten : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pwdet_cal_sten : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t tsencal_sten : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t dpd_sten : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 13; + uint32_t rfcal_level : 2; // @ 31 -- 30 # 0x3fffffff + }; + } rfcal_stateen; // @ 0x20 + uint32_t saradc_resv; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t aupll_sdm_rst_dly : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t lo_sdm_rst_dly : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t pad0 : 4; + uint32_t ppu_lead : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pud_vco_dly : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t pud_iref_dly : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pud_pa_dly : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t pad1 : 11; + uint32_t mbg_trim : 2; // @ 28 -- 27 # 0xe7ffffff + uint32_t pad2 : 3; + }; + } rf_base_ctrl1; // @ 0x28 + uint32_t rf_base_ctrl2; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t pu_sfreg : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 7; + uint32_t pu_lna : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pu_rmxgm : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pu_rmx : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pu_rbb : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pu_adda_ldo : 1; // @ 12 -- 12 # 0xffffefff + uint32_t adc_clk_en : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pu_adc : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pu_op_atest : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t pu_pa : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pu_tmx : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pu_tbb : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pu_dac : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pu_vco : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pu_fbdv : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pu_pfd : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pu_osmx : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pu_rxbuf : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pu_txbuf : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t trsw_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad1 : 1; + uint32_t pu_pkdet : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pu_rosdac : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pu_pwrmx : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t pu_tosdac : 1; // @ 31 -- 31 # 0x7fffffff + }; + } pucr1; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t pu_sfreg_hw : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 7; + uint32_t pu_lna_hw : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pu_rmxgm_hw : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pu_rmx_hw : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pu_rbb_hw : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pu_adda_ldo_hw : 1; // @ 12 -- 12 # 0xffffefff + uint32_t adc_clk_en_hw : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pu_adc_hw : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pad1 : 1; + uint32_t pu_pa_hw : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pu_tmx_hw : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pu_tbb_hw : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pu_dac_hw : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pu_vco_hw : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pu_fbdv_hw : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pu_pfd_hw : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pu_osmx_hw : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pu_rxbuf_hw : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pu_txbuf_hw : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t trsw_en_hw : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad2 : 1; + uint32_t pu_pkdet_hw : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pu_rosdac_hw : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad3 : 1; + uint32_t pu_tosdac_hw : 1; // @ 31 -- 31 # 0x7fffffff + }; + } pucr1_hw; // @ 0x34 + uint32_t pucr2; // @ 0x38 + uint32_t pucr2_hw; // @ 0x3c + union { + uint32_t value; + struct { + uint32_t pad0 : 8; + uint32_t ppu_lna_hw : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t ppu_rmxgm_hw : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad1 : 1; + uint32_t ppu_rbb_hw : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad2 : 8; + uint32_t ppu_vco_hw : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ppu_fbdv_hw : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t ppu_pfd_hw : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t ppu_osmx_hw : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t ppu_rxbuf_hw : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t ppu_txbuf_hw : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t pad3 : 6; + }; + } ppu_ctrl_hw; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t pad0 : 20; + uint32_t pud_vco_hw : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad1 : 11; + }; + } pud_ctrl_hw; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t gc_lna : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t gc_rmxgm : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t gc_rbb1 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t gc_rbb2 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t gc_tmx : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad4 : 1; + uint32_t gc_tbb : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t pad5 : 3; + uint32_t gc_tbb_boost : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t pad6 : 2; + }; + } trx_gain1; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t gc_lna_hw : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t gc_rmxgm_hw : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t gc_rbb1_hw : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t gc_rbb2_hw : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t gc_tmx_hw : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad4 : 1; + uint32_t gc_tbb_hw : 5; // @ 24 -- 20 # 0xfe0fffff + uint32_t pad5 : 3; + uint32_t gc_tbb_boost_hw : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t pad6 : 2; + }; + } trx_gain_hw; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t tmux : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t dc_tp_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t dc_tp_clkpll_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 3; + uint32_t ten_clkpll : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t ten_clkpll_sfreg : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad1 : 2; + uint32_t ten_rrf_0 : 1; // @ 12 -- 12 # 0xffffefff + uint32_t ten_rrf_1 : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t ten_pa : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ten_tmx : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t ten_tia : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t ten_bq : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t ten_atest : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ten_tbb : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ten_adc : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ten_dac_i : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t ten_dac_q : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad2 : 1; + uint32_t ten_vco : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t ten_pfdcp : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t ten_lf : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t ten_lodist : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t pad3 : 4; + }; + } ten_dc; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t dten_clkpll_postdiv_clk : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t dten_clkpll_clk96m : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t dten_clkpll_clk32m : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t dten_clkpll_fsdm : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t dten_clkpll_fref : 1; // @ 4 -- 4 # 0xffffffef + uint32_t dten_clkpll_fin : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t dten_lo_fsdm : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad0 : 1; + uint32_t dten_lo_fref : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t dtest_pull_down : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad1 : 13; + uint32_t rf_dtest_en : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad2 : 8; + }; + } ten_dig; // @ 0x54 + union { + uint32_t value; + struct { + uint32_t atest_op_cc : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t atest_dac_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t atest_in_trx_sw : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t atest_in_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad0 : 1; + uint32_t atest_gain_r9 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t atest_gain_r8 : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t atest_gain_r7 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t atest_gain_r6 : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t atest_gain_r5 : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad1 : 1; + uint32_t atest_out_en_q : 1; // @ 20 -- 20 # 0xffefffff + uint32_t atest_out_en_i : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t atest_in_en_q : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t atest_in_en_i : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad2 : 8; + }; + } ten_ac; // @ 0x58 + uint32_t pmip_mv2aon; // @ 0x5c + union { + uint32_t value; + struct { + uint32_t vg11_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t vg13_sel : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t pad0 : 28; + }; + } cip; // @ 0x60 + union { + uint32_t value; + struct { + uint32_t pa_iaq : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pa_etb_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pa_iet : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t pa_vbcore : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pa_vbcas : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pa_half_on : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t pa_ib_fix : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pa_lz_bias_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pa_pwrmx_osdac : 4; // @ 21 -- 18 # 0xffc3ffff + uint32_t pa_pwrmx_dac_pn_switch : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad0 : 1; + uint32_t pa_pwrmx_bm : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad1 : 1; + uint32_t pa_att_gc : 4; // @ 31 -- 28 # 0xfffffff + }; + } pa1; // @ 0x64 + union { + uint32_t value; + struct { + uint32_t pad0 : 3; + uint32_t pa_etb_en_hw : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pa_iet_hw : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t pa_vbcore_hw : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pa_vbcas_hw : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad1 : 1; + uint32_t pa_half_on_hw : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pa_ib_fix_hw : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pad2 : 14; + }; + } pa2; // @ 0x68 + union { + uint32_t value; + struct { + uint32_t tmx_cs : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t tmx_bm_sw : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t tmx_bm_cas : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad2 : 1; + uint32_t tmx_bm_cas_bulk : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t tx_tsense_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 15; + }; + } tmx; // @ 0x6c + union { + uint32_t value; + struct { + uint32_t tbb_bm_sf : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t tbb_bm_cg : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t tbb_vcm : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t tbb_cflt : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t tbb_iq_bias_short : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t tbb_atest_out_en : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t tbb_tosdac_q : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad3 : 2; + uint32_t tbb_tosdac_i : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad4 : 2; + }; + } tbb; // @ 0x70 + union { + uint32_t value; + struct { + uint32_t lna_bm : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t lna_bm_hw : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t lna_load_csw : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t lna_load_csw_hw : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t lna_rfb_match : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad0 : 1; + uint32_t lna_cap_lg : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t pad1 : 2; + uint32_t lna_lg_gsel : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad2 : 5; + }; + } lna; // @ 0x74 + union { + uint32_t value; + struct { + uint32_t rmx_bm : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t rmxgm_bm : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t rmxgm_10m_mode_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad2 : 23; + }; + } rmxgm; // @ 0x78 + union { + uint32_t value; + struct { + uint32_t rosdac_q : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t rosdac_i : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t rosdac_q_hw : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t rosdac_i_hw : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 1; + uint32_t rosdac_range : 1; // @ 31 -- 31 # 0x7fffffff + }; + } rbb1; // @ 0x7c + union { + uint32_t value; + struct { + uint32_t rbb_cap2_fc_q : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t rbb_cap2_fc_i : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t rbb_cap1_fc_q : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t rbb_cap1_fc_i : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } rbb2; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t rbb_bt_mode_hw : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t rbb_bt_mode : 1; // @ 4 -- 4 # 0xffffffef + uint32_t rbb_bt_fif_tune : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t pad1 : 1; + uint32_t rbb_deq : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t rbb_bm_op : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t rbb_vcm : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad4 : 2; + uint32_t rbb_bq_iqbias_short : 1; // @ 20 -- 20 # 0xffefffff + uint32_t rbb_tia_iqbias_short : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad5 : 2; + uint32_t rbb_bw : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 2; + uint32_t rxiqcal_en : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad7 : 2; + uint32_t pwr_det_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } rbb3; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t rbb_pkdet_vth : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t rbb_pkdet_out_rstn : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 3; + uint32_t rbb_pkdet_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 3; + uint32_t rbb_pkdet_out_rstn_hw : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad2 : 3; + uint32_t rbb_pkdet_en_hw : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad3 : 3; + uint32_t pkdet_out_raw : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad4 : 3; + uint32_t pkdet_out_latch : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad5 : 7; + }; + } rbb4; // @ 0x88 + union { + uint32_t value; + struct { + uint32_t dac_dvdd_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t dac_bias_sel : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t dac_clk_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t dac_rccalsel : 1; // @ 12 -- 12 # 0xffffefff + uint32_t dac_clk_sync_inv : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad3 : 2; + uint32_t adda_ldo_byps : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 3; + uint32_t adda_ldo_dvdd_sel : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t adda_ldo_dvdd_sel_hw : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad6 : 5; + }; + } adda1; // @ 0x8c + union { + uint32_t value; + struct { + uint32_t adc_vref_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t adc_dly_ctl : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t adc_dvdd_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t adc_sar_ascal_en : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad3 : 3; + uint32_t adc_gt_rm : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 3; + uint32_t adc_clk_sync_inv : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad5 : 3; + uint32_t adc_clk_inv : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad6 : 3; + uint32_t adc_clk_div_sel : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad7 : 3; + }; + } adda2; // @ 0x90 + uint8_t pad0[0xc]; + union { + uint32_t value; + struct { + uint32_t lo_vco_freq_cw : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t lo_vco_freq_cw_hw : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad0 : 3; + uint32_t lo_vco_idac_cw_hw : 5; // @ 28 -- 24 # 0xe0ffffff + uint32_t pad1 : 3; + }; + } vco1; // @ 0xa0 + union { + uint32_t value; + struct { + uint32_t lo_vco_vbias_cw : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t lo_vco_idac_boot : 1; // @ 4 -- 4 # 0xffffffef + uint32_t lo_vco_short_vbias_filter : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t lo_vco_short_idac_filter : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad1 : 1; + uint32_t acal_vref_cw : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad2 : 1; + uint32_t acal_vco_ud : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad3 : 3; + uint32_t acal_inc_en_hw : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 15; + }; + } vco2; // @ 0xa4 + union { + uint32_t value; + struct { + uint32_t fcal_div : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t fcal_cnt_op : 16; // @ 31 -- 16 # 0xffff + }; + } vco3; // @ 0xa8 + union { + uint32_t value; + struct { + uint32_t pad0 : 4; + uint32_t fcal_cnt_start : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t fcal_inc_en_hw : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad2 : 7; + uint32_t fcal_inc_large_range : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad3 : 3; + uint32_t fcal_cnt_rdy : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad4 : 3; + uint32_t fcal_inc_vctrl_ud : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad5 : 6; + }; + } vco4; // @ 0xac + union { + uint32_t value; + struct { + uint32_t lo_cp_sel : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t lo_cp_sel_hw : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t lo_cp_startup_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad2 : 3; + uint32_t lo_cp_ota_en : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad3 : 3; + uint32_t lo_cp_opamp_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 3; + uint32_t lo_cp_hiz : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad5 : 3; + uint32_t lo_pfd_rvdd_boost : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad6 : 3; + uint32_t lo_pfd_rst_csd : 1; // @ 28 -- 28 # 0xefffffff + uint32_t lo_pfd_rst_csd_hw : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad7 : 2; + }; + } pfdcp; // @ 0xb0 + union { + uint32_t value; + struct { + uint32_t lo_lf_rz_hw : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t lo_lf_r4_hw : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t lo_lf_cz_hw : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t lo_lf_rz : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t lo_lf_cz : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t lo_lf_r4 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t lo_lf_r4_short : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad3 : 1; + uint32_t lo_slipped_dn : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad4 : 3; + uint32_t lo_slipped_up : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad5 : 7; + }; + } lo; // @ 0xb4 + union { + uint32_t value; + struct { + uint32_t lo_fbdv_halfstep_en_hw : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t lo_fbdv_halfstep_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t lo_fbdv_sel_sample_clk : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t lo_fbdv_sel_fb_clk : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pad3 : 2; + uint32_t lo_fbdv_rst : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad4 : 3; + uint32_t lo_fbdv_rst_hw : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad5 : 11; + }; + } fbdv; // @ 0xb8 + union { + uint32_t value; + struct { + uint32_t lo_osmx_xgm_boost : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t lo_osmx_en_xgm : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t lo_osmx_fix_cap : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad2 : 3; + uint32_t lo_osmx_vbuf_stre : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad3 : 3; + uint32_t lo_osmx_capbank_bias : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad4 : 2; + uint32_t lo_osmx_cap : 4; // @ 23 -- 20 # 0xff0fffff + uint32_t lo_lodist_txbuf_stre : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad5 : 3; + uint32_t lo_lodist_rxbuf_stre : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad6 : 3; + }; + } lodist; // @ 0xbc + union { + uint32_t value; + struct { + uint32_t lo_sdm_dither_sel_hw : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t lo_sdm_bypass_hw : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad1 : 3; + uint32_t lo_sdm_dither_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t lo_sdm_bypass : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad3 : 3; + uint32_t lo_sdm_rstb : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t lo_sdm_rstb_hw : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pad4 : 2; + uint32_t lo_sdm_flag : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad5 : 11; + }; + } sdm1; // @ 0xc0 + union { + uint32_t value; + struct { + uint32_t lo_sdmin : 30; // @ 29 -- 0 # 0xc0000000 + uint32_t pad0 : 2; + }; + } sdm2; // @ 0xc4 + union { + uint32_t value; + struct { + uint32_t lo_sdmin_hw : 30; // @ 29 -- 0 # 0xc0000000 + uint32_t pad0 : 2; + }; + } sdm3; // @ 0xc8 + uint8_t pad1[0x20]; + union { + uint32_t value; + struct { + uint32_t rf_reserved0 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_resv_reg_0; // @ 0xec + union { + uint32_t value; + struct { + uint32_t rf_reserved1 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_resv_reg_1; // @ 0xf0 + union { + uint32_t value; + struct { + uint32_t rf_reserved2 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_resv_reg_2; // @ 0xf4 + union { + uint32_t value; + struct { + uint32_t gain_ctrl0_gc_rmxgm : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t gain_ctrl0_gc_lna : 3; // @ 4 -- 2 # 0xffffffe3 + uint32_t gain_ctrl1_gc_rmxgm : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t gain_ctrl1_gc_lna : 3; // @ 9 -- 7 # 0xfffffc7f + uint32_t gain_ctrl2_gc_rmxgm : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t gain_ctrl2_gc_lna : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t gain_ctrl3_gc_rmxgm : 2; // @ 16 -- 15 # 0xfffe7fff + uint32_t gain_ctrl3_gc_lna : 3; // @ 19 -- 17 # 0xfff1ffff + uint32_t gain_ctrl4_gc_rmxgm : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t gain_ctrl4_gc_lna : 3; // @ 24 -- 22 # 0xfe3fffff + uint32_t gain_ctrl5_gc_rmxgm : 2; // @ 26 -- 25 # 0xf9ffffff + uint32_t gain_ctrl5_gc_lna : 3; // @ 29 -- 27 # 0xc7ffffff + uint32_t pad0 : 2; + }; + } rrf_gain_index1; // @ 0xf8 + union { + uint32_t value; + struct { + uint32_t gain_ctrl8_gc_rmxgm : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t gain_ctrl8_gc_lna : 3; // @ 4 -- 2 # 0xffffffe3 + uint32_t gain_ctrl7_gc_rmxgm : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t gain_ctrl7_gc_lna : 3; // @ 9 -- 7 # 0xfffffc7f + uint32_t gain_ctrl6_gc_rmxgm : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t gain_ctrl6_gc_lna : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad0 : 17; + }; + } rrf_gain_index2; // @ 0xfc + union { + uint32_t value; + struct { + uint32_t lna_bm_hg : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t lna_bm_lg : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t lna_load_csw_hg : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t lna_load_csw_lg : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t pad0 : 16; + }; + } lna_ctrl_hw_mux; // @ 0x100 + union { + uint32_t value; + struct { + uint32_t gain_ctrl0_gc_rbb1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t gain_ctrl0_gc_rbb2 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t gain_ctrl1_gc_rbb1 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t gain_ctrl1_gc_rbb2 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t gain_ctrl2_gc_rbb1 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad4 : 2; + uint32_t gain_ctrl2_gc_rbb2 : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t gain_ctrl3_gc_rbb1 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 2; + uint32_t gain_ctrl3_gc_rbb2 : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad7 : 1; + }; + } rbb_gain_index1; // @ 0x104 + union { + uint32_t value; + struct { + uint32_t gain_ctrl4_gc_rbb1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t gain_ctrl4_gc_rbb2 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t gain_ctrl5_gc_rbb1 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t gain_ctrl5_gc_rbb2 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t gain_ctrl6_gc_rbb1 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad4 : 2; + uint32_t gain_ctrl6_gc_rbb2 : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t gain_ctrl7_gc_rbb1 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 2; + uint32_t gain_ctrl7_gc_rbb2 : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad7 : 1; + }; + } rbb_gain_index2; // @ 0x108 + union { + uint32_t value; + struct { + uint32_t gain_ctrl8_gc_rbb1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t gain_ctrl8_gc_rbb2 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t gain_ctrl9_gc_rbb1 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t gain_ctrl9_gc_rbb2 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t gain_ctrl10_gc_rbb1 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad4 : 2; + uint32_t gain_ctrl10_gc_rbb2 : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t gain_ctrl11_gc_rbb1 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 2; + uint32_t gain_ctrl11_gc_rbb2 : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad7 : 1; + }; + } rbb_gain_index3; // @ 0x10c + union { + uint32_t value; + struct { + uint32_t gain_ctrl12_gc_rbb1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t gain_ctrl12_gc_rbb2 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t gain_ctrl13_gc_rbb1 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad2 : 2; + uint32_t gain_ctrl13_gc_rbb2 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t gain_ctrl14_gc_rbb1 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad4 : 2; + uint32_t gain_ctrl14_gc_rbb2 : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t gain_ctrl15_gc_rbb1 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad6 : 2; + uint32_t gain_ctrl15_gc_rbb2 : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad7 : 1; + }; + } rbb_gain_index4; // @ 0x110 + union { + uint32_t value; + struct { + uint32_t gain_ctrl16_gc_rbb1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 2; + uint32_t gain_ctrl16_gc_rbb2 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 25; + }; + } rbb_gain_index5; // @ 0x114 + union { + uint32_t value; + struct { + uint32_t gain_ctrl0_gc_tbb : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t gain_ctrl0_gc_tmx : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad1 : 1; + uint32_t gain_ctrl0_dac_bias_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t gain_ctrl0_gc_tbb_boost : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t gain_ctrl1_gc_tbb : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad2 : 3; + uint32_t gain_ctrl1_gc_tmx : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad3 : 1; + uint32_t gain_ctrl1_dac_bias_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t gain_ctrl1_gc_tbb_boost : 2; // @ 31 -- 30 # 0x3fffffff + }; + } tbb_gain_index1; // @ 0x118 + union { + uint32_t value; + struct { + uint32_t gain_ctrl2_gc_tbb : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t gain_ctrl2_gc_tmx : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad1 : 1; + uint32_t gain_ctrl2_dac_bias_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t gain_ctrl2_gc_tbb_boost : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t gain_ctrl3_gc_tbb : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad2 : 3; + uint32_t gain_ctrl3_gc_tmx : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad3 : 1; + uint32_t gain_ctrl3_dac_bias_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t gain_ctrl3_gc_tbb_boost : 2; // @ 31 -- 30 # 0x3fffffff + }; + } tbb_gain_index2; // @ 0x11c + union { + uint32_t value; + struct { + uint32_t gain_ctrl4_gc_tbb : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t gain_ctrl4_gc_tmx : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad1 : 1; + uint32_t gain_ctrl4_dac_bias_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t gain_ctrl4_gc_tbb_boost : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t gain_ctrl5_gc_tbb : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad2 : 3; + uint32_t gain_ctrl5_gc_tmx : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad3 : 1; + uint32_t gain_ctrl5_dac_bias_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t gain_ctrl5_gc_tbb_boost : 2; // @ 31 -- 30 # 0x3fffffff + }; + } tbb_gain_index3; // @ 0x120 + union { + uint32_t value; + struct { + uint32_t gain_ctrl6_gc_tbb : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t gain_ctrl6_gc_tmx : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad1 : 1; + uint32_t gain_ctrl6_dac_bias_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t gain_ctrl6_gc_tbb_boost : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t gain_ctrl7_gc_tbb : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad2 : 3; + uint32_t gain_ctrl7_gc_tmx : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad3 : 1; + uint32_t gain_ctrl7_dac_bias_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t gain_ctrl7_gc_tbb_boost : 2; // @ 31 -- 30 # 0x3fffffff + }; + } tbb_gain_index4; // @ 0x124 + union { + uint32_t value; + struct { + uint32_t pad0 : 12; + uint32_t pa_iet_11n : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t pa_vbcore_11n : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t pa_vbcas_11n : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad1 : 9; + }; + } pa_reg_ctrl_hw1; // @ 0x128 + union { + uint32_t value; + struct { + uint32_t pa_iet_11g : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t pa_vbcore_11g : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t pa_vbcas_11g : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad0 : 1; + uint32_t pa_iet_11b : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t pa_vbcore_11b : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t pa_vbcas_11b : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad1 : 9; + }; + } pa_reg_ctrl_hw2; // @ 0x12c + union { + uint32_t value; + struct { + uint32_t pa_half_on_wifi : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 7; + uint32_t pa_etb_en_wifi : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 7; + uint32_t pa_ib_fix_wifi : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 15; + }; + } pa_reg_wifi_ctrl_hw; // @ 0x130 + union { + uint32_t value; + struct { + uint32_t adda_ldo_dvdd_sel_rx : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t adda_ldo_dvdd_sel_tx : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 25; + }; + } adda_reg_ctrl_hw; // @ 0x134 + union { + uint32_t value; + struct { + uint32_t lo_fbdv_halfstep_en_rx : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t lo_fbdv_halfstep_en_tx : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t lo_cp_sel_rx : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t lo_cp_sel_tx : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t lo_lf_cz_rx : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad0 : 2; + uint32_t lo_lf_cz_tx : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 2; + uint32_t lo_lf_rz_rx : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pad2 : 2; + uint32_t lo_lf_rz_tx : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad3 : 2; + uint32_t lo_lf_r4_rx : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t pad4 : 2; + uint32_t lo_lf_r4_tx : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad5 : 6; + }; + } lo_reg_ctrl_hw1; // @ 0x138 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2404 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2404 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2408 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2408 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw1; // @ 0x13c + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2412 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2412 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2416 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2416 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw2; // @ 0x140 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2420 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2420 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2424 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2424 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw3; // @ 0x144 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2428 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2428 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2432 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2432 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw4; // @ 0x148 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2436 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2436 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2440 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2440 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw5; // @ 0x14c + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2444 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2444 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2448 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2448 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw6; // @ 0x150 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2452 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2452 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2456 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2456 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw7; // @ 0x154 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2460 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2460 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2464 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2464 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw8; // @ 0x158 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2468 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2468 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2472 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2472 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw9; // @ 0x15c + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2476 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2476 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t lo_vco_idac_cw_2480 : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 3; + uint32_t lo_vco_freq_cw_2480 : 8; // @ 31 -- 24 # 0xffffff + }; + } lo_cal_ctrl_hw10; // @ 0x160 + union { + uint32_t value; + struct { + uint32_t lo_vco_idac_cw_2484 : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 3; + uint32_t lo_vco_freq_cw_2484 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t pad1 : 16; + }; + } lo_cal_ctrl_hw11; // @ 0x164 + union { + uint32_t value; + struct { + uint32_t rosdac_i_gc0 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t rosdac_q_gc0 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t rosdac_i_gc1 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t rosdac_q_gc1 : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } rosdac_ctrl_hw1; // @ 0x168 + union { + uint32_t value; + struct { + uint32_t rosdac_i_gc2 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t rosdac_q_gc2 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t rosdac_i_gc3 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t rosdac_q_gc3 : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } rosdac_ctrl_hw2; // @ 0x16c + union { + uint32_t value; + struct { + uint32_t rx_iq_phase_comp_gc0 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t rx_iq_gain_comp_gc0 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } rxiq_ctrl_hw1; // @ 0x170 + union { + uint32_t value; + struct { + uint32_t rx_iq_phase_comp_gc1 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t rx_iq_gain_comp_gc1 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } rxiq_ctrl_hw2; // @ 0x174 + union { + uint32_t value; + struct { + uint32_t rx_iq_phase_comp_gc2 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t rx_iq_gain_comp_gc2 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } rxiq_ctrl_hw3; // @ 0x178 + union { + uint32_t value; + struct { + uint32_t rx_iq_phase_comp_gc3 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t rx_iq_gain_comp_gc3 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } rxiq_ctrl_hw4; // @ 0x17c + union { + uint32_t value; + struct { + uint32_t tbb_tosdac_i_gc0 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t tbb_tosdac_q_gc0 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t tbb_tosdac_i_gc1 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t tbb_tosdac_q_gc1 : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } tosdac_ctrl_hw1; // @ 0x180 + union { + uint32_t value; + struct { + uint32_t tbb_tosdac_i_gc2 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t tbb_tosdac_q_gc2 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t tbb_tosdac_i_gc3 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t tbb_tosdac_q_gc3 : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } tosdac_ctrl_hw2; // @ 0x184 + union { + uint32_t value; + struct { + uint32_t tbb_tosdac_i_gc4 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t tbb_tosdac_q_gc4 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t tbb_tosdac_i_gc5 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t tbb_tosdac_q_gc5 : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } tosdac_ctrl_hw3; // @ 0x188 + union { + uint32_t value; + struct { + uint32_t tbb_tosdac_i_gc6 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t tbb_tosdac_q_gc6 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t tbb_tosdac_i_gc7 : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t pad2 : 2; + uint32_t tbb_tosdac_q_gc7 : 6; // @ 29 -- 24 # 0xc0ffffff + uint32_t pad3 : 2; + }; + } tosdac_ctrl_hw4; // @ 0x18c + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc0 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc0 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw0; // @ 0x190 + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc1 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc1 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw1; // @ 0x194 + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc2 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc2 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw2; // @ 0x198 + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc3 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc3 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw3; // @ 0x19c + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc4 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc4 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw4; // @ 0x1a0 + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc5 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc5 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw5; // @ 0x1a4 + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc6 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc6 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw6; // @ 0x1a8 + union { + uint32_t value; + struct { + uint32_t tx_iq_phase_comp_gc7 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t tx_iq_gain_comp_gc7 : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } tx_iq_gain_hw7; // @ 0x1ac + union { + uint32_t value; + struct { + uint32_t lo_sdm_dither_sel_wlan_2412 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t lo_sdm_dither_sel_wlan_2417 : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t lo_sdm_dither_sel_wlan_2422 : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t lo_sdm_dither_sel_wlan_2427 : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t lo_sdm_dither_sel_wlan_2432 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t lo_sdm_dither_sel_wlan_2437 : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t lo_sdm_dither_sel_wlan_2442 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t lo_sdm_dither_sel_wlan_2447 : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t lo_sdm_dither_sel_wlan_2452 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t lo_sdm_dither_sel_wlan_2457 : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t lo_sdm_dither_sel_wlan_2462 : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t lo_sdm_dither_sel_wlan_2467 : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t lo_sdm_dither_sel_wlan_2472 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t lo_sdm_dither_sel_wlan_2484 : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t pad0 : 4; + }; + } lo_sdm_ctrl_hw1; // @ 0x1b0 + union { + uint32_t value; + struct { + uint32_t lo_sdm_dither_sel_ble_2402 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t lo_sdm_dither_sel_ble_2404 : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t lo_sdm_dither_sel_ble_2406 : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t lo_sdm_dither_sel_ble_2408 : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t lo_sdm_dither_sel_ble_2410 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t lo_sdm_dither_sel_ble_2412 : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t lo_sdm_dither_sel_ble_2414 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t lo_sdm_dither_sel_ble_2416 : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t lo_sdm_dither_sel_ble_2418 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t lo_sdm_dither_sel_ble_2420 : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t lo_sdm_dither_sel_ble_2422 : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t lo_sdm_dither_sel_ble_2424 : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t lo_sdm_dither_sel_ble_2426 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t lo_sdm_dither_sel_ble_2428 : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t lo_sdm_dither_sel_ble_2430 : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t lo_sdm_dither_sel_ble_2432 : 2; // @ 31 -- 30 # 0x3fffffff + }; + } lo_sdm_ctrl_hw2; // @ 0x1b4 + union { + uint32_t value; + struct { + uint32_t lo_sdm_dither_sel_ble_2434 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t lo_sdm_dither_sel_ble_2436 : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t lo_sdm_dither_sel_ble_2438 : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t lo_sdm_dither_sel_ble_2440 : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t lo_sdm_dither_sel_ble_2442 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t lo_sdm_dither_sel_ble_2444 : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t lo_sdm_dither_sel_ble_2446 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t lo_sdm_dither_sel_ble_2448 : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t lo_sdm_dither_sel_ble_2450 : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t lo_sdm_dither_sel_ble_2452 : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t lo_sdm_dither_sel_ble_2454 : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t lo_sdm_dither_sel_ble_2456 : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t lo_sdm_dither_sel_ble_2458 : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t lo_sdm_dither_sel_ble_2460 : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t lo_sdm_dither_sel_ble_2462 : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t lo_sdm_dither_sel_ble_2464 : 2; // @ 31 -- 30 # 0x3fffffff + }; + } lo_sdm_ctrl_hw3; // @ 0x1b8 + union { + uint32_t value; + struct { + uint32_t lo_sdm_dither_sel_ble_2466 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t lo_sdm_dither_sel_ble_2468 : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t lo_sdm_dither_sel_ble_2470 : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t lo_sdm_dither_sel_ble_2472 : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t lo_sdm_dither_sel_ble_2474 : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t lo_sdm_dither_sel_ble_2476 : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t lo_sdm_dither_sel_ble_2478 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t lo_sdm_dither_sel_ble_2480 : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t lo_sdm_dither_sel_ble_tx : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad0 : 14; + }; + } lo_sdm_ctrl_hw4; // @ 0x1bc + union { + uint32_t value; + struct { + uint32_t lo_center_freq_mhz : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t lo_sdm_bypass_mode : 6; // @ 17 -- 12 # 0xfffc0fff + uint32_t pad0 : 14; + }; + } lo_sdm_ctrl_hw5; // @ 0x1c0 + union { + uint32_t value; + struct { + uint32_t lo_sdmin_center : 29; // @ 28 -- 0 # 0xe0000000 + uint32_t pad0 : 3; + }; + } lo_sdm_ctrl_hw6; // @ 0x1c4 + union { + uint32_t value; + struct { + uint32_t lo_sdmin_1m : 20; // @ 19 -- 0 # 0xfff00000 + uint32_t pad0 : 12; + }; + } lo_sdm_ctrl_hw7; // @ 0x1c8 + union { + uint32_t value; + struct { + uint32_t lo_sdmin_if : 20; // @ 19 -- 0 # 0xfff00000 + uint32_t pad0 : 12; + }; + } lo_sdm_ctrl_hw8; // @ 0x1cc + union { + uint32_t value; + struct { + uint32_t rbb_bt_mode_ble : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } rbb_bw_ctrl_hw; // @ 0x1d0 + uint8_t pad2[0x38]; + union { + uint32_t value; + struct { + uint32_t singen_inc_step1 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t singen_inc_step0 : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 2; + uint32_t singen_unsign_en : 1; // @ 28 -- 28 # 0xefffffff + uint32_t singen_clkdiv_n : 2; // @ 30 -- 29 # 0x9fffffff + uint32_t singen_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } singen_ctrl0; // @ 0x20c + union { + uint32_t value; + struct { + uint32_t singen_clkdiv_q : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 2; + uint32_t singen_mode_q : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t singen_clkdiv_i : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 2; + uint32_t singen_mode_i : 4; // @ 31 -- 28 # 0xfffffff + }; + } singen_ctrl1; // @ 0x210 + union { + uint32_t value; + struct { + uint32_t singen_gain_i : 11; // @ 10 -- 0 # 0xfffff800 + uint32_t pad0 : 1; + uint32_t singen_start_addr1_i : 10; // @ 21 -- 12 # 0xffc00fff + uint32_t singen_start_addr0_i : 10; // @ 31 -- 22 # 0x3fffff + }; + } singen_ctrl2; // @ 0x214 + union { + uint32_t value; + struct { + uint32_t singen_gain_q : 11; // @ 10 -- 0 # 0xfffff800 + uint32_t pad0 : 1; + uint32_t singen_start_addr1_q : 10; // @ 21 -- 12 # 0xffc00fff + uint32_t singen_start_addr0_q : 10; // @ 31 -- 22 # 0x3fffff + }; + } singen_ctrl3; // @ 0x218 + union { + uint32_t value; + struct { + uint32_t singen_fix_q : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t singen_fix_en_q : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad0 : 3; + uint32_t singen_fix_i : 12; // @ 27 -- 16 # 0xf000ffff + uint32_t singen_fix_en_i : 1; // @ 28 -- 28 # 0xefffffff + uint32_t pad1 : 3; + }; + } singen_ctrl4; // @ 0x21c + union { + uint32_t value; + struct { + uint32_t rfckg_rxclk_4s_on : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rfckg_txclk_4s_on : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rfckg_adc_afifo_inv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rfckg_adc_clkout_sel : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t rfckg_dac_afifo_inv : 1; // @ 4 -- 4 # 0xffffffef + uint32_t rx_dfe_en_4s : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rx_dfe_en_4s_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t tx_dfe_en_4s : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t tx_dfe_en_4s_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t rx_test_sel : 2; // @ 10 -- 9 # 0xfffff9ff + uint32_t tx_test_sel : 2; // @ 12 -- 11 # 0xffffe7ff + uint32_t pad_adc_clkout_inv_en : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad_dac_clkout_inv_en : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t rf_ch_ind_ble_4s : 7; // @ 21 -- 15 # 0xffc07fff + uint32_t rf_ch_ind_ble_4s_en : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t wifimode_4s : 2; // @ 24 -- 23 # 0xfe7fffff + uint32_t wifimode_4s_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t bbmode_4s : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t bbmode_4s_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t test_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } rfif_dfe_ctrl0; // @ 0x220 + union { + uint32_t value; + struct { + uint32_t test_read : 32; // @ 31 -- 0 # 0x0 + }; + } rfif_test_read; // @ 0x224 + union { + uint32_t value; + struct { + uint32_t test_from_pad_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t test_gc_from_pad_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rfckg_rxclk_div2_mode : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rfif_int_lo_unlocked_mask : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 12; + uint32_t rfif_ppud_cnt2 : 9; // @ 24 -- 16 # 0xfe00ffff + uint32_t rfif_ppud_cnt1 : 5; // @ 29 -- 25 # 0xc1ffffff + uint32_t rfif_ppud_manaual_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t pad1 : 1; + }; + } rfif_dig_ctrl; // @ 0x228 + union { + uint32_t value; + struct { + uint32_t rf_data_temp_0 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_data_temp_0; // @ 0x22c + union { + uint32_t value; + struct { + uint32_t rf_data_temp_1 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_data_temp_1; // @ 0x230 + union { + uint32_t value; + struct { + uint32_t rf_data_temp_2 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_data_temp_2; // @ 0x234 + union { + uint32_t value; + struct { + uint32_t rf_data_temp_3 : 32; // @ 31 -- 0 # 0x0 + }; + } rf_data_temp_3; // @ 0x238 + union { + uint32_t value; + struct { + uint32_t rf_sram_link_dly : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t rf_sram_link_mode : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t rf_sram_swap : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t rf_sram_ext_clr : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pad0 : 12; + }; + } rf_sram_ctrl0; // @ 0x23c + union { + uint32_t value; + struct { + uint32_t rf_sram_adc_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rf_sram_adc_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rf_sram_adc_loop_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rf_sram_adc_sts_clr : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 12; + uint32_t rf_sram_adc_done_cnt : 16; // @ 31 -- 16 # 0xffff + }; + } rf_sram_ctrl1; // @ 0x240 + union { + uint32_t value; + struct { + uint32_t rf_sram_adc_addr_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t rf_sram_adc_addr_start : 16; // @ 31 -- 16 # 0xffff + }; + } rf_sram_ctrl2; // @ 0x244 + union { + uint32_t value; + struct { + uint32_t rf_sram_adc_sts : 32; // @ 31 -- 0 # 0x0 + }; + } rf_sram_ctrl3; // @ 0x248 + union { + uint32_t value; + struct { + uint32_t rf_sram_dac_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rf_sram_dac_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rf_sram_dac_loop_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rf_sram_dac_sts_clr : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 12; + uint32_t rf_sram_dac_done_cnt : 16; // @ 31 -- 16 # 0xffff + }; + } rf_sram_ctrl4; // @ 0x24c + union { + uint32_t value; + struct { + uint32_t rf_sram_dac_addr_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t rf_sram_dac_addr_start : 16; // @ 31 -- 16 # 0xffff + }; + } rf_sram_ctrl5; // @ 0x250 + union { + uint32_t value; + struct { + uint32_t rf_sram_dac_sts : 32; // @ 31 -- 0 # 0x0 + }; + } rf_sram_ctrl6; // @ 0x254 + union { + uint32_t value; + struct { + uint32_t rf_ical_r_cnt_n : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t rf_ical_a_cnt_n : 10; // @ 19 -- 10 # 0xfff003ff + uint32_t rf_ical_f_cnt_n : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t rf_ical_a_ud_inv_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t rf_ical_f_ud_inv_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } rf_ical_ctrl0; // @ 0x258 + union { + uint32_t value; + struct { + uint32_t rf_ical_r_avg_n : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 5; + uint32_t rf_ical_r_os_q : 10; // @ 19 -- 10 # 0xfff003ff + uint32_t rf_ical_r_os_i : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t pad1 : 2; + }; + } rf_ical_ctrl1; // @ 0x25c + union { + uint32_t value; + struct { + uint32_t rf_ical_period_n : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } rf_ical_ctrl2; // @ 0x260 + union { + uint32_t value; + struct { + uint32_t rf_ch_ind_wifi : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 20; + }; + } rf_fsm_ctrl0; // @ 0x264 + union { + uint32_t value; + struct { + uint32_t rf_fsm_lo_time : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t rf_fsm_lo_rdy : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t rf_fsm_lo_rdy_rst : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t rf_fsm_lo_rdy_4s_1 : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t rf_fsm_lo_rdy_sbclr : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t rf_fsm_pu_pa_dly_n : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t pad0 : 2; + }; + } rf_fsm_ctrl1; // @ 0x268 + union { + uint32_t value; + struct { + uint32_t rf_fsm_st_dbg : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t rf_fsm_st_dbg_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t rf_trx_en_ble_4s : 1; // @ 4 -- 4 # 0xffffffef + uint32_t rf_trx_sw_ble_4s : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rf_trx_ble_4s_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad0 : 3; + uint32_t rf_fsm_dfe_tx_dly_n : 10; // @ 19 -- 10 # 0xfff003ff + uint32_t rf_fsm_dfe_rx_dly_n : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t pad1 : 2; + }; + } rf_fsm_ctrl2; // @ 0x26c + union { + uint32_t value; + struct { + uint32_t pkdet_out_cnt_sts : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t pkdet_out_cnt_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pkdet_out_mode : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 26; + }; + } rf_pkdet_ctrl0; // @ 0x270 + uint8_t pad3[0x38c]; + union { + uint32_t value; + struct { + uint32_t tx_iqc_phase : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t tx_iqc_phase_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad0 : 1; + uint32_t tx_iqc_gain : 11; // @ 22 -- 12 # 0xff800fff + uint32_t tx_iqc_gain_en : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t tx_dvga_gain_qdb : 7; // @ 30 -- 24 # 0x80ffffff + uint32_t tx_dvga_gain_ctrl_hw : 1; // @ 31 -- 31 # 0x7fffffff + }; + } dfe_ctrl_0; // @ 0x600 + union { + uint32_t value; + struct { + uint32_t tx_dac_os_i : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 4; + uint32_t tx_dac_os_q : 12; // @ 27 -- 16 # 0xf000ffff + uint32_t pad1 : 2; + uint32_t tx_dac_dat_format : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t tx_dac_iq_swap : 1; // @ 31 -- 31 # 0x7fffffff + }; + } dfe_ctrl_1; // @ 0x604 + union { + uint32_t value; + struct { + uint32_t rx_adc_os_i : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t rx_adc_os_q : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 2; + uint32_t rx_adc_dce_flt_en : 1; // @ 28 -- 28 # 0xefffffff + uint32_t rx_adc_low_pow_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t rx_adc_dat_format : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t rx_adc_iq_swap : 1; // @ 31 -- 31 # 0x7fffffff + }; + } dfe_ctrl_2; // @ 0x608 + union { + uint32_t value; + struct { + uint32_t rx_adc_4s_i_val : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t rx_adc_4s_i_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad0 : 5; + uint32_t rx_adc_4s_q_val : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t rx_adc_4s_q_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad1 : 5; + }; + } dfe_ctrl_3; // @ 0x60c + union { + uint32_t value; + struct { + uint32_t rx_pf_th2 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t rx_pf_th1 : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 4; + uint32_t rx_pf_q_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t rx_pf_i_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } dfe_ctrl_4; // @ 0x610 + union { + uint32_t value; + struct { + uint32_t rx_iqc_phase : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t rx_iqc_phase_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad0 : 1; + uint32_t rx_iqc_gain : 11; // @ 22 -- 12 # 0xff800fff + uint32_t rx_iqc_gain_en : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t pad1 : 8; + }; + } dfe_ctrl_5; // @ 0x614 + union { + uint32_t value; + struct { + uint32_t rx_pm_freqshift_cw : 20; // @ 19 -- 0 # 0xfff00000 + uint32_t rx_pm_freqshift_en : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad0 : 7; + uint32_t rx_pm_done : 1; // @ 28 -- 28 # 0xefffffff + uint32_t rx_pm_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t rx_pm_in_sel : 2; // @ 31 -- 30 # 0x3fffffff + }; + } dfe_ctrl_6; // @ 0x618 + union { + uint32_t value; + struct { + uint32_t rx_pm_start_ofs : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t rx_pm_acc_len : 16; // @ 31 -- 16 # 0xffff + }; + } dfe_ctrl_7; // @ 0x61c + union { + uint32_t value; + struct { + uint32_t rx_pm_iqacc_i : 25; // @ 24 -- 0 # 0xfe000000 + uint32_t pad0 : 7; + }; + } dfe_ctrl_8; // @ 0x620 + union { + uint32_t value; + struct { + uint32_t rx_pm_iqacc_q : 25; // @ 24 -- 0 # 0xfe000000 + uint32_t pad0 : 7; + }; + } dfe_ctrl_9; // @ 0x624 + union { + uint32_t value; + struct { + uint32_t dfe_dac_raw_i : 11; // @ 10 -- 0 # 0xfffff800 + uint32_t pad0 : 5; + uint32_t dfe_dac_raw_q : 11; // @ 26 -- 16 # 0xf800ffff + uint32_t pad1 : 5; + }; + } dfe_ctrl_10; // @ 0x628 + union { + uint32_t value; + struct { + uint32_t dfe_adc_raw_i : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t pad0 : 6; + uint32_t dfe_adc_raw_q : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t pad1 : 6; + }; + } dfe_ctrl_11; // @ 0x62c + union { + uint32_t value; + struct { + uint32_t tx_dvga_gain_qdb_gc0 : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + uint32_t tx_dvga_gain_qdb_gc1 : 7; // @ 14 -- 8 # 0xffff80ff + uint32_t pad1 : 1; + uint32_t tx_dvga_gain_qdb_gc2 : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 1; + uint32_t tx_dvga_gain_qdb_gc3 : 7; // @ 30 -- 24 # 0x80ffffff + uint32_t pad3 : 1; + }; + } dfe_ctrl_12; // @ 0x630 + union { + uint32_t value; + struct { + uint32_t tx_dvga_gain_qdb_gc4 : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + uint32_t tx_dvga_gain_qdb_gc5 : 7; // @ 14 -- 8 # 0xffff80ff + uint32_t pad1 : 1; + uint32_t tx_dvga_gain_qdb_gc6 : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 1; + uint32_t tx_dvga_gain_qdb_gc7 : 7; // @ 30 -- 24 # 0x80ffffff + uint32_t pad3 : 1; + }; + } dfe_ctrl_13; // @ 0x634 + union { + uint32_t value; + struct { + uint32_t tx_dvga_gain_qdb_gc8 : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + uint32_t tx_dvga_gain_qdb_gc9 : 7; // @ 14 -- 8 # 0xffff80ff + uint32_t pad1 : 1; + uint32_t tx_dvga_gain_qdb_gc10 : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 1; + uint32_t tx_dvga_gain_qdb_gc11 : 7; // @ 30 -- 24 # 0x80ffffff + uint32_t pad3 : 1; + }; + } dfe_ctrl_14; // @ 0x638 + union { + uint32_t value; + struct { + uint32_t tx_dvga_gain_qdb_gc12 : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + uint32_t tx_dvga_gain_qdb_gc13 : 7; // @ 14 -- 8 # 0xffff80ff + uint32_t pad1 : 1; + uint32_t tx_dvga_gain_qdb_gc14 : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 1; + uint32_t tx_dvga_gain_qdb_gc15 : 7; // @ 30 -- 24 # 0x80ffffff + uint32_t pad3 : 1; + }; + } dfe_ctrl_15; // @ 0x63c + union { + uint32_t value; + struct { + uint32_t rf_tbb_ind_gc0 : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t rf_tbb_ind_gc1 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t rf_tbb_ind_gc2 : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad2 : 1; + uint32_t rf_tbb_ind_gc3 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t rf_tbb_ind_gc4 : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad4 : 1; + uint32_t rf_tbb_ind_gc5 : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t rf_tbb_ind_gc6 : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad6 : 1; + uint32_t rf_tbb_ind_gc7 : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad7 : 1; + }; + } dfe_ctrl_16; // @ 0x640 + union { + uint32_t value; + struct { + uint32_t rf_tbb_ind_gc8 : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + uint32_t rf_tbb_ind_gc9 : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad1 : 1; + uint32_t rf_tbb_ind_gc10 : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad2 : 1; + uint32_t rf_tbb_ind_gc11 : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t pad3 : 1; + uint32_t rf_tbb_ind_gc12 : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad4 : 1; + uint32_t rf_tbb_ind_gc13 : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad5 : 1; + uint32_t rf_tbb_ind_gc14 : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pad6 : 1; + uint32_t rf_tbb_ind_gc15 : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t pad7 : 1; + }; + } dfe_ctrl_17; // @ 0x644 + union { + uint32_t value; + struct { + uint32_t tx_dvga_gain_qdb_ble_gc0 : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + uint32_t tx_dvga_gain_qdb_ble_gc1 : 7; // @ 14 -- 8 # 0xffff80ff + uint32_t pad1 : 1; + uint32_t tx_dvga_gain_qdb_ble_gc2 : 7; // @ 22 -- 16 # 0xff80ffff + uint32_t pad2 : 9; + }; + } dfe_ctrl_18; // @ 0x648 + }; +} rf_regs; +#define RF_BASE 0x40001000 +#define RF ((rf_regs* volatile)(RF_BASE)) \ No newline at end of file From b346a663b9a38d6e1c2ee2e3d423972b0184b4c6 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:20:12 -0500 Subject: [PATCH 042/148] add rf_priv header --- src/bl602_wifi/bl602_rf_private.h | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 src/bl602_wifi/bl602_rf_private.h diff --git a/src/bl602_wifi/bl602_rf_private.h b/src/bl602_wifi/bl602_rf_private.h new file mode 100644 index 0000000..bead91b --- /dev/null +++ b/src/bl602_wifi/bl602_rf_private.h @@ -0,0 +1,81 @@ +#ifndef _BL602_RF_PRIVATE_H_ +#define _BL602_RF_PRIVATE_H_ +#include + +struct anon_struct { + uint32_t index; + int32_t dvga; +}; + +typedef struct anon_struct anon_struct; + +struct anon_struct { + uint32_t vbcore; + uint32_t iet; + uint32_t vbcore_11n; + uint32_t iet_11n; + uint32_t vbcore_11g; + uint32_t iet_11g; + uint32_t vbcore_11b; + uint32_t iet_11b; + uint32_t lo_fbdv_halfstep_en; + uint32_t lo_fbdv_halfstep_en_tx; + uint32_t lo_fbdv_halfstep_en_rx; + uint32_t clkpll_reset_postdiv; + uint32_t clkpll_dither_sel; +}; + +struct notch_param { + uint32_t notch_en; + int32_t spur_freq; +}; + +typedef struct notch_param notch_param; + +struct regs_to_opti { + uint32_t vbcore; + uint32_t iet; + uint32_t vbcore_11n; + uint32_t iet_11n; + uint32_t vbcore_11g; + uint32_t iet_11g; + uint32_t vbcore_11b; + uint32_t iet_11b; + uint32_t lo_fbdv_halfstep_en; + uint32_t lo_fbdv_halfstep_en_tx; + uint32_t lo_fbdv_halfstep_en_rx; + uint32_t clkpll_reset_postdiv; + uint32_t clkpll_dither_sel; +}; + +typedef struct regs_to_opti regs_to_opti; + +struct tx_pwr_index { + uint32_t index; + int32_t dvga; +}; + +typedef struct tx_pwr_index tx_pwr_index; + +void rf_pri_config_bandwidth(uint32_t bw); +void rf_pri_fcal(void); +void rf_pri_full_cal(void); +void rf_pri_get_notch_param(uint32_t chanfreq_MHz, uint8_t * ncf_on, int32_t * ncf_freq_Hz); +uint32_t rf_pri_get_txgain_index(int32_t pwr, uint32_t mode); +int32_t rf_pri_get_txgain_max(void); +int32_t rf_pri_get_txgain_min(void); +uint32_t rf_pri_get_vco_freq_cw(uint32_t chanfreq_MHz); +uint32_t rf_pri_get_vco_idac_cw(uint32_t chanfreq_MHz); +void rf_pri_init(uint8_t reset, uint8_t chipv); +void rf_pri_init_fast(uint32_t flag); +void rf_pri_lo_acal(void); +void rf_pri_query_txgain_table(uint32_t index, uint32_t * rfg_index, uint32_t * dg); +void rf_pri_rccal(void); +void rf_pri_tx_gain_comp(int32_t Tsens); +void rf_pri_txcal(void); +void rf_pri_update_param(uint32_t chanfreq_MHz); +void rf_pri_update_power_offset(int32_t * power_offset); +void rf_pri_update_tx_power_offset(uint8_t channel, int8_t * power_offset); +void rf_pri_update_txgain_tempos(int16_t tempos); +void rf_pri_xtalfreq(uint32_t xtalfreq); +#endif \ No newline at end of file From 49a3fd6f770083d8faa0be149a38e5f4ceb43a02 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:20:34 -0500 Subject: [PATCH 043/148] fix return true --- src/bl602_wifi/phy_hal.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/bl602_wifi/phy_hal.c b/src/bl602_wifi/phy_hal.c index 2a7f6ca..3d44b30 100644 --- a/src/bl602_wifi/phy_hal.c +++ b/src/bl602_wifi/phy_hal.c @@ -35,6 +35,7 @@ void hal_get_capcode_asymm(uint8_t *capcode_in, uint8_t *capcode_out) { bool hal_get_temperature(int16_t *temperature) { *temperature = hal_env.temperature; + return 1; } void hal_set_temperature(int16_t temperature) { From 1106214d88b99551dad0b61c4362653ba9e03fb4 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:20:48 -0500 Subject: [PATCH 044/148] add tcal --- src/bl602_wifi/phy_tcal.c | 62 +++++++++++++++++++++++++++++++++++++++ src/bl602_wifi/phy_tcal.h | 15 ++++++++++ 2 files changed, 77 insertions(+) create mode 100644 src/bl602_wifi/phy_tcal.c diff --git a/src/bl602_wifi/phy_tcal.c b/src/bl602_wifi/phy_tcal.c new file mode 100644 index 0000000..980727e --- /dev/null +++ b/src/bl602_wifi/phy_tcal.c @@ -0,0 +1,62 @@ +#include "phy_tcal.h" +#include "phy_hal.h" +#include "phy_bl602.h" +#include "phy_trpc.h" +#include "bl602_rf_private.h" + +static struct tcal_tag tcal_env; // :41:24 + +void phy_tcal_reset(void) { + memset(&tcal_env,0,0x38); + tcal_env.prev_temperature = 0x19; + tcal_env.last_action_temperature[0] = 0x19; + tcal_env.last_action_temperature[1] = 0x19; + tcal_env.last_action_temperature[2] = 0x19; + tcal_env.last_action_temperature[3] = 0x19; + tcal_env.enabled = 1; +} + +void phy_tcal_start(void) { + tcal_env.enabled = 1; +} + +void phy_tcal_stop(void) { + tcal_env.enabled = 0; +} + +void phy_tcal_handle(void) { + int16_t temp; + if (hal_get_temperature(&temp)) { + phy_tcal_txpwr(temp); + int cutoff = temp; + if (cutoff > 125) + cutoff = 125; + if (cutoff < -40) + cutoff = -40; + // iVar3 = (int)((uVar2 - 0x19) * 0x10000) >> 0x10; sign? + int offset = cutoff - 25; + if (offset < 1) { + offset = (offset * -6) >> 8; + } else { + offset = ((offset * 6) >> 8) * (-1); + } + if (offset != tcal_env.last_action_out[2]) { + phy_config_rxgain(offset); + tcal_env.last_action_temperature[2] = cutoff; + tcal_env.last_action_out[2] = offset; + } + tcal_env.prev_temperature = temp; + } +} + +void phy_tcal_callback(int16_t temperature) { + hal_set_temperature(temperature); + if (tcal_env.enabled) { + phy_tcal_handle(); + } +} + +void phy_tcal_txpwr(int16_t curr_temperature) { + rf_pri_tx_gain_comp(curr_temperature); + trpc_update_vs_temperature((int8_t)curr_temperature); +} diff --git a/src/bl602_wifi/phy_tcal.h b/src/bl602_wifi/phy_tcal.h index 87cb0c7..db84c03 100644 --- a/src/bl602_wifi/phy_tcal.h +++ b/src/bl602_wifi/phy_tcal.h @@ -1,6 +1,21 @@ #ifndef _PHY_TCAL_H_ #define _PHY_TCAL_H_ + +#include + void phy_tcal_reset(void); void phy_tcal_start(void); +struct tcal_tag { + int16_t prev_temperature; // +0 + uint32_t last_action_time[4]; // +4 + uint32_t last_action_temperature[4]; // +20 + int32_t last_action_out[4]; // +36 + bool enabled; // +52 +}; // :29:8 + +void phy_tcal_stop(void); // :69:6 +void phy_tcal_handle(void); // :74:6 +void phy_tcal_callback(int16_t temperature); // :104:6 +void phy_tcal_txpwr(int16_t curr_temperature); // :141:6 #endif \ No newline at end of file From 908848339941b1d934f0a40fdb6b9f0fbf4b2259 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:20:57 -0500 Subject: [PATCH 045/148] add trpc --- src/bl602_wifi/phy_trpc.c | 111 ++++++++++++++++++++++++++++++++++++++ src/bl602_wifi/phy_trpc.h | 19 +++++++ 2 files changed, 130 insertions(+) create mode 100644 src/bl602_wifi/phy_trpc.c diff --git a/src/bl602_wifi/phy_trpc.c b/src/bl602_wifi/phy_trpc.c new file mode 100644 index 0000000..5ac8e0d --- /dev/null +++ b/src/bl602_wifi/phy_trpc.c @@ -0,0 +1,111 @@ +#include "phy_trpc.h" +#include "phy_bl602.h" +#include "bl602_rf_private.h" +#include "utils.h" + +static int8_t txpwr_vs_rate_table[3][8] = { + {0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12}, + {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, 0x0e}, + {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, 0x0e}, +}; // :12:15 + +static struct trpc_env_tag trpc_env; + +uint8_t trpc_get_default_power_idx(uint8_t formatmod, uint8_t mcs) { + if (formatmod > PHY_FORMATMOD_11N) { + formatmod = PHY_FORMATMOD_11N; + } + int mcs_max = 3; + if (formatmod) { + mcs_max = 7; + } + if (mcs > mcs_max) { + mcs = mcs_max; + } + return trpc_get_power_idx(formatmod, mcs, txpwr_vs_rate_table[formatmod][mcs]); +} + +uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm) { + if (formatmod > PHY_FORMATMOD_11N) { + formatmod = PHY_FORMATMOD_11N; + } + int mcs_max = 3; + if (formatmod) { + mcs_max = 7; + } + if (mcs > mcs_max) { + mcs = mcs_max; + } + int pwr = MIN(trpc_env.power_dbm_max_rf, trpc_env.power_dbm_lim_reg); + pwr = MIN(pwr, pwr_dbm); + pwr = MIN(pwr, txpwr_vs_rate_table[formatmod][mcs]); + pwr = MAX(pwr, trpc_env.power_dbm_min_rf); + int x = (int)(((double)((int)(pwr * -510 + trpc_env.power_dbm_max_rf) / 512)) + (double)0.5) & 0xff; + int y = 3; + if (formatmod) { + y = 0; + } + x = (y + x) & 0xff; + if (x > 0xf) + x = 0xf; + return x << 2; +} + +int8_t trpc_get_rf_max_power() { + return trpc_env.power_dbm_max_rf; +} + +int8_t trpc_get_rf_min_power() { + return trpc_env.power_dbm_min_rf; +} + +void trpc_init(void) { + trpc_env.channel_freq = 2442; + trpc_env.power_dbm_max_rf = rf_pri_get_txgain_max(); + trpc_env.power_dbm_min_rf = rf_pri_get_txgain_min(); + trpc_env.power_dbm_lim_reg = 30; + trpc_env.temperature = 25; +} + +void trpc_power_get(int8_t *power_rate_table) { + memcpy(power_rate_table, txpwr_vs_rate_table, sizeof(txpwr_vs_rate_table)); +} + +void trpc_update_power(int8_t (*power_rate_table) [8]) { + for (int i = 0; i < 3; i ++) { + for (int j = 0; j < 8; j++) { + txpwr_vs_rate_table[i][j] = power_rate_table[i][j]; + } + } +} + +void trpc_update_power_11b(int8_t *power_rate_table) { + for (int j = 0; j < 8; j++) { + txpwr_vs_rate_table[0][j] = power_rate_table[j]; + } +} + +void trpc_update_power_11g(int8_t *power_rate_table) { + for (int j = 0; j < 8; j++) { + txpwr_vs_rate_table[1][j] = power_rate_table[j]; + } +} + +void trpc_update_power_11n(int8_t *power_rate_table) { + for (int j = 0; j < 8; j++) { + txpwr_vs_rate_table[2][j] = power_rate_table[j]; + } +} + +void trpc_update_vs_channel(int8_t channel_MHz) { + trpc_env.channel_freq = channel_MHz; + trpc_env.power_dbm_max_rf = rf_pri_get_txgain_max(); + trpc_env.power_dbm_min_rf = rf_pri_get_txgain_min(); +} + + +void trpc_update_vs_temperature(int8_t temperature) { + trpc_env.temperature = temperature; + trpc_env.power_dbm_max_rf = rf_pri_get_txgain_max(); + trpc_env.power_dbm_min_rf = rf_pri_get_txgain_min(); +} diff --git a/src/bl602_wifi/phy_trpc.h b/src/bl602_wifi/phy_trpc.h index e4480d9..4ea0a66 100644 --- a/src/bl602_wifi/phy_trpc.h +++ b/src/bl602_wifi/phy_trpc.h @@ -1,9 +1,28 @@ #ifndef _PHY_TRPC_H_ #define _PHY_TRPC_H_ #include + +struct trpc_env_tag { + int8_t power_dbm_max_rf; // +0 + int8_t power_dbm_min_rf; // +1 + int8_t power_dbm_lim_reg; // +2 + int16_t channel_freq; // +4 + int8_t temperature; // +6 + int8_t temperature_compensate; // +7 +}; + void trpc_init(void); int8_t trpc_get_rf_max_power(void); int8_t trpc_get_rf_min_power(void); uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm); void trpc_update_vs_channel(int8_t channel_MHz); // :171:6 + +uint8_t trpc_get_default_power_idx(uint8_t formatmod,uint8_t mcs); +void trpc_power_get(int8_t * power_rate_table); +void trpc_update_power(int8_t (*power_rate_table) [8]); +void trpc_update_power_11b(int8_t * power_rate_table); +void trpc_update_power_11g(int8_t * power_rate_table); +void trpc_update_power_11n(int8_t * power_rate_table); +void trpc_update_vs_channel(int8_t channel_MHz); +void trpc_update_vs_temperature(int8_t temperature); #endif \ No newline at end of file From 1ffd6cbc31f637e2c4b590e04606f5105f10fcc4 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:23:47 -0500 Subject: [PATCH 046/148] fix redefinition and memset --- src/bl602_wifi/bl602_rf_private.h | 4 ++-- src/bl602_wifi/phy_tcal.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/bl602_wifi/bl602_rf_private.h b/src/bl602_wifi/bl602_rf_private.h index bead91b..27a630f 100644 --- a/src/bl602_wifi/bl602_rf_private.h +++ b/src/bl602_wifi/bl602_rf_private.h @@ -2,12 +2,12 @@ #define _BL602_RF_PRIVATE_H_ #include -struct anon_struct { +struct anon_struct1 { uint32_t index; int32_t dvga; }; -typedef struct anon_struct anon_struct; +typedef struct anon_struct1 anon_struct1; struct anon_struct { uint32_t vbcore; diff --git a/src/bl602_wifi/phy_tcal.c b/src/bl602_wifi/phy_tcal.c index 980727e..5d625b8 100644 --- a/src/bl602_wifi/phy_tcal.c +++ b/src/bl602_wifi/phy_tcal.c @@ -3,6 +3,7 @@ #include "phy_bl602.h" #include "phy_trpc.h" #include "bl602_rf_private.h" +#include "utils.h" static struct tcal_tag tcal_env; // :41:24 From 184aa2caf5cf95f614a75dff92e1431540d5d6c3 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:29:13 -0500 Subject: [PATCH 047/148] using rv32 and c11 --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5c60843..c5f600a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ set(CMAKE_SYSTEM_PROCESSOR riscv) SET(CMAKE_CROSSCOMPILING 1) set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") - +add_compile_options(-std=c11 -march=rv32imfc -mabi=ilp32f) project(bl602_re VERSION 0.1.0) include_directories(./src/include) From f4959fc0ae1a4060c9ad6d5e78d41772818a62de Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:29:37 -0500 Subject: [PATCH 048/148] add memcpy and min/max --- src/bl602_wifi/utils.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/bl602_wifi/utils.h b/src/bl602_wifi/utils.h index 68cdca3..6a71b76 100644 --- a/src/bl602_wifi/utils.h +++ b/src/bl602_wifi/utils.h @@ -1,5 +1,9 @@ #ifndef __UTILS_H_ #define ABS(x) (((x) > 0) ? (x) : (-(x))) +#define MIN(x,y) (((x) > (y)) ? (y) : (x)) +#define MAX(x,y) (((x) < (y)) ? (y) : (x)) int puts(char *s); int printf(char *fmt,...); +void* memset(void *, int, long unsigned int); +void* memcpy(void*, const void*, unsigned int); #endif \ No newline at end of file From f20f2555f4f3ae3aad94409c464aa373aa45cb3a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 02:43:37 -0500 Subject: [PATCH 049/148] fix type --- src/bl602_wifi/phy_trpc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/bl602_wifi/phy_trpc.c b/src/bl602_wifi/phy_trpc.c index 5ac8e0d..cd7a453 100644 --- a/src/bl602_wifi/phy_trpc.c +++ b/src/bl602_wifi/phy_trpc.c @@ -45,9 +45,9 @@ uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm) { if (formatmod) { y = 0; } - x = (y + x) & 0xff; - if (x > 0xf) - x = 0xf; + uint32_t z = (y + x) & 0xff; + if (z > 0xf) + z = 0xf; return x << 2; } From 9079d1ea7c78d4e60cd52b8fc9c403430f5b96a4 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 03:22:30 -0500 Subject: [PATCH 050/148] add phyif_utils --- src/bl602_wifi/phyif_utils.c | 56 ++++++++++++++++++++++++++++++++++++ src/bl602_wifi/phyif_utils.h | 16 +++++++++++ 2 files changed, 72 insertions(+) create mode 100644 src/bl602_wifi/phyif_utils.c create mode 100644 src/bl602_wifi/phyif_utils.h diff --git a/src/bl602_wifi/phyif_utils.c b/src/bl602_wifi/phyif_utils.c new file mode 100644 index 0000000..92e0623 --- /dev/null +++ b/src/bl602_wifi/phyif_utils.c @@ -0,0 +1,56 @@ +#include "phyif_utils.h" + +typedef struct { + uint32_t leg_length:12; // +0 + uint32_t leg_rate:4; // +0 + uint32_t ht_length:16; // +0 + uint32_t _ht_length:4; // +4 + uint32_t short_gi:1; // +4 + uint32_t stbc:2; // +4 + uint32_t smoothing:1; // +4 + uint32_t mcs:7; // +4 + uint32_t pre_type:1; // +4 + uint32_t format_mod:3; // +4 + uint32_t ch_bw:2; // +4 + uint32_t n_sts:3; // +4 + uint32_t lsig_valid:1; // +4 + uint32_t sounding:1; // +4 + uint32_t num_extn_ss:2; // +4 + uint32_t aggregation:1; // +4 + uint32_t fec_coding:1; // +4 + uint32_t dyn_bw:1; // +4 + uint32_t doze_not_allowed:1; // +4 + uint32_t antenna_set:8; // +8 + uint32_t partial_aid:9; // +8 + uint32_t group_id:6; // +8 + uint32_t reserved_1c:1; // +8 + int32_t rssi1:8; // +8 + int32_t rssi2:8; // +12 + union { + int32_t rssi34:16; + struct { + int32_t rssi3:8; // +12 + int32_t rssi4:8; // +12 + }; + }; + uint32_t reserved_1d:8; // +12 + uint32_t rcpi:8; // +16 + uint32_t evm1:8; // +16 + uint32_t evm2:8; // +16 + uint32_t evm3:8; // +16 + uint32_t evm4:8; // +20 + uint32_t reserved2b_1:8; // +20 + uint32_t reserved2b_2:8; // +20 + uint32_t reserved2b_3:8; // +20 +} phyif_utils_recvtable_priv_t; // :47:3 + +int phyif_utils_decode(phyif_utils_recvtable_t *vec,int8_t *ppm) { + phyif_utils_recvtable_priv_t* pvec = (phyif_utils_recvtable_priv_t*) vec; + int8_t vppm = 0; + if (pvec->format_mod < 2 && pvec->leg_rate < 4) { + vppm = (int)((double)(-(int)pvec->rssi3) * 0.7); + } else { + vppm = ((int)pvec->rssi34 / 0x7a); + } + *ppm = vppm; +} diff --git a/src/bl602_wifi/phyif_utils.h b/src/bl602_wifi/phyif_utils.h new file mode 100644 index 0000000..25f31ee --- /dev/null +++ b/src/bl602_wifi/phyif_utils.h @@ -0,0 +1,16 @@ +#ifndef _PHYIF_H_ +#define _PHYIF_H_ + +#include + +typedef struct { + uint32_t recvtable1; // +0 + uint32_t recvtable2; // +4 + uint32_t recvtable3; // +8 + uint32_t recvtable4; // +12 + uint32_t recvtable5; // +16 + uint32_t recvtable6; // +20 +} phyif_utils_recvtable_t; // :11:3 +int phyif_utils_decode(phyif_utils_recvtable_t *vec,int8_t *ppm); + +#endif \ No newline at end of file From 0a747be4c9d3f87a037ff3f111e369851c44a4f1 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 03:57:58 -0500 Subject: [PATCH 051/148] add rf --- src/bl602_wifi/rf.c | 24 ++++++++++++++++++++++++ src/bl602_wifi/rf.h | 5 +++++ src/bl602_wifi/rfc_bl602.h | 1 + 3 files changed, 30 insertions(+) create mode 100644 src/bl602_wifi/rf.c diff --git a/src/bl602_wifi/rf.c b/src/bl602_wifi/rf.c new file mode 100644 index 0000000..8c6b786 --- /dev/null +++ b/src/bl602_wifi/rf.c @@ -0,0 +1,24 @@ +#include "rf.h" +#include "rfc_bl602.h" + +void rf_set_channel(uint8_t bandwidth, uint16_t channel_freq) { + rfc_config_channel(channel_freq); +} + +void rf_clkpll_isr(void) { + return ; +} + +void rf_init(void) { + __asm( + "csrrci a5, mstatus, 0x8\n\t" + "andi a5, a5, 0x8\n\t" + "beqz a5, .L0\n\t" + "csrrsi zero, mstatus, 0x8\n\t" + ".L0:" + ); +} + +void rf_lo_isr(void) { + return ; +} diff --git a/src/bl602_wifi/rf.h b/src/bl602_wifi/rf.h index d73cf2d..28a73df 100644 --- a/src/bl602_wifi/rf.h +++ b/src/bl602_wifi/rf.h @@ -1,4 +1,9 @@ #ifndef _RF_H_ #define _RF_H_ +#include + void rf_set_channel(uint8_t bandwidth, uint16_t channel_freq); +void rf_clkpll_isr(void); +void rf_init(void); +void rf_lo_isr(void); #endif \ No newline at end of file diff --git a/src/bl602_wifi/rfc_bl602.h b/src/bl602_wifi/rfc_bl602.h index 2387da6..662a78f 100644 --- a/src/bl602_wifi/rfc_bl602.h +++ b/src/bl602_wifi/rfc_bl602.h @@ -2,4 +2,5 @@ #define _RFC_BL602_H_ uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power); // :1479:10 void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset); // :1643:6 +void rfc_config_channel(uint32_t channel_freq); #endif \ No newline at end of file From 7144472877a0fe49be1083ca5fb93222f56ae41d Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 04:07:15 -0500 Subject: [PATCH 052/148] typo --- src/bl602_wifi/phy_trpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/bl602_wifi/phy_trpc.c b/src/bl602_wifi/phy_trpc.c index cd7a453..34b34f4 100644 --- a/src/bl602_wifi/phy_trpc.c +++ b/src/bl602_wifi/phy_trpc.c @@ -48,7 +48,7 @@ uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm) { uint32_t z = (y + x) & 0xff; if (z > 0xf) z = 0xf; - return x << 2; + return z << 2; } int8_t trpc_get_rf_max_power() { From 306eed0adee7cc02404f968f67f0ba6605067150 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 25 Jul 2021 18:56:49 -0500 Subject: [PATCH 053/148] update phy --- src/bl602_wifi/phy_trpc.c | 9 +- src/bl602_wifi/rfc_bl602.c | 169 +++++++++++++++++++++++++++++++++++++ src/bl602_wifi/rfc_bl602.h | 3 + src/bl602_wifi/utils.h | 1 + 4 files changed, 176 insertions(+), 6 deletions(-) create mode 100644 src/bl602_wifi/rfc_bl602.c diff --git a/src/bl602_wifi/phy_trpc.c b/src/bl602_wifi/phy_trpc.c index 34b34f4..ca204b4 100644 --- a/src/bl602_wifi/phy_trpc.c +++ b/src/bl602_wifi/phy_trpc.c @@ -40,12 +40,9 @@ uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm) { pwr = MIN(pwr, pwr_dbm); pwr = MIN(pwr, txpwr_vs_rate_table[formatmod][mcs]); pwr = MAX(pwr, trpc_env.power_dbm_min_rf); - int x = (int)(((double)((int)(pwr * -510 + trpc_env.power_dbm_max_rf) / 512)) + (double)0.5) & 0xff; - int y = 3; - if (formatmod) { - y = 0; - } - uint32_t z = (y + x) & 0xff; + uint8_t z = trpc_env.power_dbm_max_rf - pwr; + if (formatmod == PHY_FORMATMOD_11B) + z += 3; if (z > 0xf) z = 0xf; return z << 2; diff --git a/src/bl602_wifi/rfc_bl602.c b/src/bl602_wifi/rfc_bl602.c new file mode 100644 index 0000000..c16622e --- /dev/null +++ b/src/bl602_wifi/rfc_bl602.c @@ -0,0 +1,169 @@ + +#include "rfc_bl602.h" +#include "bl602_rf_private.h" +#include "utils.h" + +#include + +void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset){ + rf_pri_update_tx_power_offset(channel, power_offset); + uint32_t rfg_index, dg; + rf_pri_query_txgain_table(0, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc0 = rfg_index & 7; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc0 = dg; + rf_pri_query_txgain_table(1, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc1 = rfg_index & 7; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc1 = dg; + rf_pri_query_txgain_table(2, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc2 = rfg_index & 7; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc2 = dg; + rf_pri_query_txgain_table(3, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc3 = rfg_index & 7; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc3 = dg; + rf_pri_query_txgain_table(4, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc4 = rfg_index & 7; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc4 = dg; + rf_pri_query_txgain_table(5, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc5 = rfg_index & 7; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc5 = dg; + rf_pri_query_txgain_table(6, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc6 = rfg_index & 7; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc6 = dg; + rf_pri_query_txgain_table(7, &rfg_index, &dg); + RF->dfe_ctrl_16.rf_tbb_ind_gc7 = rfg_index & 7; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc7 = dg; + rf_pri_query_txgain_table(8, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc8 = rfg_index & 7; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc8 = dg; + rf_pri_query_txgain_table(9, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc9 = rfg_index & 7; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc9 = dg; + rf_pri_query_txgain_table(10, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc10 = rfg_index & 7; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc10 = dg; + rf_pri_query_txgain_table(11, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc11 = rfg_index & 7; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc11 = dg; + rf_pri_query_txgain_table(12, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc12 = rfg_index & 7; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc12 = dg; + rf_pri_query_txgain_table(13, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc13 = rfg_index & 7; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc13 = dg; + rf_pri_query_txgain_table(14, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc14 = rfg_index & 7; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc14 = dg; + rf_pri_query_txgain_table(15, &rfg_index, &dg); + RF->dfe_ctrl_17.rf_tbb_ind_gc15 = rfg_index & 7; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc15 = dg; + +} + + + +void rfc_apply_tx_dvga(int8_t *dvga_qdb) { + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc0 = dvga_qdb[0]; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc1 = dvga_qdb[1]; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc2 = dvga_qdb[2]; + RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc3 = dvga_qdb[3]; + + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc4 = dvga_qdb[4]; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc5 = dvga_qdb[5]; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc6 = dvga_qdb[6]; + RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc7 = dvga_qdb[7]; + + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc8 = dvga_qdb[8]; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc9 = dvga_qdb[9]; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc10 = dvga_qdb[10]; + RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc11 = dvga_qdb[11]; + + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc12 = dvga_qdb[12]; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc13 = dvga_qdb[13]; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc14 = dvga_qdb[14]; + RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc15 = dvga_qdb[15]; +} + +void rfc_coex_force_to(uint32_t force_enable, uint32_t bbmode) { + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; + wait_us(10); + RF->rfif_dfe_ctrl0.bbmode_4s = bbmode & 1; + RF->rfif_dfe_ctrl0.bbmode_4s_en = (force_enable != 0); +} + +void rfc_config_channel(uint32_t channel_freq) { + RF->rfif_dig_ctrl.rfif_int_lo_unlocked_mask = 1; + RF->rfctrl_hw_en.lo_ctrl_hw = 1; + RF->rfctrl_hw_en.sdm_ctrl_hw = 1; + RF->rfctrl_hw_en.pu_ctrl_hw = 1; + RF->rf_fsm_ctrl0.rf_ch_ind_wifi = channel_freq & 0xfff; + RF->rf_fsm_ctrl1.rf_fsm_lo_rdy_rst = 1; + wait_us(10); + RF->rf_fsm_ctrl1.rf_fsm_lo_rdy_rst = 0; + wait_us(10); + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; + wait_us(10); + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 1; + wait_us(10); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg = 1; + wait_us(10); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 1; + wait_us(10); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg = 2; + wait_us(100); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 0; + wait_us(10); + _print_channel_info(); + rf_pri_update_param(channel_freq); + uint8_t ncf_on; + int32_t ncf_freq_Hz; + rf_pri_get_notch_param(channel_freq, &ncf_on, (int32_t *)&ncf_freq_Hz); + double freq = ncf_freq_Hz; + freq /= 40000000.0; + freq *= 256.0; + freq += 0.5; + int32_t new_freq = freq; + rfc_rxdfe_set_notch0(ncf_on, 1, new_freq); + RF->rfif_dig_ctrl.rfif_int_lo_unlocked_mask = 0; +} + +uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power) { + if (formatmod > 2) + formatmod = 0; + return rf_pri_get_txgain_index(power, formatmod) << 2; +} + +void rfc_init(uint32_t xtalfreq_hz) { + RF->rfif_dfe_ctrl0.bbmode_4s = 0; + RF->rfif_dfe_ctrl0.bbmode_4s_en = 1; + int xtal_mode = 2; + if (xtalfreq_hz != 32000000) { + if (xtalfreq_hz < 0x1e84801) { + xtal_mode = 0; + if (xtalfreq_hz == 24000000) { + xtal_mode = 1; + } else { + xtal_mode = 4; + } + } else { + if (xtalfreq_hz != 40000000) { + xtal_mode = 5; + if (xtalfreq_hz != 52000000) { + if (xtalfreq_hz == 38400000) { + xtal_mode = 3; + } else { + xtal_mode = 4; + } + } + } + } + } +} + +void _print_channel_info() { + for (int i = 0; i < 8; i++) { + wait_us(1000); + } + for (int i = 0; i < 8; i++) { + wait_us(1000); + } +} \ No newline at end of file diff --git a/src/bl602_wifi/rfc_bl602.h b/src/bl602_wifi/rfc_bl602.h index 662a78f..51987a9 100644 --- a/src/bl602_wifi/rfc_bl602.h +++ b/src/bl602_wifi/rfc_bl602.h @@ -1,6 +1,9 @@ #ifndef _RFC_BL602_H_ #define _RFC_BL602_H_ +#include uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power); // :1479:10 void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset); // :1643:6 void rfc_config_channel(uint32_t channel_freq); +void rfc_apply_tx_dvga(int8_t *dvga_qdb); +void _print_channel_info(); #endif \ No newline at end of file diff --git a/src/bl602_wifi/utils.h b/src/bl602_wifi/utils.h index 6a71b76..0129ee6 100644 --- a/src/bl602_wifi/utils.h +++ b/src/bl602_wifi/utils.h @@ -6,4 +6,5 @@ int puts(char *s); int printf(char *fmt,...); void* memset(void *, int, long unsigned int); void* memcpy(void*, const void*, unsigned int); +void wait_us(uint32_t us); #endif \ No newline at end of file From c2828b0247129bfa6b970772b8f3ff1776ea1a27 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Mon, 26 Jul 2021 00:10:32 -0500 Subject: [PATCH 054/148] update rf header --- src/include/soc/rf.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/include/soc/rf.h b/src/include/soc/rf.h index a0061d4..ee0c812 100644 --- a/src/include/soc/rf.h +++ b/src/include/soc/rf.h @@ -1915,6 +1915,19 @@ typedef union { uint32_t pad2 : 9; }; } dfe_ctrl_18; // @ 0x648 + uint8_t pad4[0xb4]; + union { + uint32_t value; + struct { + uint32_t rf_rx_notch0_alpha : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t rf_rx_notch1_alpha : 3; // @ 5 -- 3 # 0xffffffc7 + uint32_t rf_rx_notch0_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t rf_rx_notch1_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t rf_rx_notch0_nrmfc : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t rf_rx_notch1_nrmfc : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad0 : 8; + }; + } r0x1700; // @ 0x700 }; } rf_regs; #define RF_BASE 0x40001000 From ddf961547b39f7ccd8526057f7ce0c66f7a48ae1 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Fri, 30 Jul 2021 00:04:50 -0500 Subject: [PATCH 055/148] back to * -510 --- src/bl602_wifi/phy_trpc.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/bl602_wifi/phy_trpc.c b/src/bl602_wifi/phy_trpc.c index ca204b4..ac39fe9 100644 --- a/src/bl602_wifi/phy_trpc.c +++ b/src/bl602_wifi/phy_trpc.c @@ -40,12 +40,15 @@ uint8_t trpc_get_power_idx(uint8_t formatmod, uint8_t mcs, int8_t pwr_dbm) { pwr = MIN(pwr, pwr_dbm); pwr = MIN(pwr, txpwr_vs_rate_table[formatmod][mcs]); pwr = MAX(pwr, trpc_env.power_dbm_min_rf); - uint8_t z = trpc_env.power_dbm_max_rf - pwr; + int x = (int)(((double)((int)(pwr * -510 + trpc_env.power_dbm_max_rf) / 512)) + (double)0.5) & 0xff; + if (formatmod == PHY_FORMATMOD_11B) - z += 3; - if (z > 0xf) - z = 0xf; - return z << 2; + x += 3; + x &= 0xff; + if (x > 0xf) + x = 0xf; + + return x << 2; } int8_t trpc_get_rf_max_power() { From 29e8a774cfddbd64ae2d9b12963f2263ff4cd176 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 22 Sep 2021 01:51:45 -0500 Subject: [PATCH 056/148] fix ; --- src/bl602_wifi/utils.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/bl602_wifi/utils.h b/src/bl602_wifi/utils.h index 0129ee6..932abb2 100644 --- a/src/bl602_wifi/utils.h +++ b/src/bl602_wifi/utils.h @@ -7,4 +7,5 @@ int printf(char *fmt,...); void* memset(void *, int, long unsigned int); void* memcpy(void*, const void*, unsigned int); void wait_us(uint32_t us); +void BL602_Delay_US(uint32_t cnt); #endif \ No newline at end of file From ceb548b6cc13ef24949cedbd9c1f84f3c03e4f5c Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 28 Oct 2021 00:43:00 -0500 Subject: [PATCH 057/148] headers for SOC --- src/include/soc/HBN.h | 209 +++++++++++ src/include/soc/cci.h | 50 +++ src/include/soc/cks.h | 30 ++ src/include/soc/dma.h | 304 ++++++++++++++++ src/include/soc/ef_ctrl.h | 190 ++++++++++ src/include/soc/ef_data_0.h | 238 +++++++++++++ src/include/soc/ef_data_1.h | 130 +++++++ src/include/soc/gpip.h | 82 +++++ src/include/soc/i2c.h | 142 ++++++++ src/include/soc/ir.h | 195 +++++++++++ src/include/soc/l1c.h | 84 +++++ src/include/soc/pds.h | 284 +++++++++++++++ src/include/soc/pwm.h | 267 +++++++++++++++ src/include/soc/sec_dbg.h | 62 ++++ src/include/soc/sec_eng.h | 624 +++++++++++++++++++++++++++++++++ src/include/soc/sf_ctrl.h | 667 ++++++++++++++++++++++++++++++++++++ src/include/soc/spi.h | 139 ++++++++ src/include/soc/timer.h | 284 +++++++++++++++ src/include/soc/tzc_nsec.h | 62 ++++ src/include/soc/tzc_sec.h | 62 ++++ src/include/soc/uart.h | 192 +++++++++++ 21 files changed, 4297 insertions(+) create mode 100644 src/include/soc/HBN.h create mode 100644 src/include/soc/cci.h create mode 100644 src/include/soc/cks.h create mode 100644 src/include/soc/dma.h create mode 100644 src/include/soc/ef_ctrl.h create mode 100644 src/include/soc/ef_data_0.h create mode 100644 src/include/soc/ef_data_1.h create mode 100644 src/include/soc/gpip.h create mode 100644 src/include/soc/i2c.h create mode 100644 src/include/soc/ir.h create mode 100644 src/include/soc/l1c.h create mode 100644 src/include/soc/pds.h create mode 100644 src/include/soc/pwm.h create mode 100644 src/include/soc/sec_dbg.h create mode 100644 src/include/soc/sec_eng.h create mode 100644 src/include/soc/sf_ctrl.h create mode 100644 src/include/soc/spi.h create mode 100644 src/include/soc/timer.h create mode 100644 src/include/soc/tzc_nsec.h create mode 100644 src/include/soc/tzc_sec.h create mode 100644 src/include/soc/uart.h diff --git a/src/include/soc/HBN.h b/src/include/soc/HBN.h new file mode 100644 index 0000000..819f0e5 --- /dev/null +++ b/src/include/soc/HBN.h @@ -0,0 +1,209 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t rtc_ctl : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t hbn_mode : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t trap_mode : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pwrdn_hbn_core : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 1; + uint32_t pwrdn_hbn_rtc : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t sw_rst : 1; // @ 12 -- 12 # 0xffffefff + uint32_t hbn_dis_pwr_off_ldo11 : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t hbn_dis_pwr_off_ldo11_rt : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t hbn_ldo11_rt_vout_sel : 4; // @ 18 -- 15 # 0xfff87fff + uint32_t hbn_ldo11_aon_vout_sel : 4; // @ 22 -- 19 # 0xff87ffff + uint32_t pu_dcdc18_aon : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t rtc_dly_option : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pwr_on_option : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t sram_slp_option : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t sram_slp : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t hbn_state : 4; // @ 31 -- 28 # 0xfffffff + }; + } HBN_CTL; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t hbn_time_l : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_TIME_L; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t hbn_time_h : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } HBN_TIME_H; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t rtc_time_latch_l : 32; // @ 31 -- 0 # 0x0 + }; + } RTC_TIME_L; // @ 0xc + union { + uint32_t value; + struct { + uint32_t rtc_time_latch_h : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 23; + uint32_t rtc_time_latch : 1; // @ 31 -- 31 # 0x7fffffff + }; + } RTC_TIME_H; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t hbn_pin_wakeup_mode : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t hbn_pin_wakeup_mask : 2; // @ 4 -- 3 # 0xffffffe7 + uint32_t pad0 : 3; + uint32_t reg_aon_pad_ie_smt : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 7; + uint32_t reg_en_hw_pu_pd : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 1; + uint32_t irq_bor_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad3 : 1; + uint32_t irq_acomp0_en : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t irq_acomp1_en : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t pin_wakeup_sel : 3; // @ 26 -- 24 # 0xf8ffffff + uint32_t pin_wakeup_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t pad4 : 4; + }; + } HBN_IRQ_MODE; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t irq_stat : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_IRQ_STAT; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t irq_clr : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_IRQ_CLR; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t pir_hpf_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pir_lpf_sel : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 1; + uint32_t pir_dis : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 1; + uint32_t pir_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t gpadc_cgen : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t gpadc_nosync : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad2 : 22; + }; + } HBN_PIR_CFG; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t pir_vth : 14; // @ 13 -- 0 # 0xffffc000 + uint32_t pad0 : 18; + }; + } HBN_PIR_VTH; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t pir_interval : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 20; + }; + } HBN_PIR_INTERVAL; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t bor_sel : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t bor_vth : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pu_bor : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t r_bor_out : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; + }; + } HBN_BOR_CFG; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t hbn_root_clk_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t hbn_uart_clk_sel : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t hbn_f32k_sel : 2; // @ 4 -- 3 # 0xffffffe7 + uint32_t hbn_pu_rc32k : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 10; + uint32_t sw_ldo11soc_vout_sel_aon : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t pad1 : 4; + uint32_t sw_ldo11_rt_vout_sel : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t sw_ldo11_aon_vout_sel : 4; // @ 31 -- 28 # 0xfffffff + }; + } HBN_GLB; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t pad0 : 6; + uint32_t retram_ret : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t retram_slp : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad1 : 24; + }; + } HBN_SRAM; // @ 0x34 + uint8_t pad0[0xc8]; + union { + uint32_t value; + struct { + uint32_t HBN_RSV0 : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_RSV0; // @ 0x100 + union { + uint32_t value; + struct { + uint32_t HBN_RSV1 : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_RSV1; // @ 0x104 + union { + uint32_t value; + struct { + uint32_t HBN_RSV2 : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_RSV2; // @ 0x108 + union { + uint32_t value; + struct { + uint32_t HBN_RSV3 : 32; // @ 31 -- 0 # 0x0 + }; + } HBN_RSV3; // @ 0x10c + uint8_t pad1[0xf0]; + union { + uint32_t value; + struct { + uint32_t rc32k_cal_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rc32k_rdy : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rc32k_cal_inprogress : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rc32k_cal_div : 2; // @ 4 -- 3 # 0xffffffe7 + uint32_t rc32k_cal_precharge : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rc32k_dig_code_fr_cal : 10; // @ 15 -- 6 # 0xffff003f + uint32_t rc32k_vref_dly : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t rc32k_allow_cal : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t rc32k_ext_code_en : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t rc32k_cal_en : 1; // @ 20 -- 20 # 0xffefffff + uint32_t pad0 : 1; + uint32_t rc32k_code_fr_ext : 10; // @ 31 -- 22 # 0x3fffff + }; + } rc32k_ctrl0; // @ 0x200 + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t xtal32k_ext_sel : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t xtal32k_amp_ctrl : 2; // @ 4 -- 3 # 0xffffffe7 + uint32_t xtal32k_reg : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t xtal32k_outbuf_stre : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t xtal32k_otf_short : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t xtal32k_inv_stre : 2; // @ 10 -- 9 # 0xfffff9ff + uint32_t xtal32k_capbank : 6; // @ 16 -- 11 # 0xfffe07ff + uint32_t xtal32k_ac_cap_short : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t pu_xtal32k_buf : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pu_xtal32k : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pad1 : 12; + }; + } xtal32k; // @ 0x204 + }; +} HBN_regs; +#define HBN_BASE 0x4000f000 +#define HBN ((HBN_regs* volatile)(HBN_BASE)) \ No newline at end of file diff --git a/src/include/soc/cci.h b/src/include/soc/cci.h new file mode 100644 index 0000000..d9d4def --- /dev/null +++ b/src/include/soc/cci.h @@ -0,0 +1,50 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t cci_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cci_slv_sel_cci2 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cci_mas_sel_cci2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cci_mas_hw_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t reg_m_cci_sclk_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t reg_div_m_cci_sclk : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t cfg_cci1_pre_read : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t reg_scci_clk_inv : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t reg_mcci_clk_inv : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 22; + }; + } cci_cfg; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t apb_cci_addr : 32; // @ 31 -- 0 # 0x0 + }; + } cci_addr; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t apb_cci_wdata : 32; // @ 31 -- 0 # 0x0 + }; + } cci_wdata; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t apb_cci_rdata : 32; // @ 31 -- 0 # 0x0 + }; + } cci_rdata; // @ 0xc + union { + uint32_t value; + struct { + uint32_t cci_write_flag : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cci_read_flag : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t ahb_state : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t pad0 : 28; + }; + } cci_ctl; // @ 0x10 + }; +} cci_regs; +#define CCI_BASE 0x40008000 +#define CCI ((cci_regs* volatile)(CCI_BASE)) \ No newline at end of file diff --git a/src/include/soc/cks.h b/src/include/soc/cks.h new file mode 100644 index 0000000..474e844 --- /dev/null +++ b/src/include/soc/cks.h @@ -0,0 +1,30 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t cr_cks_clr : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_cks_byte_swap : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; + }; + } cks_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t data_in : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } data_in; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t cks_out : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } cks_out; // @ 0x8 + }; +} cks_regs; +#define CKS_BASE 0x4000a000 +#define CKS ((cks_regs* volatile)(CKS_BASE)) \ No newline at end of file diff --git a/src/include/soc/dma.h b/src/include/soc/dma.h new file mode 100644 index 0000000..8b88f88 --- /dev/null +++ b/src/include/soc/dma.h @@ -0,0 +1,304 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t IntStatus : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_IntStatus; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t IntTCStatus : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_IntTCStatus; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t IntTCClear : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_IntTCClear; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t IntErrorStatus : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_IntErrorStatus; // @ 0xc + union { + uint32_t value; + struct { + uint32_t IntErrClr : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_IntErrClr; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t RawIntTCStatus : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_RawIntTCStatus; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t RawIntErrorStatus : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_RawIntErrorStatus; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t EnabledChannels : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } DMA_EnbldChns; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t SoftBReq : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_SoftBReq; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t SoftSReq : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_SoftSReq; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t SoftLBReq : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_SoftLBReq; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t SoftLSReq : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_SoftLSReq; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t E : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t M : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; + }; + } DMA_Top_Config; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t DMA_Sync : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_Sync; // @ 0x34 + uint8_t pad0[0xc8]; + union { + uint32_t value; + struct { + uint32_t SrcAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C0SrcAddr; // @ 0x100 + union { + uint32_t value; + struct { + uint32_t DstAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C0DstAddr; // @ 0x104 + union { + uint32_t value; + struct { + uint32_t LLI : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C0LLI; // @ 0x108 + union { + uint32_t value; + struct { + uint32_t TransferSize : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t SBSize : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t DBSize : 3; // @ 17 -- 15 # 0xfffc7fff + uint32_t SWidth : 3; // @ 20 -- 18 # 0xffe3ffff + uint32_t DWidth : 3; // @ 23 -- 21 # 0xff1fffff + uint32_t SLargerD : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad0 : 1; + uint32_t SI : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t DI : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t Prot : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t I : 1; // @ 31 -- 31 # 0x7fffffff + }; + } DMA_C0Control; // @ 0x10c + union { + uint32_t value; + struct { + uint32_t E : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t SrcPeripheral : 5; // @ 5 -- 1 # 0xffffffc1 + uint32_t DstPeripheral : 5; // @ 10 -- 6 # 0xfffff83f + uint32_t FlowCntrl : 3; // @ 13 -- 11 # 0xffffc7ff + uint32_t IE : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ITC : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t L : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t A : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t H : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad0 : 1; + uint32_t LLICounter : 10; // @ 29 -- 20 # 0xc00fffff + uint32_t pad1 : 2; + }; + } DMA_C0Config; // @ 0x110 + uint8_t pad1[0xec]; + union { + uint32_t value; + struct { + uint32_t SrcAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C1SrcAddr; // @ 0x200 + union { + uint32_t value; + struct { + uint32_t DstAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C1DstAddr; // @ 0x204 + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t LLI : 30; // @ 31 -- 2 # 0x3 + }; + } DMA_C1LLI; // @ 0x208 + union { + uint32_t value; + struct { + uint32_t TransferSize : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t SBSize : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t DBSize : 3; // @ 17 -- 15 # 0xfffc7fff + uint32_t SWidth : 3; // @ 20 -- 18 # 0xffe3ffff + uint32_t DWidth : 3; // @ 23 -- 21 # 0xff1fffff + uint32_t pad0 : 2; + uint32_t SI : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t DI : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t Prot : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t I : 1; // @ 31 -- 31 # 0x7fffffff + }; + } DMA_C1Control; // @ 0x20c + union { + uint32_t value; + struct { + uint32_t E : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t SrcPeripheral : 5; // @ 5 -- 1 # 0xffffffc1 + uint32_t DstPeripheral : 5; // @ 10 -- 6 # 0xfffff83f + uint32_t FlowCntrl : 3; // @ 13 -- 11 # 0xffffc7ff + uint32_t IE : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ITC : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t L : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t A : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t H : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad0 : 13; + }; + } DMA_C1Config; // @ 0x210 + uint8_t pad2[0xec]; + union { + uint32_t value; + struct { + uint32_t SrcAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C2SrcAddr; // @ 0x300 + union { + uint32_t value; + struct { + uint32_t DstAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C2DstAddr; // @ 0x304 + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t LLI : 30; // @ 31 -- 2 # 0x3 + }; + } DMA_C2LLI; // @ 0x308 + union { + uint32_t value; + struct { + uint32_t TransferSize : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t SBSize : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t DBSize : 3; // @ 17 -- 15 # 0xfffc7fff + uint32_t SWidth : 3; // @ 20 -- 18 # 0xffe3ffff + uint32_t DWidth : 3; // @ 23 -- 21 # 0xff1fffff + uint32_t pad0 : 2; + uint32_t SI : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t DI : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t Prot : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t I : 1; // @ 31 -- 31 # 0x7fffffff + }; + } DMA_C2Control; // @ 0x30c + union { + uint32_t value; + struct { + uint32_t E : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t SrcPeripheral : 5; // @ 5 -- 1 # 0xffffffc1 + uint32_t DstPeripheral : 5; // @ 10 -- 6 # 0xfffff83f + uint32_t FlowCntrl : 3; // @ 13 -- 11 # 0xffffc7ff + uint32_t IE : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ITC : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t L : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t A : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t H : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad0 : 13; + }; + } DMA_C2Config; // @ 0x310 + uint8_t pad3[0xec]; + union { + uint32_t value; + struct { + uint32_t SrcAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C3SrcAddr; // @ 0x400 + union { + uint32_t value; + struct { + uint32_t DstAddr : 32; // @ 31 -- 0 # 0x0 + }; + } DMA_C3DstAddr; // @ 0x404 + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t LLI : 30; // @ 31 -- 2 # 0x3 + }; + } DMA_C3LLI; // @ 0x408 + union { + uint32_t value; + struct { + uint32_t TransferSize : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t SBSize : 3; // @ 14 -- 12 # 0xffff8fff + uint32_t DBSize : 3; // @ 17 -- 15 # 0xfffc7fff + uint32_t SWidth : 3; // @ 20 -- 18 # 0xffe3ffff + uint32_t DWidth : 3; // @ 23 -- 21 # 0xff1fffff + uint32_t pad0 : 2; + uint32_t SI : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t DI : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t Prot : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t I : 1; // @ 31 -- 31 # 0x7fffffff + }; + } DMA_C3Control; // @ 0x40c + union { + uint32_t value; + struct { + uint32_t E : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t SrcPeripheral : 5; // @ 5 -- 1 # 0xffffffc1 + uint32_t DstPeripheral : 5; // @ 10 -- 6 # 0xfffff83f + uint32_t FlowCntrl : 3; // @ 13 -- 11 # 0xffffc7ff + uint32_t IE : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ITC : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t L : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t A : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t H : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad0 : 13; + }; + } DMA_C3Config; // @ 0x410 + }; +} dma_regs; +#define DMA_BASE 0x4000c000 +#define DMA ((dma_regs* volatile)(DMA_BASE)) \ No newline at end of file diff --git a/src/include/soc/ef_ctrl.h b/src/include/soc/ef_ctrl.h new file mode 100644 index 0000000..b2ef074 --- /dev/null +++ b/src/include/soc/ef_ctrl.h @@ -0,0 +1,190 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + uint8_t pad0[0x800]; + union { + uint32_t value; + struct { + uint32_t ef_if_0_autoload_p1_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t ef_if_0_autoload_done : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t ef_if_0_busy : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t ef_if_0_rw : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t ef_if_0_trig : 1; // @ 4 -- 4 # 0xffffffef + uint32_t ef_if_0_manual_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t ef_if_0_cyc_modify : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t ef_clk_sahb_data_sel : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t ef_if_prot_code_ctrl : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t ef_if_por_dig : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t ef_clk_sahb_data_gate : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t ef_if_auto_rd_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ef_if_cyc_modify_lock : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ef_if_0_int : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ef_if_0_int_clr : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t ef_if_0_int_set : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad0 : 1; + uint32_t ef_if_prot_code_cyc : 8; // @ 31 -- 24 # 0xffffff + }; + } ef_if_ctrl_0; // @ 0x800 + union { + uint32_t value; + struct { + uint32_t ef_if_cyc_rd_dmy : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t ef_if_cyc_rd_dat : 6; // @ 11 -- 6 # 0xfffff03f + uint32_t ef_if_cyc_rd_adr : 6; // @ 17 -- 12 # 0xfffc0fff + uint32_t ef_if_cyc_cs : 6; // @ 23 -- 18 # 0xff03ffff + uint32_t ef_if_cyc_pd_cs_s : 8; // @ 31 -- 24 # 0xffffff + }; + } ef_if_cyc_0; // @ 0x804 + union { + uint32_t value; + struct { + uint32_t ef_if_cyc_pi : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t ef_if_cyc_pp : 8; // @ 13 -- 6 # 0xffffc03f + uint32_t ef_if_cyc_wr_adr : 6; // @ 19 -- 14 # 0xfff03fff + uint32_t ef_if_cyc_ps_cs : 6; // @ 25 -- 20 # 0xfc0fffff + uint32_t ef_if_cyc_pd_cs_h : 6; // @ 31 -- 26 # 0x3ffffff + }; + } ef_if_cyc_1; // @ 0x808 + union { + uint32_t value; + struct { + uint32_t ef_if_a : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t ef_if_pd : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t ef_if_ps : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t ef_if_strobe : 1; // @ 12 -- 12 # 0xffffefff + uint32_t ef_if_pgenb : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t ef_if_load : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ef_if_csb : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t ef_if_0_q : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t ef_if_prot_code_manual : 8; // @ 31 -- 24 # 0xffffff + }; + } ef_if_0_manual; // @ 0x80c + union { + uint32_t value; + struct { + uint32_t ef_if_0_status : 32; // @ 31 -- 0 # 0x0 + }; + } ef_if_0_status; // @ 0x810 + union { + uint32_t value; + struct { + uint32_t ef_if_sf_aes_mode : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t ef_if_sboot_sign_mode : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t ef_if_sboot_en : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t ef_if_cpu1_enc_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t ef_if_cpu0_enc_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t ef_if_boot_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t ef_if_sw_usage_1 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t ef_if_sdu_dis : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ef_if_ble_dis : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t ef_if_wifi_dis : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t ef_if_0_key_enc_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t ef_if_cam_dis : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ef_if_sf_dis : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ef_if_cpu1_dis : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ef_if_cpu_rst_dbg_dis : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t ef_if_se_dbg_dis : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t ef_if_efuse_dbg_dis : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t ef_if_dbg_jtag_1_dis : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t ef_if_dbg_jtag_0_dis : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t ef_if_dbg_mode : 4; // @ 31 -- 28 # 0xfffffff + }; + } ef_if_cfg_0; // @ 0x814 + union { + uint32_t value; + struct { + uint32_t ef_sw_sf_aes_mode : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t ef_sw_sboot_sign_mode : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t ef_sw_sboot_en : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t ef_sw_cpu1_enc_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t ef_sw_cpu0_enc_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 4; + uint32_t ef_sw_sw_usage_1 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t ef_sw_sdu_dis : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ef_sw_ble_dis : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t ef_sw_wifi_dis : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t ef_sw_0_key_enc_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t ef_sw_cam_dis : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ef_sw_sf_dis : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ef_sw_cpu1_dis : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ef_sw_cpu_rst_dbg_dis : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t ef_sw_se_dbg_dis : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t ef_sw_efuse_dbg_dis : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t ef_sw_dbg_jtag_1_dis : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t ef_sw_dbg_jtag_0_dis : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t ef_sw_dbg_mode : 4; // @ 31 -- 28 # 0xfffffff + }; + } ef_sw_cfg_0; // @ 0x818 + union { + uint32_t value; + struct { + uint32_t ef_reserved : 32; // @ 31 -- 0 # 0x0 + }; + } ef_reserved; // @ 0x81c + union { + uint32_t value; + struct { + uint32_t ef_if_ana_trim_0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_if_ana_trim_0; // @ 0x820 + union { + uint32_t value; + struct { + uint32_t ef_if_sw_usage_0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_if_sw_usage_0; // @ 0x824 + uint8_t pad1[0x1d8]; + union { + uint32_t value; + struct { + uint32_t ef_crc_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t ef_crc_trig : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t ef_crc_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t ef_crc_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t ef_crc_error : 1; // @ 4 -- 4 # 0xffffffef + uint32_t ef_crc_dout_inv_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t ef_crc_dout_endian : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t ef_crc_din_endian : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t ef_crc_int : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t ef_crc_int_clr : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t ef_crc_int_set : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t ef_crc_lock : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad0 : 4; + uint32_t ef_crc_slp_n : 16; // @ 31 -- 16 # 0xffff + }; + } ef_crc_ctrl_0; // @ 0xa00 + union { + uint32_t value; + struct { + uint32_t ef_crc_data_0_en : 32; // @ 31 -- 0 # 0x0 + }; + } ef_crc_ctrl_1; // @ 0xa04 + union { + uint32_t value; + struct { + uint32_t ef_crc_data_1_en : 32; // @ 31 -- 0 # 0x0 + }; + } ef_crc_ctrl_2; // @ 0xa08 + union { + uint32_t value; + struct { + uint32_t ef_crc_iv : 32; // @ 31 -- 0 # 0x0 + }; + } ef_crc_ctrl_3; // @ 0xa0c + union { + uint32_t value; + struct { + uint32_t ef_crc_golden : 32; // @ 31 -- 0 # 0x0 + }; + } ef_crc_ctrl_4; // @ 0xa10 + union { + uint32_t value; + struct { + uint32_t ef_crc_dout : 32; // @ 31 -- 0 # 0x0 + }; + } ef_crc_ctrl_5; // @ 0xa14 + }; +} ef_ctrl_regs; +#define EF_CTRL_BASE 0x40007000 +#define EF_CTRL ((ef_ctrl_regs* volatile)(EF_CTRL_BASE)) \ No newline at end of file diff --git a/src/include/soc/ef_data_0.h b/src/include/soc/ef_data_0.h new file mode 100644 index 0000000..612e008 --- /dev/null +++ b/src/include/soc/ef_data_0.h @@ -0,0 +1,238 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t ef_sf_aes_mode : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t ef_sboot_sign_mode : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t ef_sboot_en : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t ef_cpu1_enc_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t ef_cpu0_enc_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t ef_boot_sel : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t ef_sw_usage_1 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t ef_sdu_dis : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t ef_ble_dis : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t ef_wifi_dis : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t ef_0_key_enc_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t ef_cam_dis : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t ef_sf_dis : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t ef_cpu1_dis : 1; // @ 20 -- 20 # 0xffefffff + uint32_t ef_cpu_rst_dbg_dis : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t ef_se_dbg_dis : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t ef_efuse_dbg_dis : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t ef_dbg_jtag_1_dis : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t ef_dbg_jtag_0_dis : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t ef_dbg_mode : 4; // @ 31 -- 28 # 0xfffffff + }; + } ef_cfg_0; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t ef_dbg_pwd_low : 32; // @ 31 -- 0 # 0x0 + }; + } ef_dbg_pwd_low; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t ef_dbg_pwd_high : 32; // @ 31 -- 0 # 0x0 + }; + } ef_dbg_pwd_high; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t ef_ana_trim_0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_ana_trim_0; // @ 0xc + union { + uint32_t value; + struct { + uint32_t ef_sw_usage_0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_sw_usage_0; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t ef_wifi_mac_low : 32; // @ 31 -- 0 # 0x0 + }; + } ef_wifi_mac_low; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t ef_wifi_mac_high : 32; // @ 31 -- 0 # 0x0 + }; + } ef_wifi_mac_high; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_0_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_0_w0; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t ef_key_slot_0_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_0_w1; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_0_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_0_w2; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_0_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_0_w3; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_1_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_1_w0; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t ef_key_slot_1_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_1_w1; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_1_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_1_w2; // @ 0x34 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_1_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_1_w3; // @ 0x38 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_2_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_2_w0; // @ 0x3c + union { + uint32_t value; + struct { + uint32_t ef_key_slot_2_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_2_w1; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_2_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_2_w2; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_2_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_2_w3; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_3_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_3_w0; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t ef_key_slot_3_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_3_w1; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_3_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_3_w2; // @ 0x54 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_3_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_3_w3; // @ 0x58 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_4_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_4_w0; // @ 0x5c + union { + uint32_t value; + struct { + uint32_t ef_key_slot_4_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_4_w1; // @ 0x60 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_4_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_4_w2; // @ 0x64 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_4_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_4_w3; // @ 0x68 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_5_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_5_w0; // @ 0x6c + union { + uint32_t value; + struct { + uint32_t ef_key_slot_5_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_5_w1; // @ 0x70 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_5_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_5_w2; // @ 0x74 + union { + uint32_t value; + struct { + uint32_t ef_key_slot_5_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } ef_key_slot_5_w3; // @ 0x78 + union { + uint32_t value; + struct { + uint32_t ef_ana_trim_1 : 13; // @ 12 -- 0 # 0xffffe000 + uint32_t wr_lock_key_slot_4_l : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t wr_lock_key_slot_5_l : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t wr_lock_boot_mode : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t wr_lock_dbg_pwd : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t wr_lock_sw_usage_0 : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t wr_lock_wifi_mac : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t wr_lock_key_slot_0 : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t wr_lock_key_slot_1 : 1; // @ 20 -- 20 # 0xffefffff + uint32_t wr_lock_key_slot_2 : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t wr_lock_key_slot_3 : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t wr_lock_key_slot_4_h : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t wr_lock_key_slot_5_h : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t rd_lock_dbg_pwd : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t rd_lock_key_slot_0 : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t rd_lock_key_slot_1 : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t rd_lock_key_slot_2 : 1; // @ 28 -- 28 # 0xefffffff + uint32_t rd_lock_key_slot_3 : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t rd_lock_key_slot_4 : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t rd_lock_key_slot_5 : 1; // @ 31 -- 31 # 0x7fffffff + }; + } ef_data_0_lock; // @ 0x7c + }; +} ef_data_0_regs; +#define EF_DATA_0_BASE 0x40007000 +#define EF_DATA_0 ((ef_data_0_regs* volatile)(EF_DATA_0_BASE)) \ No newline at end of file diff --git a/src/include/soc/ef_data_1.h b/src/include/soc/ef_data_1.h new file mode 100644 index 0000000..3667e6a --- /dev/null +++ b/src/include/soc/ef_data_1.h @@ -0,0 +1,130 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + uint8_t pad0[0x80]; + union { + uint32_t value; + struct { + uint32_t reg_key_slot_6_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_6_w0; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_6_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_6_w1; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_6_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_6_w2; // @ 0x88 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_6_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_6_w3; // @ 0x8c + union { + uint32_t value; + struct { + uint32_t reg_key_slot_7_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_7_w0; // @ 0x90 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_7_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_7_w1; // @ 0x94 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_7_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_7_w2; // @ 0x98 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_7_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_7_w3; // @ 0x9c + union { + uint32_t value; + struct { + uint32_t reg_key_slot_8_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_8_w0; // @ 0xa0 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_8_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_8_w1; // @ 0xa4 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_8_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_8_w2; // @ 0xa8 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_8_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_8_w3; // @ 0xac + union { + uint32_t value; + struct { + uint32_t reg_key_slot_9_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_9_w0; // @ 0xb0 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_9_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_9_w1; // @ 0xb4 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_9_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_9_w2; // @ 0xb8 + union { + uint32_t value; + struct { + uint32_t reg_key_slot_9_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } reg_key_slot_9_w3; // @ 0xbc + uint32_t reg_key_slot_10_w0; // @ 0xc0 + uint32_t reg_key_slot_10_w1; // @ 0xc4 + uint32_t reg_key_slot_10_w2; // @ 0xc8 + uint32_t reg_key_slot_10_w3; // @ 0xcc + uint32_t reg_key_slot_11_w0; // @ 0xd0 + uint32_t reg_key_slot_11_w1; // @ 0xd4 + uint32_t reg_key_slot_11_w2; // @ 0xd8 + uint32_t reg_key_slot_11_w3; // @ 0xdc + union { + uint32_t value; + struct { + uint32_t RESERVED_9_0 : 10; // @ 9 -- 0 # 0xfffffc00 + uint32_t wr_lock_key_slot_6 : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t wr_lock_key_slot_7 : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t wr_lock_key_slot_8 : 1; // @ 12 -- 12 # 0xffffefff + uint32_t wr_lock_key_slot_9 : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad0 : 2; + uint32_t RESERVED_25_16 : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t rd_lock_key_slot_6 : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t rd_lock_key_slot_7 : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t rd_lock_key_slot_8 : 1; // @ 28 -- 28 # 0xefffffff + uint32_t rd_lock_key_slot_9 : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad1 : 2; + }; + } reg_data_1_lock; // @ 0xe0 + }; +} ef_data_1_regs; +#define EF_DATA_1_BASE 0x40007000 +#define EF_DATA_1 ((ef_data_1_regs* volatile)(EF_DATA_1_BASE)) \ No newline at end of file diff --git a/src/include/soc/gpip.h b/src/include/soc/gpip.h new file mode 100644 index 0000000..ae4f5a4 --- /dev/null +++ b/src/include/soc/gpip.h @@ -0,0 +1,82 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t gpadc_dma_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpadc_fifo_clr : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t gpadc_fifo_ne : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t gpadc_fifo_full : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t gpadc_rdy : 1; // @ 4 -- 4 # 0xffffffef + uint32_t gpadc_fifo_overrun : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t gpadc_fifo_underrun : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad0 : 1; + uint32_t gpadc_rdy_clr : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t gpadc_fifo_overrun_clr : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t gpadc_fifo_underrun_clr : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad1 : 1; + uint32_t gpadc_rdy_mask : 1; // @ 12 -- 12 # 0xffffefff + uint32_t gpadc_fifo_overrun_mask : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t gpadc_fifo_underrun_mask : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pad2 : 1; + uint32_t gpadc_fifo_data_count : 6; // @ 21 -- 16 # 0xffc0ffff + uint32_t gpadc_fifo_thl : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t rsvd_31_24 : 8; // @ 31 -- 24 # 0xffffff + }; + } gpadc_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t gpadc_dma_rdata : 26; // @ 25 -- 0 # 0xfc000000 + uint32_t rsvd_31_26 : 6; // @ 31 -- 26 # 0x3ffffff + }; + } gpadc_dma_rdata; // @ 0x4 + uint8_t pad0[0x38]; + union { + uint32_t value; + struct { + uint32_t gpdac_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t gpdac_en2 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 2; + uint32_t dsm_mode : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t gpdac_mode : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad2 : 5; + uint32_t gpdac_ch_a_sel : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t gpdac_ch_b_sel : 4; // @ 23 -- 20 # 0xff0fffff + uint32_t rsvd_31_24 : 8; // @ 31 -- 24 # 0xffffff + }; + } gpdac_config; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t gpdac_dma_tx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t gpdac_dma_format : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 26; + }; + } gpdac_dma_config; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t gpdac_dma_wdata : 32; // @ 31 -- 0 # 0x0 + }; + } gpdac_dma_wdata; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t tx_fifo_empty : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tx_fifo_full : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tx_cs : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t TxFifoRdPtr : 3; // @ 6 -- 4 # 0xffffff8f + uint32_t pad0 : 1; + uint32_t TxFifoWrPtr : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 22; + }; + } gpdac_tx_fifo_status; // @ 0x4c + }; +} gpip_regs; +#define GPIP_BASE 0x40002000 +#define GPIP ((gpip_regs* volatile)(GPIP_BASE)) \ No newline at end of file diff --git a/src/include/soc/i2c.h b/src/include/soc/i2c.h new file mode 100644 index 0000000..805c66b --- /dev/null +++ b/src/include/soc/i2c.h @@ -0,0 +1,142 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t cr_i2c_m_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_i2c_pkt_dir : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_i2c_deg_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_i2c_scl_sync_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_i2c_sub_addr_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_i2c_sub_addr_bc : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t pad0 : 1; + uint32_t cr_i2c_slv_addr : 7; // @ 14 -- 8 # 0xffff80ff + uint32_t pad1 : 1; + uint32_t cr_i2c_pkt_len : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad2 : 4; + uint32_t cr_i2c_deg_cnt : 4; // @ 31 -- 28 # 0xfffffff + }; + } i2c_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t i2c_end_int : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t i2c_txf_int : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t i2c_rxf_int : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t i2c_nak_int : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t i2c_arb_int : 1; // @ 4 -- 4 # 0xffffffef + uint32_t i2c_fer_int : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t cr_i2c_end_mask : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t cr_i2c_txf_mask : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t cr_i2c_rxf_mask : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t cr_i2c_nak_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t cr_i2c_arb_mask : 1; // @ 12 -- 12 # 0xffffefff + uint32_t cr_i2c_fer_mask : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad1 : 2; + uint32_t cr_i2c_end_clr : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t rsvd_17 : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t rsvd_18 : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t cr_i2c_nak_clr : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t cr_i2c_arb_clr : 1; // @ 20 -- 20 # 0xffefffff + uint32_t rsvd_21 : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t cr_i2c_end_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t cr_i2c_txf_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t cr_i2c_rxf_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t cr_i2c_nak_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t cr_i2c_arb_en : 1; // @ 28 -- 28 # 0xefffffff + uint32_t cr_i2c_fer_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad3 : 2; + }; + } i2c_int_sts; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t cr_i2c_sub_addr_b0 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t cr_i2c_sub_addr_b1 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t cr_i2c_sub_addr_b2 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t cr_i2c_sub_addr_b3 : 8; // @ 31 -- 24 # 0xffffff + }; + } i2c_sub_addr; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t sts_i2c_bus_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_i2c_bus_busy_clr : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; + }; + } i2c_bus_busy; // @ 0xc + union { + uint32_t value; + struct { + uint32_t cr_i2c_prd_s_ph_0 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t cr_i2c_prd_s_ph_1 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t cr_i2c_prd_s_ph_2 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t cr_i2c_prd_s_ph_3 : 8; // @ 31 -- 24 # 0xffffff + }; + } i2c_prd_start; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t cr_i2c_prd_p_ph_0 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t cr_i2c_prd_p_ph_1 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t cr_i2c_prd_p_ph_2 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t cr_i2c_prd_p_ph_3 : 8; // @ 31 -- 24 # 0xffffff + }; + } i2c_prd_stop; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t cr_i2c_prd_d_ph_0 : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t cr_i2c_prd_d_ph_1 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t cr_i2c_prd_d_ph_2 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t cr_i2c_prd_d_ph_3 : 8; // @ 31 -- 24 # 0xffffff + }; + } i2c_prd_data; // @ 0x18 + uint8_t pad0[0x64]; + union { + uint32_t value; + struct { + uint32_t i2c_dma_tx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t i2c_dma_rx_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tx_fifo_clr : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rx_fifo_clr : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t tx_fifo_overflow : 1; // @ 4 -- 4 # 0xffffffef + uint32_t tx_fifo_underflow : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rx_fifo_overflow : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t rx_fifo_underflow : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } i2c_fifo_config_0; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t tx_fifo_cnt : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t rx_fifo_cnt : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t tx_fifo_th : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 7; + uint32_t rx_fifo_th : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad3 : 7; + }; + } i2c_fifo_config_1; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t i2c_fifo_wdata : 32; // @ 31 -- 0 # 0x0 + }; + } i2c_fifo_wdata; // @ 0x88 + union { + uint32_t value; + struct { + uint32_t i2c_fifo_rdata : 32; // @ 31 -- 0 # 0x0 + }; + } i2c_fifo_rdata; // @ 0x8c + }; +} i2c_regs; +#define I2C_BASE 0x4000a300 +#define I2C ((i2c_regs* volatile)(I2C_BASE)) \ No newline at end of file diff --git a/src/include/soc/ir.h b/src/include/soc/ir.h new file mode 100644 index 0000000..c1b3a7f --- /dev/null +++ b/src/include/soc/ir.h @@ -0,0 +1,195 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t cr_irtx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_irtx_out_inv : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_irtx_mod_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_irtx_swm_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_irtx_data_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_irtx_logic0_hl_inv : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t cr_irtx_logic1_hl_inv : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad0 : 1; + uint32_t cr_irtx_head_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t cr_irtx_head_hl_inv : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t cr_irtx_tail_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t cr_irtx_tail_hl_inv : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t cr_irtx_data_num : 6; // @ 17 -- 12 # 0xfffc0fff + uint32_t pad1 : 14; + }; + } irtx_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t irtx_end_int : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 7; + uint32_t cr_irtx_end_mask : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 7; + uint32_t cr_irtx_end_clr : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 7; + uint32_t cr_irtx_end_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad3 : 7; + }; + } irtx_int_sts; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t cr_irtx_data_word0 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_data_word0; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t cr_irtx_data_word1 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_data_word1; // @ 0xc + union { + uint32_t value; + struct { + uint32_t cr_irtx_pw_unit : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 4; + uint32_t cr_irtx_mod_ph0_w : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t cr_irtx_mod_ph1_w : 8; // @ 31 -- 24 # 0xffffff + }; + } irtx_pulse_width; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t cr_irtx_logic0_ph0_w : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t cr_irtx_logic0_ph1_w : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t cr_irtx_logic1_ph0_w : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t cr_irtx_logic1_ph1_w : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t cr_irtx_head_ph0_w : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t cr_irtx_head_ph1_w : 4; // @ 23 -- 20 # 0xff0fffff + uint32_t cr_irtx_tail_ph0_w : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t cr_irtx_tail_ph1_w : 4; // @ 31 -- 28 # 0xfffffff + }; + } irtx_pw; // @ 0x14 + uint8_t pad0[0x28]; + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_0 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_0; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_1 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_1; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_2 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_2; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_3 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_3; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_4 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_4; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_5 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_5; // @ 0x54 + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_6 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_6; // @ 0x58 + union { + uint32_t value; + struct { + uint32_t cr_irtx_swm_pw_7 : 32; // @ 31 -- 0 # 0x0 + }; + } irtx_swm_pw_7; // @ 0x5c + uint8_t pad1[0x20]; + union { + uint32_t value; + struct { + uint32_t cr_irrx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_irrx_in_inv : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_irrx_mode : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t cr_irrx_deg_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 3; + uint32_t cr_irrx_deg_cnt : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 20; + }; + } irrx_config; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t irrx_end_int : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 7; + uint32_t cr_irrx_end_mask : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad1 : 7; + uint32_t cr_irrx_end_clr : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 7; + uint32_t cr_irrx_end_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad3 : 7; + }; + } irrx_int_sts; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t cr_irrx_data_th : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t cr_irrx_end_th : 16; // @ 31 -- 16 # 0xffff + }; + } irrx_pw_config; // @ 0x88 + uint8_t pad2[0x4]; + union { + uint32_t value; + struct { + uint32_t sts_irrx_data_cnt : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 25; + }; + } irrx_data_count; // @ 0x90 + union { + uint32_t value; + struct { + uint32_t sts_irrx_data_word0 : 32; // @ 31 -- 0 # 0x0 + }; + } irrx_data_word0; // @ 0x94 + union { + uint32_t value; + struct { + uint32_t sts_irrx_data_word1 : 32; // @ 31 -- 0 # 0x0 + }; + } irrx_data_word1; // @ 0x98 + uint8_t pad3[0x24]; + union { + uint32_t value; + struct { + uint32_t rx_fifo_clr : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 1; + uint32_t rx_fifo_overflow : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rx_fifo_underflow : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t rx_fifo_cnt : 7; // @ 10 -- 4 # 0xfffff80f + uint32_t pad1 : 21; + }; + } irrx_swm_fifo_config_0; // @ 0xc0 + union { + uint32_t value; + struct { + uint32_t rx_fifo_rdata : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } irrx_swm_fifo_rdata; // @ 0xc4 + }; +} ir_regs; +#define IR_BASE 0x4000a600 +#define IR ((ir_regs* volatile)(IR_BASE)) \ No newline at end of file diff --git a/src/include/soc/l1c.h b/src/include/soc/l1c.h new file mode 100644 index 0000000..ce77cad --- /dev/null +++ b/src/include/soc/l1c.h @@ -0,0 +1,84 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t l1c_cacheable : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t l1c_cnt_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t l1c_invalid_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t l1c_invalid_done : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 4; + uint32_t l1c_way_dis : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t irom_2t_access : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad1 : 1; + uint32_t l1c_bypass : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t l1c_bmx_err_en : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t l1c_bmx_arb_mode : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 2; + uint32_t l1c_bmx_timeout_en : 4; // @ 23 -- 20 # 0xff0fffff + uint32_t l1c_bmx_busy_option_dis : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t early_resp_dis : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t wrap_dis : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad3 : 5; + }; + } l1c_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t hit_cnt_lsb : 32; // @ 31 -- 0 # 0x0 + }; + } hit_cnt_lsb; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t hit_cnt_msb : 32; // @ 31 -- 0 # 0x0 + }; + } hit_cnt_msb; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t miss_cnt : 32; // @ 31 -- 0 # 0x0 + }; + } miss_cnt; // @ 0xc + uint32_t l1c_range; // @ 0x10 + uint8_t pad0[0x1ec]; + union { + uint32_t value; + struct { + uint32_t l1c_bmx_err_addr_dis : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t l1c_bmx_err_dec : 1; // @ 4 -- 4 # 0xffffffef + uint32_t l1c_bmx_err_tz : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 10; + uint32_t l1c_hsel_option : 4; // @ 19 -- 16 # 0xfff0ffff + uint32_t pad2 : 12; + }; + } l1c_bmx_err_addr_en; // @ 0x200 + union { + uint32_t value; + struct { + uint32_t l1c_bmx_err_addr : 32; // @ 31 -- 0 # 0x0 + }; + } l1c_bmx_err_addr; // @ 0x204 + union { + uint32_t value; + struct { + uint32_t irom1_misr_dataout_0 : 32; // @ 31 -- 0 # 0x0 + }; + } irom1_misr_dataout_0; // @ 0x208 + uint32_t irom1_misr_dataout_1; // @ 0x20c + union { + uint32_t value; + struct { + uint32_t force_e21_clock_on_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t force_e21_clock_on_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t force_e21_clock_on_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } cpu_clk_gate; // @ 0x210 + }; +} l1c_regs; +#define L1C_BASE 0x40009000 +#define L1C ((l1c_regs* volatile)(L1C_BASE)) \ No newline at end of file diff --git a/src/include/soc/pds.h b/src/include/soc/pds.h new file mode 100644 index 0000000..c0e6079 --- /dev/null +++ b/src/include/soc/pds.h @@ -0,0 +1,284 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t pds_start_ps : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_sleep_forever : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_xtal_force_off : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_wifi_pds_save_state : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_pds_pd_dcdc18 : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_pds_pd_bg_sys : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t cr_pds_gate_clk : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t cr_pds_mem_stby : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad1 : 1; + uint32_t cr_pds_iso_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t cr_pds_wait_xtal_rdy : 1; // @ 12 -- 12 # 0xffffefff + uint32_t cr_pds_pwr_off : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t cr_pds_pd_xtal : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t cr_pds_soc_enb_force_on : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t cr_pds_rst_soc_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t cr_pds_rc32m_off_dis : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t cr_pds_ldo_vsel_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad2 : 2; + uint32_t cr_np_wfi_mask : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t cr_pds_pd_ldo11 : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad3 : 1; + uint32_t cr_pds_ldo_vol : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t cr_pds_ctrl_rf : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t cr_pds_ctrl_pll : 2; // @ 31 -- 30 # 0x3fffffff + }; + } PDS_CTL; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t cr_sleep_duration : 32; // @ 31 -- 0 # 0x0 + }; + } PDS_TIME1; // @ 0x4 + uint8_t pad0[0x4]; + union { + uint32_t value; + struct { + uint32_t ro_pds_wake_int : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t ro_pds_irq_in : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t ro_pds_rf_done_int : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t ro_pds_pll_done_int : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 4; + uint32_t cr_pds_wake_int_mask : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t cr_pds_irq_in_dis : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t cr_pds_rf_done_int_mask : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t cr_pds_pll_done_int_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad1 : 4; + uint32_t cr_pds_int_clr : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 15; + }; + } PDS_INT; // @ 0xc + union { + uint32_t value; + struct { + uint32_t cr_pds_force_np_pwr_off : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 1; + uint32_t cr_pds_force_wb_pwr_off : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad1 : 1; + uint32_t cr_pds_force_np_iso_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad2 : 1; + uint32_t cr_pds_force_wb_iso_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad3 : 1; + uint32_t cr_pds_force_np_pds_rst : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad4 : 1; + uint32_t cr_pds_force_wb_pds_rst : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad5 : 1; + uint32_t cr_pds_force_np_mem_stby : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad6 : 1; + uint32_t cr_pds_force_wb_mem_stby : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pad7 : 1; + uint32_t cr_pds_force_np_gate_clk : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad8 : 1; + uint32_t cr_pds_force_wb_gate_clk : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad9 : 13; + }; + } PDS_CTL2; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t pad0 : 1; + uint32_t cr_pds_force_misc_pwr_off : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad1 : 2; + uint32_t cr_pds_force_misc_iso_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad2 : 2; + uint32_t cr_pds_force_misc_pds_rst : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad3 : 2; + uint32_t cr_pds_force_misc_mem_stby : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad4 : 2; + uint32_t cr_pds_force_misc_gate_clk : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad5 : 10; + uint32_t cr_pds_np_iso_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t pad6 : 2; + uint32_t cr_pds_wb_iso_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t pad7 : 2; + uint32_t cr_pds_misc_iso_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t pad8 : 1; + }; + } PDS_CTL3; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t cr_pds_np_pwr_off : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_pds_np_reset : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_pds_np_mem_stby : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_pds_np_gate_clk : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 8; + uint32_t cr_pds_wb_pwr_off : 1; // @ 12 -- 12 # 0xffffefff + uint32_t cr_pds_wb_reset : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t cr_pds_wb_mem_stby : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t cr_pds_wb_gate_clk : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t pad1 : 8; + uint32_t cr_pds_misc_pwr_off : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t cr_pds_misc_reset : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t cr_pds_misc_mem_stby : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t cr_pds_misc_gate_clk : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t pad2 : 4; + }; + } PDS_CTL4; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t ro_pds_state : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t pad0 : 4; + uint32_t ro_pds_rf_state : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t pad1 : 4; + uint32_t ro_pds_pll_state : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } pds_stat; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t cr_np_sram_pwr : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } pds_ram1; // @ 0x20 + uint8_t pad1[0x2dc]; + union { + uint32_t value; + struct { + uint32_t rc32m_cal_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rc32m_rdy : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rc32m_cal_inprogress : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rc32m_cal_div : 2; // @ 4 -- 3 # 0xffffffe7 + uint32_t rc32m_cal_precharge : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rc32m_dig_code_fr_cal : 8; // @ 13 -- 6 # 0xffffc03f + uint32_t pad0 : 3; + uint32_t rc32m_allow_cal : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t rc32m_refclk_half : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t rc32m_ext_code_en : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t rc32m_cal_en : 1; // @ 20 -- 20 # 0xffefffff + uint32_t rc32m_pd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t rc32m_code_fr_ext : 8; // @ 29 -- 22 # 0xc03fffff + uint32_t pad1 : 2; + }; + } rc32m_ctrl0; // @ 0x300 + union { + uint32_t value; + struct { + uint32_t rc32m_test_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t rc32m_soft_rst : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rc32m_clk_soft_rst : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rc32m_clk_inv : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t rc32m_clk_force_on : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 19; + uint32_t rc32m_reserved : 8; // @ 31 -- 24 # 0xffffff + }; + } rc32m_ctrl1; // @ 0x304 + uint8_t pad2[0xf8]; + union { + uint32_t value; + struct { + uint32_t clkpll_sdm_reset : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t clkpll_reset_postdiv : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t clkpll_reset_fbdv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t clkpll_reset_refdiv : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t clkpll_pu_postdiv : 1; // @ 4 -- 4 # 0xffffffef + uint32_t clkpll_pu_fbdv : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t clkpll_pu_clamp_op : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t clkpll_pu_pfd : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t clkpll_pu_cp : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pu_clkpll_sfreg : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pu_clkpll : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad0 : 21; + }; + } pu_rst_clkpll; // @ 0x400 + union { + uint32_t value; + struct { + uint32_t clkpll_postdiv : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + uint32_t clkpll_refdiv_ratio : 4; // @ 11 -- 8 # 0xfffff0ff + uint32_t clkpll_xtal_rc32m_sel : 1; // @ 12 -- 12 # 0xffffefff + uint32_t pad1 : 3; + uint32_t clkpll_refclk_sel : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad2 : 3; + uint32_t clkpll_vg11_sel : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t pad3 : 2; + uint32_t clkpll_vg13_sel : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad4 : 6; + }; + } clkpll_top_ctrl; // @ 0x404 + union { + uint32_t value; + struct { + uint32_t clkpll_sel_cp_bias : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t clkpll_icp_5u : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t clkpll_icp_1u : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t clkpll_int_frac_sw : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t clkpll_cp_startup_en : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t clkpll_cp_opamp_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad1 : 21; + }; + } clkpll_cp; // @ 0x408 + union { + uint32_t value; + struct { + uint32_t clkpll_c4_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 3; + uint32_t clkpll_r4 : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t pad1 : 2; + uint32_t clkpll_r4_short : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t pad2 : 3; + uint32_t clkpll_c3 : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t clkpll_cz : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t clkpll_rz : 3; // @ 18 -- 16 # 0xfff8ffff + uint32_t pad3 : 13; + }; + } clkpll_rz; // @ 0x40c + union { + uint32_t value; + struct { + uint32_t clkpll_sel_sample_clk : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t clkpll_sel_fb_clk : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t pad0 : 28; + }; + } clkpll_fbdv; // @ 0x410 + union { + uint32_t value; + struct { + uint32_t clkpll_vco_speed : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t clkpll_shrtr : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; + }; + } clkpll_vco; // @ 0x414 + union { + uint32_t value; + struct { + uint32_t clkpll_sdmin : 24; // @ 23 -- 0 # 0xff000000 + uint32_t clkpll_dither_sel : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad0 : 2; + uint32_t clkpll_sdm_flag : 1; // @ 28 -- 28 # 0xefffffff + uint32_t clkpll_sdm_bypass : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad1 : 2; + }; + } clkpll_sdm; // @ 0x418 + union { + uint32_t value; + struct { + uint32_t clkpll_en_480m : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t clkpll_en_240m : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t clkpll_en_192m : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t clkpll_en_160m : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t clkpll_en_120m : 1; // @ 4 -- 4 # 0xffffffef + uint32_t clkpll_en_96m : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t clkpll_en_80m : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t clkpll_en_48m : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t clkpll_en_32m : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t clkpll_en_div2_480m : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 22; + }; + } clkpll_output_en; // @ 0x41c + }; +} pds_regs; +#define PDS_BASE 0x4000e000 +#define PDS ((pds_regs* volatile)(PDS_BASE)) \ No newline at end of file diff --git a/src/include/soc/pwm.h b/src/include/soc/pwm.h new file mode 100644 index 0000000..14c358d --- /dev/null +++ b/src/include/soc/pwm.h @@ -0,0 +1,267 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t pwm_interrupt_sts : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t pwm_int_clear : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 18; + }; + } pwm_int_config; // @ 0x0 + uint8_t pad0[0x1c]; + union { + uint32_t value; + struct { + uint32_t pwm_clk_div : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm0_clkdiv; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t pwm_thre1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm0_thre1; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t pwm_thre2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm0_thre2; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t pwm_period : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm0_period; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t reg_clk_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pwm_out_inv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pwm_stop_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pwm_sw_force_val : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pwm_sw_mode : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pwm_stop_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pwm_sts_top : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } pwm0_config; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t pwm_int_period_cnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pwm_int_enable : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 15; + }; + } pwm0_interrupt; // @ 0x34 + uint8_t pad1[0x8]; + union { + uint32_t value; + struct { + uint32_t pwm_clk_div : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm1_clkdiv; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t pwm_thre1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm1_thre1; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t pwm_thre2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm1_thre2; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t pwm_period : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm1_period; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t reg_clk_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pwm_out_inv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pwm_stop_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pwm_sw_force_val : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pwm_sw_mode : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pwm_stop_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pwm_sts_top : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } pwm1_config; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t pwm_int_period_cnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pwm_int_enable : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 15; + }; + } pwm1_interrupt; // @ 0x54 + uint8_t pad2[0x8]; + union { + uint32_t value; + struct { + uint32_t pwm_clk_div : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm2_clkdiv; // @ 0x60 + union { + uint32_t value; + struct { + uint32_t pwm_thre1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm2_thre1; // @ 0x64 + union { + uint32_t value; + struct { + uint32_t pwm_thre2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm2_thre2; // @ 0x68 + union { + uint32_t value; + struct { + uint32_t pwm_period : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm2_period; // @ 0x6c + union { + uint32_t value; + struct { + uint32_t reg_clk_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pwm_out_inv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pwm_stop_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pwm_sw_force_val : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pwm_sw_mode : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pwm_stop_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pwm_sts_top : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } pwm2_config; // @ 0x70 + union { + uint32_t value; + struct { + uint32_t pwm_int_period_cnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pwm_int_enable : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 15; + }; + } pwm2_interrupt; // @ 0x74 + uint8_t pad3[0x8]; + union { + uint32_t value; + struct { + uint32_t pwm_clk_div : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm3_clkdiv; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t pwm_thre1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm3_thre1; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t pwm_thre2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm3_thre2; // @ 0x88 + union { + uint32_t value; + struct { + uint32_t pwm_period : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm3_period; // @ 0x8c + union { + uint32_t value; + struct { + uint32_t reg_clk_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pwm_out_inv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pwm_stop_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pwm_sw_force_val : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pwm_sw_mode : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pwm_stop_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pwm_sts_top : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } pwm3_config; // @ 0x90 + union { + uint32_t value; + struct { + uint32_t pwm_int_period_cnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pwm_int_enable : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 15; + }; + } pwm3_interrupt; // @ 0x94 + uint8_t pad4[0x8]; + union { + uint32_t value; + struct { + uint32_t pwm_clk_div : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm4_clkdiv; // @ 0xa0 + union { + uint32_t value; + struct { + uint32_t pwm_thre1 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm4_thre1; // @ 0xa4 + union { + uint32_t value; + struct { + uint32_t pwm_thre2 : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm4_thre2; // @ 0xa8 + union { + uint32_t value; + struct { + uint32_t pwm_period : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } pwm4_period; // @ 0xac + union { + uint32_t value; + struct { + uint32_t reg_clk_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pwm_out_inv : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pwm_stop_mode : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pwm_sw_force_val : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pwm_sw_mode : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pwm_stop_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pwm_sts_top : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } pwm4_config; // @ 0xb0 + union { + uint32_t value; + struct { + uint32_t pwm_int_period_cnt : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pwm_int_enable : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t pad0 : 15; + }; + } pwm4_interrupt; // @ 0xb4 + }; +} pwm_regs; +#define PWM_BASE 0x4000a400 +#define PWM ((pwm_regs* volatile)(PWM_BASE)) \ No newline at end of file diff --git a/src/include/soc/sec_dbg.h b/src/include/soc/sec_dbg.h new file mode 100644 index 0000000..8687274 --- /dev/null +++ b/src/include/soc/sec_dbg.h @@ -0,0 +1,62 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t sd_chip_id_low : 32; // @ 31 -- 0 # 0x0 + }; + } sd_chip_id_low; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t sd_chip_id_high : 32; // @ 31 -- 0 # 0x0 + }; + } sd_chip_id_high; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t sd_wifi_mac_low : 32; // @ 31 -- 0 # 0x0 + }; + } sd_wifi_mac_low; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t sd_wifi_mac_high : 32; // @ 31 -- 0 # 0x0 + }; + } sd_wifi_mac_high; // @ 0xc + union { + uint32_t value; + struct { + uint32_t sd_dbg_pwd_low : 32; // @ 31 -- 0 # 0x0 + }; + } sd_dbg_pwd_low; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t sd_dbg_pwd_high : 32; // @ 31 -- 0 # 0x0 + }; + } sd_dbg_pwd_high; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t sd_dbg_pwd_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sd_dbg_pwd_trig : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t sd_dbg_cci_read_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t sd_dbg_cci_clk_sel : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t sd_dbg_pwd_cnt : 20; // @ 23 -- 4 # 0xff00000f + uint32_t sd_dbg_mode : 4; // @ 27 -- 24 # 0xf0ffffff + uint32_t sd_dbg_ena : 4; // @ 31 -- 28 # 0xfffffff + }; + } sd_status; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t sd_dbg_reserved : 32; // @ 31 -- 0 # 0x0 + }; + } sd_dbg_reserved; // @ 0x1c + }; +} sec_dbg_regs; +#define SEC_DBG_BASE 0x40003000 +#define SEC_DBG ((sec_dbg_regs* volatile)(SEC_DBG_BASE)) \ No newline at end of file diff --git a/src/include/soc/sec_eng.h b/src/include/soc/sec_eng.h new file mode 100644 index 0000000..be41930 --- /dev/null +++ b/src/include/soc/sec_eng.h @@ -0,0 +1,624 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t se_sha_0_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_sha_0_trig_1t : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_sha_0_mode : 3; // @ 4 -- 2 # 0xffffffe3 + uint32_t se_sha_0_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t se_sha_0_hash_sel : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad0 : 1; + uint32_t se_sha_0_int : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t se_sha_0_int_clr_1t : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t se_sha_0_int_set_1t : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t se_sha_0_int_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad1 : 3; + uint32_t se_sha_0_link_mode : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t se_sha_0_msg_len : 16; // @ 31 -- 16 # 0xffff + }; + } se_sha_0_ctrl; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t se_sha_0_msa : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_msa; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t se_sha_0_status : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_status; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t se_sha_0_dout_endian : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } se_sha_0_endian; // @ 0xc + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_0; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_1; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_2; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_3 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_3; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_4 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_4; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_5 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_5; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_6 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_6; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_l_7 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_l_7; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_0; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_1; // @ 0x34 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_2; // @ 0x38 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_3 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_3; // @ 0x3c + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_4 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_4; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_5 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_5; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_6 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_6; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t se_sha_0_hash_h_7 : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_hash_h_7; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t se_sha_0_lca : 32; // @ 31 -- 0 # 0x0 + }; + } se_sha_0_link; // @ 0x50 + uint8_t pad0[0xa8]; + union { + uint32_t value; + struct { + uint32_t se_sha_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_sha_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_sha_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } se_sha_0_ctrl_prot; // @ 0xfc + union { + uint32_t value; + struct { + uint32_t se_aes_0_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_aes_0_trig_1t : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_aes_0_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t se_aes_0_mode : 2; // @ 4 -- 3 # 0xffffffe7 + uint32_t se_aes_0_dec_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t se_aes_0_dec_key_sel : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t se_aes_0_hw_key_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t se_aes_0_int : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t se_aes_0_int_clr_1t : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t se_aes_0_int_set_1t : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t se_aes_0_int_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t se_aes_0_block_mode : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t se_aes_0_iv_sel : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t se_aes_0_link_mode : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t se_aes_0_msg_len : 16; // @ 31 -- 16 # 0xffff + }; + } se_aes_0_ctrl; // @ 0x100 + union { + uint32_t value; + struct { + uint32_t se_aes_0_msa : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_msa; // @ 0x104 + union { + uint32_t value; + struct { + uint32_t se_aes_0_mda : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_mda; // @ 0x108 + union { + uint32_t value; + struct { + uint32_t se_aes_0_status : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_status; // @ 0x10c + union { + uint32_t value; + struct { + uint32_t se_aes_0_iv_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_iv_0; // @ 0x110 + union { + uint32_t value; + struct { + uint32_t se_aes_0_iv_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_iv_1; // @ 0x114 + union { + uint32_t value; + struct { + uint32_t se_aes_0_iv_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_iv_2; // @ 0x118 + union { + uint32_t value; + struct { + uint32_t se_aes_0_iv_3 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_iv_3; // @ 0x11c + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_0; // @ 0x120 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_1; // @ 0x124 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_2; // @ 0x128 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_3 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_3; // @ 0x12c + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_4 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_4; // @ 0x130 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_5 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_5; // @ 0x134 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_6 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_6; // @ 0x138 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_7 : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_key_7; // @ 0x13c + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_sel_0 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 30; + }; + } se_aes_0_key_sel_0; // @ 0x140 + union { + uint32_t value; + struct { + uint32_t se_aes_0_key_sel_1 : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 30; + }; + } se_aes_0_key_sel_1; // @ 0x144 + union { + uint32_t value; + struct { + uint32_t se_aes_0_dout_endian : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_aes_0_din_endian : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_aes_0_key_endian : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t se_aes_0_iv_endian : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 26; + uint32_t se_aes_0_ctr_len : 2; // @ 31 -- 30 # 0x3fffffff + }; + } se_aes_0_endian; // @ 0x148 + union { + uint32_t value; + struct { + uint32_t se_aes_0_sboot_key_sel : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } se_aes_0_sboot; // @ 0x14c + union { + uint32_t value; + struct { + uint32_t se_aes_0_lca : 32; // @ 31 -- 0 # 0x0 + }; + } se_aes_0_link; // @ 0x150 + uint8_t pad1[0xa8]; + union { + uint32_t value; + struct { + uint32_t se_aes_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_aes_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_aes_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } se_aes_0_ctrl_prot; // @ 0x1fc + union { + uint32_t value; + struct { + uint32_t se_trng_0_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_trng_0_trig_1t : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_trng_0_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t se_trng_0_dout_clr_1t : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t se_trng_0_ht_error : 1; // @ 4 -- 4 # 0xffffffef + uint32_t pad0 : 3; + uint32_t se_trng_0_int : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t se_trng_0_int_clr_1t : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t se_trng_0_int_set_1t : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t se_trng_0_int_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad1 : 1; + uint32_t se_trng_0_manual_fun_sel : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t se_trng_0_manual_reseed : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t se_trng_0_manual_en : 1; // @ 15 -- 15 # 0xffff7fff + uint32_t pad2 : 16; + }; + } se_trng_0_ctrl_0; // @ 0x200 + union { + uint32_t value; + struct { + uint32_t se_trng_0_status : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_status; // @ 0x204 + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_0; // @ 0x208 + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_1; // @ 0x20c + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_2; // @ 0x210 + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_3 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_3; // @ 0x214 + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_4 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_4; // @ 0x218 + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_5 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_5; // @ 0x21c + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_6 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_6; // @ 0x220 + union { + uint32_t value; + struct { + uint32_t se_trng_0_dout_7 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_dout_7; // @ 0x224 + union { + uint32_t value; + struct { + uint32_t se_trng_0_test_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_trng_0_cp_test_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_trng_0_cp_bypass : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t se_trng_0_ht_dis : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t se_trng_0_ht_alarm_n : 8; // @ 11 -- 4 # 0xfffff00f + uint32_t pad0 : 20; + }; + } se_trng_0_test; // @ 0x228 + union { + uint32_t value; + struct { + uint32_t se_trng_0_reseed_n_lsb : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_ctrl_1; // @ 0x22c + union { + uint32_t value; + struct { + uint32_t se_trng_0_reseed_n_msb : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } se_trng_0_ctrl_2; // @ 0x230 + union { + uint32_t value; + struct { + uint32_t se_trng_0_cp_ratio : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t se_trng_0_ht_rct_c : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t se_trng_0_ht_apt_c : 10; // @ 25 -- 16 # 0xfc00ffff + uint32_t se_trng_0_ht_od_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t pad0 : 4; + uint32_t se_trng_0_rosc_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } se_trng_0_ctrl_3; // @ 0x234 + uint8_t pad2[0x8]; + union { + uint32_t value; + struct { + uint32_t se_trng_0_test_out_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_test_out_0; // @ 0x240 + union { + uint32_t value; + struct { + uint32_t se_trng_0_test_out_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_test_out_1; // @ 0x244 + union { + uint32_t value; + struct { + uint32_t se_trng_0_test_out_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_test_out_2; // @ 0x248 + union { + uint32_t value; + struct { + uint32_t se_trng_0_test_out_3 : 32; // @ 31 -- 0 # 0x0 + }; + } se_trng_0_test_out_3; // @ 0x24c + uint8_t pad3[0xac]; + union { + uint32_t value; + struct { + uint32_t se_trng_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_trng_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_trng_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } se_trng_0_ctrl_prot; // @ 0x2fc + union { + uint32_t value; + struct { + uint32_t se_pka_0_done : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_pka_0_done_clr_1t : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_pka_0_busy : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t se_pka_0_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t se_pka_0_prot_md : 4; // @ 7 -- 4 # 0xffffff0f + uint32_t se_pka_0_int : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t se_pka_0_int_clr_1t : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t se_pka_0_int_set : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t se_pka_0_int_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t se_pka_0_endian : 1; // @ 12 -- 12 # 0xffffefff + uint32_t se_pka_0_ram_clr_md : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad0 : 2; + uint32_t se_pka_0_status_clr_1t : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t se_pka_0_status : 15; // @ 31 -- 17 # 0x1ffff + }; + } se_pka_0_ctrl_0; // @ 0x300 + uint8_t pad4[0x8]; + union { + uint32_t value; + struct { + uint32_t se_pka_0_seed : 32; // @ 31 -- 0 # 0x0 + }; + } se_pka_0_seed; // @ 0x30c + union { + uint32_t value; + struct { + uint32_t se_pka_0_hburst : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t se_pka_0_hbypass : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 28; + }; + } se_pka_0_ctrl_1; // @ 0x310 + uint8_t pad5[0x2c]; + uint32_t se_pka_0_rw; // @ 0x340 + uint8_t pad6[0x1c]; + uint32_t se_pka_0_rw_burst; // @ 0x360 + uint8_t pad7[0x98]; + union { + uint32_t value; + struct { + uint32_t se_pka_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_pka_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_pka_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } se_pka_0_ctrl_prot; // @ 0x3fc + union { + uint32_t value; + struct { + uint32_t se_cdet_0_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_cdet_0_error : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_cdet_0_status : 14; // @ 15 -- 2 # 0xffff0003 + uint32_t se_cdet_0_g_loop_max : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t se_cdet_0_g_loop_min : 8; // @ 31 -- 24 # 0xffffff + }; + } se_cdet_0_ctrl_0; // @ 0x400 + union { + uint32_t value; + struct { + uint32_t se_cdet_0_t_loop_n : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t se_cdet_0_t_dly_n : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t se_cdet_0_g_slp_n : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t pad0 : 8; + }; + } se_cdet_0_ctrl_1; // @ 0x404 + uint8_t pad8[0xf4]; + union { + uint32_t value; + struct { + uint32_t se_cdet_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_cdet_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_cdet_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } se_cdet_0_ctrl_prot; // @ 0x4fc + union { + uint32_t value; + struct { + uint32_t se_gmac_0_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_gmac_0_trig_1t : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_gmac_0_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 5; + uint32_t se_gmac_0_int : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t se_gmac_0_int_clr_1t : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t se_gmac_0_int_set_1t : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t se_gmac_0_int_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t se_gmac_0_t_endian : 1; // @ 12 -- 12 # 0xffffefff + uint32_t se_gmac_0_h_endian : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t se_gmac_0_x_endian : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pad1 : 17; + }; + } se_gmac_0_ctrl_0; // @ 0x500 + union { + uint32_t value; + struct { + uint32_t se_gmac_0_lca : 32; // @ 31 -- 0 # 0x0 + }; + } se_gmac_0_lca; // @ 0x504 + union { + uint32_t value; + struct { + uint32_t se_gmac_0_status : 32; // @ 31 -- 0 # 0x0 + }; + } se_gmac_0_status; // @ 0x508 + uint8_t pad9[0xf0]; + union { + uint32_t value; + struct { + uint32_t se_gmac_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_gmac_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_gmac_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } se_gmac_0_ctrl_prot; // @ 0x5fc + uint8_t pad10[0x900]; + union { + uint32_t value; + struct { + uint32_t se_sha_prot_en_rd : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t se_sha_id0_en_rd : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t se_sha_id1_en_rd : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 1; + uint32_t se_aes_prot_en_rd : 1; // @ 4 -- 4 # 0xffffffef + uint32_t se_aes_id0_en_rd : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t se_aes_id1_en_rd : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t pad1 : 1; + uint32_t se_trng_prot_en_rd : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t se_trng_id0_en_rd : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t se_trng_id1_en_rd : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad2 : 1; + uint32_t se_pka_prot_en_rd : 1; // @ 12 -- 12 # 0xffffefff + uint32_t se_pka_id0_en_rd : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t se_pka_id1_en_rd : 1; // @ 14 -- 14 # 0xffffbfff + uint32_t pad3 : 1; + uint32_t se_cdet_prot_en_rd : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t se_cdet_id0_en_rd : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t se_cdet_id1_en_rd : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad4 : 1; + uint32_t se_gmac_prot_en_rd : 1; // @ 20 -- 20 # 0xffefffff + uint32_t se_gmac_id0_en_rd : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t se_gmac_id1_en_rd : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t pad5 : 8; + uint32_t se_dbg_dis : 1; // @ 31 -- 31 # 0x7fffffff + }; + } se_ctrl_prot_rd; // @ 0xf00 + union { + uint32_t value; + struct { + uint32_t se_ctrl_reserved_0 : 32; // @ 31 -- 0 # 0x0 + }; + } se_ctrl_reserved_0; // @ 0xf04 + union { + uint32_t value; + struct { + uint32_t se_ctrl_reserved_1 : 32; // @ 31 -- 0 # 0x0 + }; + } se_ctrl_reserved_1; // @ 0xf08 + union { + uint32_t value; + struct { + uint32_t se_ctrl_reserved_2 : 32; // @ 31 -- 0 # 0x0 + }; + } se_ctrl_reserved_2; // @ 0xf0c + }; +} sec_eng_regs; +#define SEC_ENG_BASE 0x40004000 +#define SEC_ENG ((sec_eng_regs* volatile)(SEC_ENG_BASE)) \ No newline at end of file diff --git a/src/include/soc/sf_ctrl.h b/src/include/soc/sf_ctrl.h new file mode 100644 index 0000000..5eaec5c --- /dev/null +++ b/src/include/soc/sf_ctrl.h @@ -0,0 +1,667 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t sf_clk_sf_rx_inv_sel : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t sf_clk_out_gate_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t sf_clk_out_inv_sel : 1; // @ 4 -- 4 # 0xffffffef + uint32_t sf_clk_sahb_sram_sel : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 2; + uint32_t sf_if_read_dly_n : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t sf_if_read_dly_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad2 : 4; + uint32_t sf_if_int : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t sf_if_int_clr : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t sf_if_int_set : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t sf_aes_dly_mode : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t sf_aes_dout_endian : 1; // @ 20 -- 20 # 0xffefffff + uint32_t sf_aes_ctr_plus_en : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t sf_aes_key_endian : 1; // @ 22 -- 22 # 0xffbfffff + uint32_t sf_aes_iv_endian : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t sf_id : 8; // @ 31 -- 24 # 0xffffff + }; + } sf_ctrl_0; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t sf_if_sr_pat_mask : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t sf_if_sr_pat : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t sf_if_sr_int : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t sf_if_sr_int_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t sf_if_sr_int_set : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t pad0 : 1; + uint32_t sf_if_0_ack_lat : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad1 : 1; + uint32_t sf_if_reg_hold : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t sf_if_reg_wp : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t sf_ahb2sif_stopped : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t sf_ahb2sif_stop : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t sf_if_fn_sel : 1; // @ 28 -- 28 # 0xefffffff + uint32_t sf_if_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t sf_ahb2sif_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t sf_ahb2sram_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_ctrl_1; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t sf_if_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sf_if_0_trig : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t sf_if_0_dat_byte : 10; // @ 11 -- 2 # 0xfffff003 + uint32_t sf_if_0_dmy_byte : 5; // @ 16 -- 12 # 0xfffe0fff + uint32_t sf_if_0_adr_byte : 3; // @ 19 -- 17 # 0xfff1ffff + uint32_t sf_if_0_cmd_byte : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t sf_if_0_dat_rw : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t sf_if_0_dat_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t sf_if_0_dmy_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t sf_if_0_adr_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t sf_if_0_cmd_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t sf_if_0_spi_mode : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t sf_if_0_qpi_mode_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_if_sahb_0; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t sf_if_0_cmd_buf_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_sahb_1; // @ 0xc + union { + uint32_t value; + struct { + uint32_t sf_if_0_cmd_buf_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_sahb_2; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t pad0 : 12; + uint32_t sf_if_1_dmy_byte : 5; // @ 16 -- 12 # 0xfffe0fff + uint32_t sf_if_1_adr_byte : 3; // @ 19 -- 17 # 0xfff1ffff + uint32_t sf_if_1_cmd_byte : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t sf_if_1_dat_rw : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t sf_if_1_dat_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t sf_if_1_dmy_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t sf_if_1_adr_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t sf_if_1_cmd_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t sf_if_1_spi_mode : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t sf_if_1_qpi_mode_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_if_iahb_0; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t sf_if_1_cmd_buf_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_iahb_1; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t sf_if_1_cmd_buf_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_iahb_2; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t sf_if_status_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_status_0; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t sf_if_status_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_status_1; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t sf_aes_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sf_aes_mode : 2; // @ 2 -- 1 # 0xfffffff9 + uint32_t sf_aes_pref_trig : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t sf_aes_pref_busy : 1; // @ 4 -- 4 # 0xffffffef + uint32_t sf_aes_status : 27; // @ 31 -- 5 # 0x1f + }; + } sf_aes; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t sf_ahb2sif_status : 32; // @ 31 -- 0 # 0x0 + }; + } sf_ahb2sif_status; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t sf_cs_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf_clk_out_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 16; + uint32_t sf_dqs_oe_dly_sel : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t sf_dqs_di_dly_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t sf_dqs_do_dly_sel : 2; // @ 31 -- 30 # 0x3fffffff + }; + } sf_if_io_dly_0; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t sf_io_0_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf_io_0_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf_io_0_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf_if_io_dly_1; // @ 0x34 + union { + uint32_t value; + struct { + uint32_t sf_io_1_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf_io_1_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf_io_1_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf_if_io_dly_2; // @ 0x38 + union { + uint32_t value; + struct { + uint32_t sf_io_2_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf_io_2_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf_io_2_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf_if_io_dly_3; // @ 0x3c + union { + uint32_t value; + struct { + uint32_t sf_io_3_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf_io_3_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf_io_3_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf_if_io_dly_4; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t sf_reserved : 32; // @ 31 -- 0 # 0x0 + }; + } sf_reserved; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t sf2_cs_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf2_clk_out_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 16; + uint32_t sf2_dqs_oe_dly_sel : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t sf2_dqs_di_dly_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t sf2_dqs_do_dly_sel : 2; // @ 31 -- 30 # 0x3fffffff + }; + } sf2_if_io_dly_0; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t sf2_io_0_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf2_io_0_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf2_io_0_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf2_if_io_dly_1; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t sf2_io_1_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf2_io_1_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf2_io_1_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf2_if_io_dly_2; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t sf2_io_2_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf2_io_2_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf2_io_2_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf2_if_io_dly_3; // @ 0x54 + union { + uint32_t value; + struct { + uint32_t sf2_io_3_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf2_io_3_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf2_io_3_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf2_if_io_dly_4; // @ 0x58 + union { + uint32_t value; + struct { + uint32_t sf3_cs_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf3_clk_out_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 16; + uint32_t sf3_dqs_oe_dly_sel : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t sf3_dqs_di_dly_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t sf3_dqs_do_dly_sel : 2; // @ 31 -- 30 # 0x3fffffff + }; + } sf3_if_io_dly_0; // @ 0x5c + union { + uint32_t value; + struct { + uint32_t sf3_io_0_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf3_io_0_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf3_io_0_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf3_if_io_dly_1; // @ 0x60 + union { + uint32_t value; + struct { + uint32_t sf3_io_1_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf3_io_1_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf3_io_1_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf3_if_io_dly_2; // @ 0x64 + union { + uint32_t value; + struct { + uint32_t sf3_io_2_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf3_io_2_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf3_io_2_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf3_if_io_dly_3; // @ 0x68 + union { + uint32_t value; + struct { + uint32_t sf3_io_3_oe_dly_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 6; + uint32_t sf3_io_3_di_dly_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 6; + uint32_t sf3_io_3_do_dly_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 14; + }; + } sf3_if_io_dly_4; // @ 0x6c + union { + uint32_t value; + struct { + uint32_t sf_if_pad_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 1; + uint32_t sf_if_pad_sel_lock : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t sf_if_dtr_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t sf_if_dqs_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad1 : 26; + }; + } sf_ctrl_2; // @ 0x70 + union { + uint32_t value; + struct { + uint32_t sf_cmds_wrap_len : 4; // @ 3 -- 0 # 0xfffffff0 + uint32_t sf_cmds_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t sf_cmds_bt_dly : 3; // @ 7 -- 5 # 0xffffff1f + uint32_t sf_cmds_bt_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t sf_cmds_wrap_q_ini : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t sf_cmds_wrap_mode : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t pad0 : 18; + uint32_t sf_if_1_ack_lat : 3; // @ 31 -- 29 # 0x1fffffff + }; + } sf_ctrl_3; // @ 0x74 + union { + uint32_t value; + struct { + uint32_t pad0 : 12; + uint32_t sf_if_2_dmy_byte : 5; // @ 16 -- 12 # 0xfffe0fff + uint32_t sf_if_2_adr_byte : 3; // @ 19 -- 17 # 0xfff1ffff + uint32_t sf_if_2_cmd_byte : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t sf_if_2_dat_rw : 1; // @ 23 -- 23 # 0xff7fffff + uint32_t sf_if_2_dat_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t sf_if_2_dmy_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t sf_if_2_adr_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t sf_if_2_cmd_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t sf_if_2_spi_mode : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t sf_if_2_qpi_mode_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_if_iahb_3; // @ 0x78 + union { + uint32_t value; + struct { + uint32_t sf_if_2_cmd_buf_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_iahb_4; // @ 0x7c + union { + uint32_t value; + struct { + uint32_t sf_if_2_cmd_buf_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_iahb_5; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t pad0 : 20; + uint32_t sf_if_3_cmd_byte : 3; // @ 22 -- 20 # 0xff8fffff + uint32_t pad1 : 5; + uint32_t sf_if_3_spi_mode : 3; // @ 30 -- 28 # 0x8fffffff + uint32_t sf_if_3_qpi_mode_en : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_if_iahb_6; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t sf_if_3_cmd_buf_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_if_iahb_7; // @ 0x88 + uint8_t pad0[0x74]; + union { + uint32_t value; + struct { + uint32_t sf_ctrl_prot_en_rd : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sf_ctrl_id0_en_rd : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t sf_ctrl_id1_en_rd : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 27; + uint32_t sf_if_0_trig_wr_lock : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t sf_dbg_dis : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_ctrl_prot_en_rd; // @ 0x100 + union { + uint32_t value; + struct { + uint32_t sf_ctrl_prot_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sf_ctrl_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t sf_ctrl_id1_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } sf_ctrl_prot_en; // @ 0x104 + uint8_t pad1[0xf8]; + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_0; // @ 0x200 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_1; // @ 0x204 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_2 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_2; // @ 0x208 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_3 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_3; // @ 0x20c + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_4 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_4; // @ 0x210 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_5 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_5; // @ 0x214 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_6 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_6; // @ 0x218 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r0_7 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r0_7; // @ 0x21c + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r0_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r0_w0; // @ 0x220 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r0_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r0_w1; // @ 0x224 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r0_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r0_w2; // @ 0x228 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r0_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r0_w3; // @ 0x22c + union { + uint32_t value; + struct { + uint32_t sf_aes_region_r0_end : 14; // @ 13 -- 0 # 0xffffc000 + uint32_t sf_aes_region_r0_start : 14; // @ 27 -- 14 # 0xf0003fff + uint32_t pad0 : 1; + uint32_t sf_aes_region_r0_hw_key_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t sf_aes_region_r0_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t sf_aes_region_r0_lock : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_aes_cfg_r0; // @ 0x230 + uint8_t pad2[0xcc]; + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_0; // @ 0x300 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_1; // @ 0x304 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_2 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_2; // @ 0x308 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_3 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_3; // @ 0x30c + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_4 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_4; // @ 0x310 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_5 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_5; // @ 0x314 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_6 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_6; // @ 0x318 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r1_7 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r1_7; // @ 0x31c + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r1_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r1_w0; // @ 0x320 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r1_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r1_w1; // @ 0x324 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r1_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r1_w2; // @ 0x328 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r1_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r1_w3; // @ 0x32c + union { + uint32_t value; + struct { + uint32_t sf_aes_r1_end : 14; // @ 13 -- 0 # 0xffffc000 + uint32_t sf_aes_r1_start : 14; // @ 27 -- 14 # 0xf0003fff + uint32_t pad0 : 1; + uint32_t sf_aes_r1_hw_key_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t sf_aes_r1_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t sf_aes_r1_lock : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_aes_r1; // @ 0x330 + uint8_t pad3[0xcc]; + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_0; // @ 0x400 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_1; // @ 0x404 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_2 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_2; // @ 0x408 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_3 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_3; // @ 0x40c + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_4 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_4; // @ 0x410 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_5 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_5; // @ 0x414 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_6 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_6; // @ 0x418 + union { + uint32_t value; + struct { + uint32_t sf_aes_key_r2_7 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_key_r2_7; // @ 0x41c + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r2_w0 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r2_w0; // @ 0x420 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r2_w1 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r2_w1; // @ 0x424 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r2_w2 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r2_w2; // @ 0x428 + union { + uint32_t value; + struct { + uint32_t sf_aes_iv_r2_w3 : 32; // @ 31 -- 0 # 0x0 + }; + } sf_aes_iv_r2_w3; // @ 0x42c + union { + uint32_t value; + struct { + uint32_t sf_aes_r2_end : 14; // @ 13 -- 0 # 0xffffc000 + uint32_t sf_aes_r2_start : 14; // @ 27 -- 14 # 0xf0003fff + uint32_t pad0 : 1; + uint32_t sf_aes_r2_hw_key_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t sf_aes_r2_en : 1; // @ 30 -- 30 # 0xbfffffff + uint32_t sf_aes_r2_lock : 1; // @ 31 -- 31 # 0x7fffffff + }; + } sf_aes_r2; // @ 0x430 + union { + uint32_t value; + struct { + uint32_t sf_id0_offset : 24; // @ 23 -- 0 # 0xff000000 + uint32_t pad0 : 8; + }; + } sf_id0_offset; // @ 0x434 + union { + uint32_t value; + struct { + uint32_t sf_id1_offset : 24; // @ 23 -- 0 # 0xff000000 + uint32_t pad0 : 8; + }; + } sf_id1_offset; // @ 0x438 + }; +} sf_ctrl_regs; +#define SF_CTRL_BASE 0x4000b000 +#define SF_CTRL ((sf_ctrl_regs* volatile)(SF_CTRL_BASE)) \ No newline at end of file diff --git a/src/include/soc/spi.h b/src/include/soc/spi.h new file mode 100644 index 0000000..77d6650 --- /dev/null +++ b/src/include/soc/spi.h @@ -0,0 +1,139 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t cr_spi_m_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_spi_s_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_spi_frame_size : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t cr_spi_sclk_pol : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_spi_sclk_ph : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t cr_spi_bit_inv : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t cr_spi_byte_inv : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t cr_spi_rxd_ignr_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t cr_spi_m_cont_en : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t pad0 : 1; + uint32_t cr_spi_deg_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t cr_spi_deg_cnt : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t pad1 : 16; + }; + } spi_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t spi_end_int : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t spi_txf_int : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t spi_rxf_int : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t spi_sto_int : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t spi_txu_int : 1; // @ 4 -- 4 # 0xffffffef + uint32_t spi_fer_int : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t pad0 : 2; + uint32_t cr_spi_end_mask : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t cr_spi_txf_mask : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t cr_spi_rxf_mask : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t cr_spi_sto_mask : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t cr_spi_txu_mask : 1; // @ 12 -- 12 # 0xffffefff + uint32_t cr_spi_fer_mask : 1; // @ 13 -- 13 # 0xffffdfff + uint32_t pad1 : 2; + uint32_t cr_spi_end_clr : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t rsvd_17 : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t rsvd_18 : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t cr_spi_sto_clr : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t cr_spi_txu_clr : 1; // @ 20 -- 20 # 0xffefffff + uint32_t rsvd_21 : 1; // @ 21 -- 21 # 0xffdfffff + uint32_t pad2 : 2; + uint32_t cr_spi_end_en : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t cr_spi_txf_en : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t cr_spi_rxf_en : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t cr_spi_sto_en : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t cr_spi_txu_en : 1; // @ 28 -- 28 # 0xefffffff + uint32_t cr_spi_fer_en : 1; // @ 29 -- 29 # 0xdfffffff + uint32_t pad3 : 2; + }; + } spi_int_sts; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t sts_spi_bus_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } spi_bus_busy; // @ 0x8 + uint8_t pad0[0x4]; + union { + uint32_t value; + struct { + uint32_t cr_spi_prd_s : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t cr_spi_prd_p : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t cr_spi_prd_d_ph_0 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t cr_spi_prd_d_ph_1 : 8; // @ 31 -- 24 # 0xffffff + }; + } spi_prd_0; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t cr_spi_prd_i : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } spi_prd_1; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t cr_spi_rxd_ignr_p : 5; // @ 4 -- 0 # 0xffffffe0 + uint32_t pad0 : 11; + uint32_t cr_spi_rxd_ignr_s : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad1 : 11; + }; + } spi_rxd_ignr; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t cr_spi_sto_value : 12; // @ 11 -- 0 # 0xfffff000 + uint32_t pad0 : 20; + }; + } spi_sto_value; // @ 0x1c + uint8_t pad1[0x60]; + union { + uint32_t value; + struct { + uint32_t spi_dma_tx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t spi_dma_rx_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tx_fifo_clr : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rx_fifo_clr : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t tx_fifo_overflow : 1; // @ 4 -- 4 # 0xffffffef + uint32_t tx_fifo_underflow : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rx_fifo_overflow : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t rx_fifo_underflow : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } spi_fifo_config_0; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t tx_fifo_cnt : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 5; + uint32_t rx_fifo_cnt : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad1 : 5; + uint32_t tx_fifo_th : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t pad2 : 6; + uint32_t rx_fifo_th : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t pad3 : 6; + }; + } spi_fifo_config_1; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t spi_fifo_wdata : 32; // @ 31 -- 0 # 0x0 + }; + } spi_fifo_wdata; // @ 0x88 + union { + uint32_t value; + struct { + uint32_t spi_fifo_rdata : 32; // @ 31 -- 0 # 0x0 + }; + } spi_fifo_rdata; // @ 0x8c + }; +} spi_regs; +#define SPI_BASE 0x4000a200 +#define SPI ((spi_regs* volatile)(SPI_BASE)) \ No newline at end of file diff --git a/src/include/soc/timer.h b/src/include/soc/timer.h new file mode 100644 index 0000000..bf6d225 --- /dev/null +++ b/src/include/soc/timer.h @@ -0,0 +1,284 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t pad0 : 2; + uint32_t cs_1 : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t RESERVED_4 : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cs_2 : 2; // @ 6 -- 5 # 0xffffff9f + uint32_t RESERVED_7 : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t cs_wdt : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t pad1 : 22; + }; + } TCCR; // @ 0x0 + uint8_t pad0[0xc]; + union { + uint32_t value; + struct { + uint32_t tmr : 32; // @ 31 -- 0 # 0x0 + }; + } TMR2_0; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t tmr : 32; // @ 31 -- 0 # 0x0 + }; + } TMR2_1; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t tmr : 32; // @ 31 -- 0 # 0x0 + }; + } TMR2_2; // @ 0x18 + union { + uint32_t value; + struct { + uint32_t tmr : 32; // @ 31 -- 0 # 0x0 + }; + } TMR3_0; // @ 0x1c + union { + uint32_t value; + struct { + uint32_t tmr : 32; // @ 31 -- 0 # 0x0 + }; + } TMR3_1; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t tmr : 32; // @ 31 -- 0 # 0x0 + }; + } TMR3_2; // @ 0x24 + uint8_t pad1[0x4]; + union { + uint32_t value; + struct { + uint32_t tcr : 32; // @ 31 -- 0 # 0x0 + }; + } TCR2; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t tcr3_counter : 32; // @ 31 -- 0 # 0x0 + }; + } TCR3; // @ 0x30 + uint8_t pad2[0x4]; + union { + uint32_t value; + struct { + uint32_t tmsr_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tmsr_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tmsr_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TMSR2; // @ 0x38 + union { + uint32_t value; + struct { + uint32_t tmsr_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tmsr_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tmsr_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TMSR3; // @ 0x3c + uint8_t pad3[0x4]; + union { + uint32_t value; + struct { + uint32_t tier_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tier_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tier_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TIER2; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t tier_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tier_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tier_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TIER3; // @ 0x48 + uint8_t pad4[0x4]; + union { + uint32_t value; + struct { + uint32_t tplvr : 32; // @ 31 -- 0 # 0x0 + }; + } TPLVR2; // @ 0x50 + union { + uint32_t value; + struct { + uint32_t tplvr : 32; // @ 31 -- 0 # 0x0 + }; + } TPLVR3; // @ 0x54 + uint8_t pad5[0x4]; + union { + uint32_t value; + struct { + uint32_t tplcr : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 30; + }; + } TPLCR2; // @ 0x5c + union { + uint32_t value; + struct { + uint32_t tplcr : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t pad0 : 30; + }; + } TPLCR3; // @ 0x60 + union { + uint32_t value; + struct { + uint32_t we : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t wrie : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; + }; + } WMER; // @ 0x64 + union { + uint32_t value; + struct { + uint32_t wmr : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } WMR; // @ 0x68 + union { + uint32_t value; + struct { + uint32_t wvr : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } WVR; // @ 0x6c + union { + uint32_t value; + struct { + uint32_t wts : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } WSR; // @ 0x70 + uint8_t pad6[0x4]; + union { + uint32_t value; + struct { + uint32_t tclr_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tclr_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tclr_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TICR2; // @ 0x78 + union { + uint32_t value; + struct { + uint32_t tclr_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tclr_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tclr_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TICR3; // @ 0x7c + union { + uint32_t value; + struct { + uint32_t wiclr : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } WICR; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t pad0 : 1; + uint32_t timer2_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t timer3_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad1 : 29; + }; + } TCER; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t pad0 : 1; + uint32_t timer2_mode : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t timer3_mode : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad1 : 29; + }; + } TCMR; // @ 0x88 + uint8_t pad7[0x4]; + union { + uint32_t value; + struct { + uint32_t tilr_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tilr_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tilr_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TILR2; // @ 0x90 + union { + uint32_t value; + struct { + uint32_t tilr_0 : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tilr_1 : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tilr_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 29; + }; + } TILR3; // @ 0x94 + union { + uint32_t value; + struct { + uint32_t wcr : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } WCR; // @ 0x98 + union { + uint32_t value; + struct { + uint32_t wfar : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } WFAR; // @ 0x9c + union { + uint32_t value; + struct { + uint32_t wsar : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } WSAR; // @ 0xa0 + uint8_t pad8[0x4]; + union { + uint32_t value; + struct { + uint32_t tcvwr : 32; // @ 31 -- 0 # 0x0 + }; + } TCVWR2; // @ 0xa8 + union { + uint32_t value; + struct { + uint32_t tcvwr : 32; // @ 31 -- 0 # 0x0 + }; + } TCVWR3; // @ 0xac + uint8_t pad9[0x4]; + union { + uint32_t value; + struct { + uint32_t tcvsyn2 : 32; // @ 31 -- 0 # 0x0 + }; + } TCVSYN2; // @ 0xb4 + union { + uint32_t value; + struct { + uint32_t tcvsyn3 : 32; // @ 31 -- 0 # 0x0 + }; + } TCVSYN3; // @ 0xb8 + union { + uint32_t value; + struct { + uint32_t pad0 : 8; + uint32_t tcdr2 : 8; // @ 15 -- 8 # 0xffff00ff + uint32_t tcdr3 : 8; // @ 23 -- 16 # 0xff00ffff + uint32_t wcdr : 8; // @ 31 -- 24 # 0xffffff + }; + } TCDR; // @ 0xbc + }; +} timer_regs; +#define TIMER_BASE 0x4000a500 +#define TIMER ((timer_regs* volatile)(TIMER_BASE)) \ No newline at end of file diff --git a/src/include/soc/tzc_nsec.h b/src/include/soc/tzc_nsec.h new file mode 100644 index 0000000..c82efc8 --- /dev/null +++ b/src/include/soc/tzc_nsec.h @@ -0,0 +1,62 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + uint8_t pad0[0x40]; + union { + uint32_t value; + struct { + uint32_t tzc_rom0_r0_id0_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tzc_rom0_r1_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tzc_rom1_r0_id0_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t tzc_rom1_r1_id0_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 4; + uint32_t tzc_rom0_r0_id1_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t tzc_rom0_r1_id1_en : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t tzc_rom1_r0_id1_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t tzc_rom1_r1_id1_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad1 : 4; + uint32_t tzc_rom0_r0_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t tzc_rom0_r1_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t tzc_rom1_r0_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t tzc_rom1_r1_en : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pad2 : 4; + uint32_t tzc_rom0_r0_lock : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t tzc_rom0_r1_lock : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t tzc_rom1_r0_lock : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t tzc_rom1_r1_lock : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t tzc_sboot_done : 4; // @ 31 -- 28 # 0xfffffff + }; + } tzc_rom_ctrl; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t tzc_rom0_r0_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom0_r0_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom0_r0; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t tzc_rom0_r1_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom0_r1_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom0_r1; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t tzc_rom1_r0_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom1_r0_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom1_r0; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t tzc_rom1_r1_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom1_r1_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom1_r1; // @ 0x50 + }; +} tzc_nsec_regs; +#define TZC_NSEC_BASE 0x40006000 +#define TZC_NSEC ((tzc_nsec_regs* volatile)(TZC_NSEC_BASE)) \ No newline at end of file diff --git a/src/include/soc/tzc_sec.h b/src/include/soc/tzc_sec.h new file mode 100644 index 0000000..90582e2 --- /dev/null +++ b/src/include/soc/tzc_sec.h @@ -0,0 +1,62 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + uint8_t pad0[0x40]; + union { + uint32_t value; + struct { + uint32_t tzc_rom0_r0_id0_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t tzc_rom0_r1_id0_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tzc_rom1_r0_id0_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t tzc_rom1_r1_id0_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t pad0 : 4; + uint32_t tzc_rom0_r0_id1_en : 1; // @ 8 -- 8 # 0xfffffeff + uint32_t tzc_rom0_r1_id1_en : 1; // @ 9 -- 9 # 0xfffffdff + uint32_t tzc_rom1_r0_id1_en : 1; // @ 10 -- 10 # 0xfffffbff + uint32_t tzc_rom1_r1_id1_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t pad1 : 4; + uint32_t tzc_rom0_r0_en : 1; // @ 16 -- 16 # 0xfffeffff + uint32_t tzc_rom0_r1_en : 1; // @ 17 -- 17 # 0xfffdffff + uint32_t tzc_rom1_r0_en : 1; // @ 18 -- 18 # 0xfffbffff + uint32_t tzc_rom1_r1_en : 1; // @ 19 -- 19 # 0xfff7ffff + uint32_t pad2 : 4; + uint32_t tzc_rom0_r0_lock : 1; // @ 24 -- 24 # 0xfeffffff + uint32_t tzc_rom0_r1_lock : 1; // @ 25 -- 25 # 0xfdffffff + uint32_t tzc_rom1_r0_lock : 1; // @ 26 -- 26 # 0xfbffffff + uint32_t tzc_rom1_r1_lock : 1; // @ 27 -- 27 # 0xf7ffffff + uint32_t tzc_sboot_done : 4; // @ 31 -- 28 # 0xfffffff + }; + } tzc_rom_ctrl; // @ 0x40 + union { + uint32_t value; + struct { + uint32_t tzc_rom0_r0_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom0_r0_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom0_r0; // @ 0x44 + union { + uint32_t value; + struct { + uint32_t tzc_rom0_r1_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom0_r1_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom0_r1; // @ 0x48 + union { + uint32_t value; + struct { + uint32_t tzc_rom1_r0_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom1_r0_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom1_r0; // @ 0x4c + union { + uint32_t value; + struct { + uint32_t tzc_rom1_r1_end : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t tzc_rom1_r1_start : 16; // @ 31 -- 16 # 0xffff + }; + } tzc_rom1_r1; // @ 0x50 + }; +} tzc_sec_regs; +#define TZC_SEC_BASE 0x40005000 +#define TZC_SEC ((tzc_sec_regs* volatile)(TZC_SEC_BASE)) \ No newline at end of file diff --git a/src/include/soc/uart.h b/src/include/soc/uart.h new file mode 100644 index 0000000..c8d2e76 --- /dev/null +++ b/src/include/soc/uart.h @@ -0,0 +1,192 @@ +typedef union { + uint32_t regs[0x400]; + uint8_t pad[0x1000]; + struct { + union { + uint32_t value; + struct { + uint32_t cr_utx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_utx_cts_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_utx_frm_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t pad0 : 1; + uint32_t cr_utx_prt_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_utx_prt_sel : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t cr_utx_ir_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t cr_utx_ir_inv : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t cr_utx_bit_cnt_d : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t pad1 : 1; + uint32_t cr_utx_bit_cnt_p : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t pad2 : 2; + uint32_t cr_utx_len : 16; // @ 31 -- 16 # 0xffff + }; + } utx_config; // @ 0x0 + union { + uint32_t value; + struct { + uint32_t cr_urx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_urx_rts_sw_mode : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_urx_rts_sw_val : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_urx_abr_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_urx_prt_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_urx_prt_sel : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t cr_urx_ir_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t cr_urx_ir_inv : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t cr_urx_bit_cnt_d : 3; // @ 10 -- 8 # 0xfffff8ff + uint32_t cr_urx_deg_en : 1; // @ 11 -- 11 # 0xfffff7ff + uint32_t cr_urx_deg_cnt : 4; // @ 15 -- 12 # 0xffff0fff + uint32_t cr_urx_len : 16; // @ 31 -- 16 # 0xffff + }; + } urx_config; // @ 0x4 + union { + uint32_t value; + struct { + uint32_t cr_utx_bit_prd : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t cr_urx_bit_prd : 16; // @ 31 -- 16 # 0xffff + }; + } uart_bit_prd; // @ 0x8 + union { + uint32_t value; + struct { + uint32_t cr_uart_bit_inv : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t pad0 : 31; + }; + } data_config; // @ 0xc + union { + uint32_t value; + struct { + uint32_t cr_utx_ir_pos_s : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t cr_utx_ir_pos_p : 16; // @ 31 -- 16 # 0xffff + }; + } utx_ir_position; // @ 0x10 + union { + uint32_t value; + struct { + uint32_t cr_urx_ir_pos_s : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t pad0 : 16; + }; + } urx_ir_position; // @ 0x14 + union { + uint32_t value; + struct { + uint32_t cr_urx_rto_value : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } urx_rto_timer; // @ 0x18 + uint8_t pad0[0x4]; + union { + uint32_t value; + struct { + uint32_t utx_end_int : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t urx_end_int : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t utx_fifo_int : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t urx_fifo_int : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t urx_rto_int : 1; // @ 4 -- 4 # 0xffffffef + uint32_t urx_pce_int : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t utx_fer_int : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t urx_fer_int : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } uart_int_sts; // @ 0x20 + union { + uint32_t value; + struct { + uint32_t cr_utx_end_mask : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_urx_end_mask : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_utx_fifo_mask : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_urx_fifo_mask : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_urx_rto_mask : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_urx_pce_mask : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t cr_utx_fer_mask : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t cr_urx_fer_mask : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } uart_int_mask; // @ 0x24 + union { + uint32_t value; + struct { + uint32_t cr_utx_end_clr : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_urx_end_clr : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t rsvd_2 : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rsvd_3 : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_urx_rto_clr : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_urx_pce_clr : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rsvd_6 : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t rsvd_7 : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } uart_int_clear; // @ 0x28 + union { + uint32_t value; + struct { + uint32_t cr_utx_end_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t cr_urx_end_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t cr_utx_fifo_en : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t cr_urx_fifo_en : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t cr_urx_rto_en : 1; // @ 4 -- 4 # 0xffffffef + uint32_t cr_urx_pce_en : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t cr_utx_fer_en : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t cr_urx_fer_en : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } uart_int_en; // @ 0x2c + union { + uint32_t value; + struct { + uint32_t sts_utx_bus_busy : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t sts_urx_bus_busy : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t pad0 : 30; + }; + } uart_status; // @ 0x30 + union { + uint32_t value; + struct { + uint32_t sts_urx_abr_prd_start : 16; // @ 15 -- 0 # 0xffff0000 + uint32_t sts_urx_abr_prd_0x55 : 16; // @ 31 -- 16 # 0xffff + }; + } sts_urx_abr_prd; // @ 0x34 + uint8_t pad1[0x48]; + union { + uint32_t value; + struct { + uint32_t uart_dma_tx_en : 1; // @ 0 -- 0 # 0xfffffffe + uint32_t uart_dma_rx_en : 1; // @ 1 -- 1 # 0xfffffffd + uint32_t tx_fifo_clr : 1; // @ 2 -- 2 # 0xfffffffb + uint32_t rx_fifo_clr : 1; // @ 3 -- 3 # 0xfffffff7 + uint32_t tx_fifo_overflow : 1; // @ 4 -- 4 # 0xffffffef + uint32_t tx_fifo_underflow : 1; // @ 5 -- 5 # 0xffffffdf + uint32_t rx_fifo_overflow : 1; // @ 6 -- 6 # 0xffffffbf + uint32_t rx_fifo_underflow : 1; // @ 7 -- 7 # 0xffffff7f + uint32_t pad0 : 24; + }; + } uart_fifo_config_0; // @ 0x80 + union { + uint32_t value; + struct { + uint32_t tx_fifo_cnt : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t rx_fifo_cnt : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + uint32_t tx_fifo_th : 5; // @ 20 -- 16 # 0xffe0ffff + uint32_t pad2 : 3; + uint32_t rx_fifo_th : 5; // @ 28 -- 24 # 0xe0ffffff + uint32_t pad3 : 3; + }; + } uart_fifo_config_1; // @ 0x84 + union { + uint32_t value; + struct { + uint32_t uart_fifo_wdata : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } uart_fifo_wdata; // @ 0x88 + union { + uint32_t value; + struct { + uint32_t uart_fifo_rdata : 8; // @ 7 -- 0 # 0xffffff00 + uint32_t pad0 : 24; + }; + } uart_fifo_rdata; // @ 0x8c + }; +} uart_regs; +#define UART_BASE 0x4000a000 +#define UART ((uart_regs* volatile)(UART_BASE)) \ No newline at end of file From 63427a378eeadeb88d6720f2ee47baf9a50f2210 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 28 Oct 2021 00:44:35 -0500 Subject: [PATCH 058/148] partial link library --- CMakeLists.txt | 4 ++- cmake/add_module.cmake | 49 +++++++++++++++++++++++++++++++++++ src/bl602_wifi/CMakeLists.txt | 31 +++------------------- 3 files changed, 56 insertions(+), 28 deletions(-) create mode 100644 cmake/add_module.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index c5f600a..be544e1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,9 +4,11 @@ set(CMAKE_SYSTEM_PROCESSOR riscv) SET(CMAKE_CROSSCOMPILING 1) set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") -add_compile_options(-std=c11 -march=rv32imfc -mabi=ilp32f) +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -march=rv32imfc -mabi=ilp32f") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=c11 -march=rv32imfc -mabi=ilp32f") project(bl602_re VERSION 0.1.0) include_directories(./src/include) +include(cmake/add_module.cmake) add_subdirectory(./src/bl602_wifi) diff --git a/cmake/add_module.cmake b/cmake/add_module.cmake new file mode 100644 index 0000000..1b53c9f --- /dev/null +++ b/cmake/add_module.cmake @@ -0,0 +1,49 @@ + +function (init_bl602module libname) + set(libname "${libname}" PARENT_SCOPE) + add_library(${libname} STATIC) + target_include_directories(${libname} PRIVATE ${CMAKE_SOURCE_DIR}/src/include/${libname}) +endfunction() + +function (add_bl602module module_name) + file(GLOB lSRCs + "${CMAKE_CURRENT_LIST_DIR}/${module_name}/*.c" + ) + get_property(gSrcs GLOBAL PROPERTY ${libname}_SRCs) + list(APPEND gSrcs ${lSRCs}) + set_property(GLOBAL PROPERTY ${libname}_SRCs "${gSrcs}") + + get_property(NEEDREMOVE GLOBAL PROPERTY ${libname}_NEEDREMOVE) + foreach(blsrc ${lSRCs}) + get_filename_component(wle ${blsrc} NAME_WLE) + list(APPEND NEEDREMOVE ${wle}) + endforeach() + + set_property(GLOBAL PROPERTY ${libname}_NEEDREMOVE "${NEEDREMOVE}") +endfunction() + +function (end_bl602module) + file(GLOB original_OBJs + "${PROJECT_SOURCE_DIR}/lib${libname}/*.o" + ) + + foreach(blobj ${original_OBJs}) + get_filename_component(wle ${blobj} NAME_WLE) + list(APPEND OBJs ${wle}) + endforeach() + + get_property(NEEDREMOVE GLOBAL PROPERTY ${libname}_NEEDREMOVE) + list(REMOVE_ITEM OBJs ${NEEDREMOVE}) + list(TRANSFORM OBJs PREPEND "${PROJECT_SOURCE_DIR}/lib${libname}/") + list(TRANSFORM OBJs APPEND ".o") + set_property(GLOBAL PROPERTY ${libname}_OBJs "${OBJs}") + + get_property(gSrcs GLOBAL PROPERTY ${libname}_SRCs) + target_sources(${libname} PRIVATE ${gSrcs} ${OBJs}) + + message(STATUS "Library info: ${libname}") + message(STATUS "Using Srcs") + message(STATUS "${gSrcs}") + message(STATUS "Using Objs") + message(STATUS "${OBJs}") +endfunction() \ No newline at end of file diff --git a/src/bl602_wifi/CMakeLists.txt b/src/bl602_wifi/CMakeLists.txt index 3a5e008..2dbb21e 100644 --- a/src/bl602_wifi/CMakeLists.txt +++ b/src/bl602_wifi/CMakeLists.txt @@ -1,27 +1,4 @@ - - -file(GLOB bl602_wifi_original_OBJs -"${PROJECT_SOURCE_DIR}/libbl602_wifi/*.o" -) - -file(GLOB bl602_wifi_SRCs -"*.c" -) - -foreach(blsrc ${bl602_wifi_SRCs}) - get_filename_component(wle ${blsrc} NAME_WLE) - list(APPEND NEEDREMOVE ${wle}) -endforeach() - -foreach(blobj ${bl602_wifi_original_OBJs}) - get_filename_component(wle ${blobj} NAME_WLE) - list(APPEND bl602_wifi_OBJs ${wle}) -endforeach() - -list(REMOVE_ITEM bl602_wifi_OBJs ${NEEDREMOVE}) -list(TRANSFORM bl602_wifi_OBJs PREPEND "${PROJECT_SOURCE_DIR}/libbl602_wifi/") -list(TRANSFORM bl602_wifi_OBJs APPEND ".o") - - -add_library(bl602_wifi STATIC ${bl602_wifi_SRCs} ${bl602_wifi_OBJs}) - +init_bl602module("bl602_wifi") +add_bl602module("driver/phy/phy_rf") +add_bl602module("driver/phyif") +end_bl602module() \ No newline at end of file From ad0421491eedc27c5a547b86340bcde402a9b861 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 28 Oct 2021 00:45:26 -0500 Subject: [PATCH 059/148] reg scanner --- blobs/reg_riu.h | 902 ++++++++++++++++++++++++++++ blobs/regdump_44C0B000-44C0CFFF.bin | Bin 0 -> 8192 bytes script/reg.py | 65 ++ 3 files changed, 967 insertions(+) create mode 100644 blobs/reg_riu.h create mode 100644 blobs/regdump_44C0B000-44C0CFFF.bin create mode 100755 script/reg.py diff --git a/blobs/reg_riu.h b/blobs/reg_riu.h new file mode 100644 index 0000000..36c326b --- /dev/null +++ b/blobs/reg_riu.h @@ -0,0 +1,902 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright(c) 2019-2021, Celeno Communications Ltd. */ + +#ifndef CL_REG_RIU_H +#define CL_REG_RIU_H + +#include +#include "reg/reg_access.h" +#include "hw.h" + +#define RIU_RSF_FILE_SIZE 0x60C + +/* + * @brief CCA_CNT_CS register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_CS                0x0
+ *
+ */ +#define RIU_CCA_CNT_CS_ADDR (REG_RIU_BASE_ADDR + 0x00000058) +#define RIU_CCA_CNT_CS_OFFSET 0x00000058 +#define RIU_CCA_CNT_CS_INDEX 0x00000016 +#define RIU_CCA_CNT_CS_RESET 0x00000000 + +static inline u32 riu_cca_cnt_cs_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_CS_ADDR); +} + +/* + * @brief RSF_CONTROL register definition + * resampling filter operation mode register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    rsf_init_en               1
+ *    07    rsf_tx_bypass_type        0
+ *    06    rsf_tx_bypass_mode        1
+ *    05    rsf_rx_bypass_type        0
+ *    04    rsf_rx_bypass_mode        1
+ *    01    rsf_rx_ctl_from_reg       1
+ *
+ */ +#define RIU_RSF_CONTROL_ADDR (REG_RIU_BASE_ADDR + 0x000001A8) +#define RIU_RSF_CONTROL_OFFSET 0x000001A8 +#define RIU_RSF_CONTROL_INDEX 0x0000006A +#define RIU_RSF_CONTROL_RESET 0x80000053 + +static inline void riu_rsf_control_rsf_init_en_setf(struct cl_hw *cl_hw, u8 rsfiniten) +{ + cl_reg_write(cl_hw, RIU_RSF_CONTROL_ADDR, + (cl_reg_read(cl_hw, RIU_RSF_CONTROL_ADDR) & ~((u32)0x80000000)) | ((u32)rsfiniten << 31)); +} + +/* + * @brief RSF_INIT register definition + * resampling filter initialization data register description + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 RSF_INIT_DATA             0x0
+ *
+ */ +#define RIU_RSF_INIT_ADDR (REG_RIU_BASE_ADDR + 0x000001AC) +#define RIU_RSF_INIT_OFFSET 0x000001AC +#define RIU_RSF_INIT_INDEX 0x0000006B +#define RIU_RSF_INIT_RESET 0x00000000 + +static inline void riu_rsf_init_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, RIU_RSF_INIT_ADDR, value); +} + +/* + * @brief AGCFSM_RAM_INIT_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    AGC_FSM_RAM_INIT_EN       0
+ *    29    AGC_FSM_RAM_INIT_AINC2    0
+ *    28    AGC_FSM_RAM_INIT_AINC1    0
+ *    12    AGC_FSM_RAM_INIT_WPTR_SET 0
+ *    10:00 AGC_FSM_RAM_INIT_WPTR     0x0
+ *
+ */ +#define RIU_AGCFSM_RAM_INIT_1_ADDR (REG_RIU_BASE_ADDR + 0x000001B0) +#define RIU_AGCFSM_RAM_INIT_1_OFFSET 0x000001B0 +#define RIU_AGCFSM_RAM_INIT_1_INDEX 0x0000006C +#define RIU_AGCFSM_RAM_INIT_1_RESET 0x00000000 + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_wptr_setf(struct cl_hw *cl_hw, + u16 agcfsmraminitwptr) +{ + ASSERT_ERR((((u32)agcfsmraminitwptr << 0) & ~((u32)0x000007FF)) == 0); + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x000007FF)) | ((u32)agcfsmraminitwptr << 0)); +} + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_wptr_set_setf(struct cl_hw *cl_hw, u8 agcfsmraminitwptrset) +{ + ASSERT_ERR((((u32)agcfsmraminitwptrset << 12) & ~((u32)0x00001000)) == 0); + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x00001000)) | ((u32)agcfsmraminitwptrset << 12)); +} + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_ainc_1_setf(struct cl_hw *cl_hw, + u8 agcfsmraminitainc1) +{ + ASSERT_ERR((((u32)agcfsmraminitainc1 << 28) & ~((u32)0x10000000)) == 0); + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x10000000)) | ((u32)agcfsmraminitainc1 << 28)); +} + +static inline void riu_agcfsm_ram_init_1_agc_fsm_ram_init_en_setf(struct cl_hw *cl_hw, + u8 agcfsmraminiten) +{ + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR, + (cl_reg_read(cl_hw, RIU_AGCFSM_RAM_INIT_1_ADDR) & ~((u32)0x80000000)) | ((u32)agcfsmraminiten << 31)); +} + +/* + * @brief AGCFSM_RAM_INIT_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 AGC_FSM_RAM_INIT_WDATA    0x0
+ *
+ */ +#define RIU_AGCFSM_RAM_INIT_2_ADDR (REG_RIU_BASE_ADDR + 0x000001B4) +#define RIU_AGCFSM_RAM_INIT_2_OFFSET 0x000001B4 +#define RIU_AGCFSM_RAM_INIT_2_INDEX 0x0000006D +#define RIU_AGCFSM_RAM_INIT_2_RESET 0x00000000 + +static inline void riu_agcfsm_ram_init_2_set(struct cl_hw *cl_hw, u32 value) +{ + cl_reg_write(cl_hw, RIU_AGCFSM_RAM_INIT_2_ADDR, value); +} + +/* + * @brief AGCINBDPOW_20_STAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PDBM3           0x0
+ *    23:16 INBDPOW20_PDBM2           0x0
+ *    15:08 INBDPOW20_PDBM1           0x0
+ *    07:00 INBDPOW20_PDBM0           0x0
+ *
+ */ +#define RIU_AGCINBDPOW_20_STAT_ADDR (REG_RIU_BASE_ADDR + 0x0000020C) +#define RIU_AGCINBDPOW_20_STAT_OFFSET 0x0000020C +#define RIU_AGCINBDPOW_20_STAT_INDEX 0x00000083 +#define RIU_AGCINBDPOW_20_STAT_RESET 0x00000000 + +static inline void riu_agcinbdpow_20_stat_unpack(struct cl_hw *cl_hw, + u8 *inbdpow20pdbm3, u8 *inbdpow20pdbm2, + u8 *inbdpow20pdbm1, u8 *inbdpow20pdbm0) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_AGCINBDPOW_20_STAT_ADDR); + + *inbdpow20pdbm3 = (local_val & ((u32)0xFF000000)) >> 24; + *inbdpow20pdbm2 = (local_val & ((u32)0x00FF0000)) >> 16; + *inbdpow20pdbm1 = (local_val & ((u32)0x0000FF00)) >> 8; + *inbdpow20pdbm0 = (local_val & ((u32)0x000000FF)) >> 0; +} + +/* + * @brief AGCINBDPOW_20_PNOISESTAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PNOISEDBM3      0x0
+ *    23:16 INBDPOW20_PNOISEDBM2      0x0
+ *    15:08 INBDPOW20_PNOISEDBM1      0x0
+ *    07:00 INBDPOW20_PNOISEDBM0      0x0
+ *
+ */ +#define RIU_AGCINBDPOW_20_PNOISESTAT_ADDR (REG_RIU_BASE_ADDR + 0x00000228) +#define RIU_AGCINBDPOW_20_PNOISESTAT_OFFSET 0x00000228 +#define RIU_AGCINBDPOW_20_PNOISESTAT_INDEX 0x0000008A +#define RIU_AGCINBDPOW_20_PNOISESTAT_RESET 0x00000000 + +static inline u32 riu_agcinbdpow_20_pnoisestat_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOW_20_PNOISESTAT_ADDR); +} + +/* + * @brief AGCINBDPOWSECNOISESTAT register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    23:16 INBDPOW80_SNOISEDBM       0x0
+ *    15:08 INBDPOW40_SNOISEDBM       0x0
+ *    07:00 INBDPOW20_SNOISEDBM       0x0
+ *
+ */ +#define RIU_AGCINBDPOWSECNOISESTAT_ADDR (REG_RIU_BASE_ADDR + 0x00000230) +#define RIU_AGCINBDPOWSECNOISESTAT_OFFSET 0x00000230 +#define RIU_AGCINBDPOWSECNOISESTAT_INDEX 0x0000008C +#define RIU_AGCINBDPOWSECNOISESTAT_RESET 0x00000000 + +static inline u32 riu_agcinbdpowsecnoisestat_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOWSECNOISESTAT_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_P register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_P     0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_P_ADDR (REG_RIU_BASE_ADDR + 0x000002DC) +#define RIU_CCA_CNT_MODEM_STATE_P_OFFSET 0x000002DC +#define RIU_CCA_CNT_MODEM_STATE_P_INDEX 0x000000B7 +#define RIU_CCA_CNT_MODEM_STATE_P_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_p_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_P_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_20_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_20_S  0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_20_S_ADDR (REG_RIU_BASE_ADDR + 0x000002E0) +#define RIU_CCA_CNT_MODEM_STATE_20_S_OFFSET 0x000002E0 +#define RIU_CCA_CNT_MODEM_STATE_20_S_INDEX 0x000000B8 +#define RIU_CCA_CNT_MODEM_STATE_20_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_20_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_20_S_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_40_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_40_S  0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_40_S_ADDR (REG_RIU_BASE_ADDR + 0x000002E4) +#define RIU_CCA_CNT_MODEM_STATE_40_S_OFFSET 0x000002E4 +#define RIU_CCA_CNT_MODEM_STATE_40_S_INDEX 0x000000B9 +#define RIU_CCA_CNT_MODEM_STATE_40_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_40_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_40_S_ADDR); +} + +/* + * @brief CCA_CNT_MODEM_STATE_80_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_MODEM_STATE_80_S  0x0
+ *
+ */ +#define RIU_CCA_CNT_MODEM_STATE_80_S_ADDR (REG_RIU_BASE_ADDR + 0x000002E8) +#define RIU_CCA_CNT_MODEM_STATE_80_S_OFFSET 0x000002E8 +#define RIU_CCA_CNT_MODEM_STATE_80_S_INDEX 0x000000BA +#define RIU_CCA_CNT_MODEM_STATE_80_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_modem_state_80_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_MODEM_STATE_80_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_P register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_P      0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_P_ADDR (REG_RIU_BASE_ADDR + 0x000002F4) +#define RIU_CCA_CNT_ENERGY_THR_P_OFFSET 0x000002F4 +#define RIU_CCA_CNT_ENERGY_THR_P_INDEX 0x000000BD +#define RIU_CCA_CNT_ENERGY_THR_P_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_p_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_P_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_S   0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_S_ADDR (REG_RIU_BASE_ADDR + 0x000002F8) +#define RIU_CCA_CNT_ENERGY_THR_20_S_OFFSET 0x000002F8 +#define RIU_CCA_CNT_ENERGY_THR_20_S_INDEX 0x000000BE +#define RIU_CCA_CNT_ENERGY_THR_20_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_S_ADDR); +} + +/* + * @brief CCA_CNT_GI_20_P register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_20_P           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_20_P_ADDR (REG_RIU_BASE_ADDR + 0x000002FC) +#define RIU_CCA_CNT_GI_20_P_OFFSET 0x000002FC +#define RIU_CCA_CNT_GI_20_P_INDEX 0x000000BF +#define RIU_CCA_CNT_GI_20_P_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_20_p_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_20_P_ADDR); +} + +/* + * @brief RWNXAGCRAMP register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    26:24 RAMPDNNDLINDEX            0x5
+ *    23:16 RAMPDNGAPQDB              0x20
+ *    10:08 RAMPUPNDLINDEX            0x7
+ *    07:00 RAMPUPGAPQDB              0x10
+ *
+ */ +#define RIU_RWNXAGCRAMP_ADDR (REG_RIU_BASE_ADDR + 0x0000036C) +#define RIU_RWNXAGCRAMP_OFFSET 0x0000036C +#define RIU_RWNXAGCRAMP_INDEX 0x000000DB +#define RIU_RWNXAGCRAMP_RESET 0x05200710 + +static inline u8 riu_rwnxagcramp_rampupgapqdb_getf(struct cl_hw *cl_hw) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_RWNXAGCRAMP_ADDR); + + return ((local_val & ((u32)0x000000FF)) >> 0); +} + +static inline void riu_rwnxagcramp_rampupgapqdb_setf(struct cl_hw *cl_hw, u8 rampupgapqdb) +{ + cl_reg_write(cl_hw, RIU_RWNXAGCRAMP_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCRAMP_ADDR) & ~((u32)0x000000FF)) | ((u32)rampupgapqdb << 0)); +} + +/* + * @brief RWNXAGCCNTL register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:26 COMBPATHSEL               0x3F
+ *    25:20 GAINKEEP                  0x0
+ *    16    HTSTFGAINEN               1
+ *    15    NOISE_CAPTURE_DELAY_MODE  0
+ *    14    EST_PATH_SEL_2            0
+ *    13    CCA_MDM_ST_CLEAR          0
+ *    12    AGCFSMRESET               0
+ *    11    RADARDETEN                0
+ *    10    RIFSDETEN                 1
+ *    09    DSSSONLY                  0
+ *    08    OFDMONLY                  0
+ *    07:04 GPSTATUS                  0x0
+ *    03    EST_PATH_SEL              0
+ *    01    ADC_SEL_RADAR_DETECTOR    0
+ *    00    ADC_SEL_COMP_MODULE       0
+ *
+ */ +#define RIU_RWNXAGCCNTL_ADDR (REG_RIU_BASE_ADDR + 0x00000390) +#define RIU_RWNXAGCCNTL_OFFSET 0x00000390 +#define RIU_RWNXAGCCNTL_INDEX 0x000000E4 +#define RIU_RWNXAGCCNTL_RESET 0xFC010400 + +static inline void riu_rwnxagccntl_agcfsmreset_setf(struct cl_hw *cl_hw, u8 agcfsmreset) +{ + ASSERT_ERR((((u32)agcfsmreset << 12) & ~((u32)0x00001000)) == 0); + cl_reg_write(cl_hw, RIU_RWNXAGCCNTL_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCNTL_ADDR) & ~((u32)0x00001000)) | ((u32)agcfsmreset << 12)); +} + +/* + * @brief RWNXAGCCCA_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31    CCA_CNT_CLEAR             0
+ *    30:29 CCA_CNT_RATE              0x0
+ *    28:20 INBDCCAPOWMINDBM          0x1B5
+ *    19:12 CCAFALLTHRDBM             0xBF
+ *    10    CCAEnergy_Reset_Type      0
+ *    09    DISCCAEN                  1
+ *    08    SATCCAEN                  1
+ *    07:00 CCARISETHRDBM             0xC2
+ *
+ */ +#define RIU_RWNXAGCCCA_1_ADDR (REG_RIU_BASE_ADDR + 0x000003AC) +#define RIU_RWNXAGCCCA_1_OFFSET 0x000003AC +#define RIU_RWNXAGCCCA_1_INDEX 0x000000EB +#define RIU_RWNXAGCCCA_1_RESET 0x1B5BF3C2 + +static inline void riu_rwnxagccca_1_cca_cnt_clear_setf(struct cl_hw *cl_hw, u8 ccacntclear) +{ + cl_reg_write(cl_hw, RIU_RWNXAGCCCA_1_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCCA_1_ADDR) & ~((u32)0x80000000)) | ((u32)ccacntclear << 31)); +} + +/* + * @brief RWNXAGCCCACTRL register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:28 CCAFLAG3_CTRL             0xA
+ *    27:24 CCAFLAG2_CTRL             0x2
+ *    23:20 CCAFLAG1_CTRL             0x8
+ *    19:16 CCAFLAG0_CTRL             0x0
+ *    14:12 CCA_SECOND_ANT_SEL        0x1
+ *    10:08 CCA_MAIN_ANT_SEL          0x0
+ *    07:04 CCADEMOD                  0xF
+ *    00    CCACSEN                   1
+ *
+ */ +#define RIU_RWNXAGCCCACTRL_ADDR (REG_RIU_BASE_ADDR + 0x000003B0) +#define RIU_RWNXAGCCCACTRL_OFFSET 0x000003B0 +#define RIU_RWNXAGCCCACTRL_INDEX 0x000000EC +#define RIU_RWNXAGCCCACTRL_RESET 0xA28010F1 + +static inline void riu_rwnxagcccactrl_cca_main_ant_sel_setf(struct cl_hw *cl_hw, u8 ccamainantsel) +{ + ASSERT_ERR((((u32)ccamainantsel << 8) & ~((u32)0x00000700)) == 0); + cl_reg_write(cl_hw, RIU_RWNXAGCCCACTRL_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCCACTRL_ADDR) & ~((u32)0x00000700)) | ((u32)ccamainantsel << 8)); +} + +/* + * @brief RWNXAGCCCASTATE_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    28    CCAMDMSTFORCEEN           0
+ *    27:24 CCAMDMSTFORCE             0x0
+ *    23:12 RXSTATECCA20_SSEL         0x380
+ *    11:00 RXSTATECCA20_PSEL         0x3F8
+ *
+ */ +#define RIU_RWNXAGCCCASTATE_0_ADDR (REG_RIU_BASE_ADDR + 0x000003B4) +#define RIU_RWNXAGCCCASTATE_0_OFFSET 0x000003B4 +#define RIU_RWNXAGCCCASTATE_0_INDEX 0x000000ED +#define RIU_RWNXAGCCCASTATE_0_RESET 0x003803F8 + +static inline void riu_rwnxagcccastate_0_rxstatecca_20_psel_setf(struct cl_hw *cl_hw, + u16 rxstatecca20psel) +{ + ASSERT_ERR((((u32)rxstatecca20psel << 0) & ~((u32)0x00000FFF)) == 0); + cl_reg_write(cl_hw, RIU_RWNXAGCCCASTATE_0_ADDR, + (cl_reg_read(cl_hw, RIU_RWNXAGCCCASTATE_0_ADDR) & ~((u32)0x00000FFF)) | ((u32)rxstatecca20psel << 0)); +} + +/* + * @brief AGCINBDPOWNOISEPER_20_STAT_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWNOISEDBMPER20_3    0x0
+ *    23:16 INBDPOWNOISEDBMPER20_2    0x0
+ *    15:08 INBDPOWNOISEDBMPER20_1    0x0
+ *    07:00 INBDPOWNOISEDBMPER20_0    0x0
+ *
+ */ +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_ADDR (REG_RIU_BASE_ADDR + 0x00000478) +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_OFFSET 0x00000478 +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_INDEX 0x0000011E +#define RIU_AGCINBDPOWNOISEPER_20_STAT_0_RESET 0x00000000 + +static inline u32 riu_agcinbdpownoiseper_20_stat_0_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOWNOISEPER_20_STAT_0_ADDR); +} + +/* + * @brief AGCINBDPOWNOISEPER_20_STAT_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWNOISEDBMPER20_7    0x0
+ *    23:16 INBDPOWNOISEDBMPER20_6    0x0
+ *    15:08 INBDPOWNOISEDBMPER20_5    0x0
+ *    07:00 INBDPOWNOISEDBMPER20_4    0x0
+ *
+ */ +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_ADDR (REG_RIU_BASE_ADDR + 0x0000047C) +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_OFFSET 0x0000047C +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_INDEX 0x0000011F +#define RIU_AGCINBDPOWNOISEPER_20_STAT_1_RESET 0x00000000 + +static inline u32 riu_agcinbdpownoiseper_20_stat_1_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOWNOISEPER_20_STAT_1_ADDR); +} + +/* + * @brief INBDPOWFORMAC_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PDBMA3_MAC      0x0
+ *    23:16 INBDPOW20_PDBMA2_MAC      0x0
+ *    15:08 INBDPOW20_PDBMA1_MAC      0x0
+ *    07:00 INBDPOW20_PDBMA0_MAC      0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_0_ADDR (REG_RIU_BASE_ADDR + 0x00000480) +#define RIU_INBDPOWFORMAC_0_OFFSET 0x00000480 +#define RIU_INBDPOWFORMAC_0_INDEX 0x00000120 +#define RIU_INBDPOWFORMAC_0_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_0_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_0_ADDR); +} + +/* + * @brief INBDPOWFORMAC_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    15:08 INBDPOW20_PDBMA5_MAC      0x0
+ *    07:00 INBDPOW20_PDBMA4_MAC      0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_1_ADDR (REG_RIU_BASE_ADDR + 0x00000484) +#define RIU_INBDPOWFORMAC_1_OFFSET 0x00000484 +#define RIU_INBDPOWFORMAC_1_INDEX 0x00000121 +#define RIU_INBDPOWFORMAC_1_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_1_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_1_ADDR); +} + +/* + * @brief INBDPOWFORMAC_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    23:16 INBDPOW80_SDBM_MAC        0x0
+ *    15:08 INBDPOW40_SDBM_MAC        0x0
+ *    07:00 INBDPOW20_SDBM_MAC        0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_2_ADDR (REG_RIU_BASE_ADDR + 0x00000488) +#define RIU_INBDPOWFORMAC_2_OFFSET 0x00000488 +#define RIU_INBDPOWFORMAC_2_INDEX 0x00000122 +#define RIU_INBDPOWFORMAC_2_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_2_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_2_ADDR); +} + +/* + * @brief INBDPOWFORMAC_3 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWPER20_PDBM_3_MAC   0x0
+ *    23:16 INBDPOWPER20_PDBM_2_MAC   0x0
+ *    15:08 INBDPOWPER20_PDBM_1_MAC   0x0
+ *    07:00 INBDPOWPER20_PDBM_0_MAC   0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_3_ADDR (REG_RIU_BASE_ADDR + 0x0000048C) +#define RIU_INBDPOWFORMAC_3_OFFSET 0x0000048C +#define RIU_INBDPOWFORMAC_3_INDEX 0x00000123 +#define RIU_INBDPOWFORMAC_3_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_3_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_3_ADDR); +} + +/* + * @brief INBDPOWFORMAC_4 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOWPER20_PDBM_7_MAC   0x0
+ *    23:16 INBDPOWPER20_PDBM_6_MAC   0x0
+ *    15:08 INBDPOWPER20_PDBM_5_MAC   0x0
+ *    07:00 INBDPOWPER20_PDBM_4_MAC   0x0
+ *
+ */ +#define RIU_INBDPOWFORMAC_4_ADDR (REG_RIU_BASE_ADDR + 0x00000490) +#define RIU_INBDPOWFORMAC_4_OFFSET 0x00000490 +#define RIU_INBDPOWFORMAC_4_INDEX 0x00000124 +#define RIU_INBDPOWFORMAC_4_RESET 0x00000000 + +static inline u32 riu_inbdpowformac_4_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_INBDPOWFORMAC_4_ADDR); +} + +/* + * @brief CCA_CNT_GI_20_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_20_S           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_20_S_ADDR (REG_RIU_BASE_ADDR + 0x00000494) +#define RIU_CCA_CNT_GI_20_S_OFFSET 0x00000494 +#define RIU_CCA_CNT_GI_20_S_INDEX 0x00000125 +#define RIU_CCA_CNT_GI_20_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_20_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_20_S_ADDR); +} + +/* + * @brief CCA_CNT_GI_40_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_40_S           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_40_S_ADDR (REG_RIU_BASE_ADDR + 0x00000498) +#define RIU_CCA_CNT_GI_40_S_OFFSET 0x00000498 +#define RIU_CCA_CNT_GI_40_S_INDEX 0x00000126 +#define RIU_CCA_CNT_GI_40_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_40_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_40_S_ADDR); +} + +/* + * @brief CCA_CNT_GI_80_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_GI_80_S           0x0
+ *
+ */ +#define RIU_CCA_CNT_GI_80_S_ADDR (REG_RIU_BASE_ADDR + 0x0000049C) +#define RIU_CCA_CNT_GI_80_S_OFFSET 0x0000049C +#define RIU_CCA_CNT_GI_80_S_INDEX 0x00000127 +#define RIU_CCA_CNT_GI_80_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_gi_80_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_GI_80_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_40_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_40_S   0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_40_S_ADDR (REG_RIU_BASE_ADDR + 0x000004A0) +#define RIU_CCA_CNT_ENERGY_THR_40_S_OFFSET 0x000004A0 +#define RIU_CCA_CNT_ENERGY_THR_40_S_INDEX 0x00000128 +#define RIU_CCA_CNT_ENERGY_THR_40_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_40_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_40_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_80_S register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_80_S   0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_80_S_ADDR (REG_RIU_BASE_ADDR + 0x000004A4) +#define RIU_CCA_CNT_ENERGY_THR_80_S_OFFSET 0x000004A4 +#define RIU_CCA_CNT_ENERGY_THR_80_S_INDEX 0x00000129 +#define RIU_CCA_CNT_ENERGY_THR_80_S_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_80_s_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_80_S_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_0 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_0 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_ADDR (REG_RIU_BASE_ADDR + 0x000004A8) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_OFFSET 0x000004A8 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_INDEX 0x0000012A +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_0_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_0_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_0_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_1 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_1 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_ADDR (REG_RIU_BASE_ADDR + 0x000004AC) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_OFFSET 0x000004AC +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_INDEX 0x0000012B +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_1_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_1_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_1_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_2 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_ADDR (REG_RIU_BASE_ADDR + 0x000004B0) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_OFFSET 0x000004B0 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_INDEX 0x0000012C +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_2_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_2_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_2_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_3 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_3 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_ADDR (REG_RIU_BASE_ADDR + 0x000004B4) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_OFFSET 0x000004B4 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_INDEX 0x0000012D +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_3_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_3_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_3_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_4 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_4 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_ADDR (REG_RIU_BASE_ADDR + 0x000004B8) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_OFFSET 0x000004B8 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_INDEX 0x0000012E +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_4_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_4_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_4_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_5 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_5 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_ADDR (REG_RIU_BASE_ADDR + 0x000004BC) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_OFFSET 0x000004BC +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_INDEX 0x0000012F +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_5_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_5_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_5_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_6 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_6 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_ADDR (REG_RIU_BASE_ADDR + 0x000004C0) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_OFFSET 0x000004C0 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_INDEX 0x00000130 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_6_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_6_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_6_ADDR); +} + +/* + * @brief CCA_CNT_ENERGY_THR_20_BAND_7 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 CCA_CNT_ENERGY_THR_20_BAND_7 0x0
+ *
+ */ +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_ADDR (REG_RIU_BASE_ADDR + 0x000004C4) +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_OFFSET 0x000004C4 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_INDEX 0x00000131 +#define RIU_CCA_CNT_ENERGY_THR_20_BAND_7_RESET 0x00000000 + +static inline u32 riu_cca_cnt_energy_thr_20_band_7_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_CCA_CNT_ENERGY_THR_20_BAND_7_ADDR); +} + +/* + * @brief AGCADCPOWSTAT_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PDBM5           0x0
+ *    23:16 INBDPOW20_PDBM4           0x0
+ *    14:08 ADCPOWDBV5                0x0
+ *    06:00 ADCPOWDBV4                0x0
+ *
+ */ +#define RIU_AGCADCPOWSTAT_2_ADDR (REG_RIU_BASE_ADDR + 0x00000670) +#define RIU_AGCADCPOWSTAT_2_OFFSET 0x00000670 +#define RIU_AGCADCPOWSTAT_2_INDEX 0x0000019C +#define RIU_AGCADCPOWSTAT_2_RESET 0x00000000 + +static inline void riu_agcadcpowstat_2_unpack(struct cl_hw *cl_hw, + u8 *inbdpow20pdbm5, u8 *inbdpow20pdbm4, + u8 *adcpowdbv5, u8 *adcpowdbv4) +{ + u32 local_val = cl_reg_read(cl_hw, RIU_AGCADCPOWSTAT_2_ADDR); + + *inbdpow20pdbm5 = (local_val & ((u32)0xFF000000)) >> 24; + *inbdpow20pdbm4 = (local_val & ((u32)0x00FF0000)) >> 16; + *adcpowdbv5 = (local_val & ((u32)0x00007F00)) >> 8; + *adcpowdbv4 = (local_val & ((u32)0x0000007F)) >> 0; +} + +/* + * @brief AGCINBDPOW_20_PNOISESTAT_2 register definition + * 
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 INBDPOW20_PNOISEDBM5      0x0
+ *    23:16 INBDPOW20_PNOISEDBM4      0x0
+ *    15:08 ADCPOWDBM5                0x0
+ *    07:00 ADCPOWDBM4                0x0
+ *
+ */ +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_ADDR (REG_RIU_BASE_ADDR + 0x0000067C) +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_OFFSET 0x0000067C +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_INDEX 0x0000019F +#define RIU_AGCINBDPOW_20_PNOISESTAT_2_RESET 0x00000000 + +static inline u32 riu_agcinbdpow_20_pnoisestat_2_get(struct cl_hw *cl_hw) +{ + return cl_reg_read(cl_hw, RIU_AGCINBDPOW_20_PNOISESTAT_2_ADDR); +} + +#endif /*_REG_RIU_H_ */ \ No newline at end of file diff --git a/blobs/regdump_44C0B000-44C0CFFF.bin b/blobs/regdump_44C0B000-44C0CFFF.bin new file mode 100644 index 0000000000000000000000000000000000000000..b82bd3689ab3322a6ba506c779381cdfc479d362 GIT binary patch literal 8192 zcmWf1+`=%Dfr5ep0|+y)07C(U844I4nM_gvu@GWl-Y79#L%@l_iCnL-v$8NTLNyEU za&xjWGcz#)1r%hZB}4@H`M5Y37%VMpI69g%7zEfASUH$OI2c3(g_#(bfHFYRrQkQK z3qv5siQ-W14(1eQ7NF*>KX@4CKn$J3@R^&LnSp_mGnC=b=V zb1-b(prNsE|Lwa_CxEFP0o>9cj4U?F#vTF!0^m%KU2;@(Gz5lu2ndeW|D*N)Fi+zI zy*FC_6AYr^s$jJKAFeSw>MvqKKme*p(U64!gp&=_7!nxN7y=kr;TWVO0EmGd79d!_ zAO)rw7??rbriOzVPzk6gX_Sztl!BVJp}8$-+J=p46-5~_0WM%Ka@hE2)FY!IFd71* zAut*OLm>qCA(cAJsR|%Q2aJbCAGyTO!0Yni4--h7k)c5WSo?#p1cL#C2T+KE2iBSZ ia)uOOV*n2L3k@kJk2-cV1V%$(Gz3ONU^E0M2mt`52T)}I literal 0 HcmV?d00001 diff --git a/script/reg.py b/script/reg.py new file mode 100755 index 0000000..ebf1e86 --- /dev/null +++ b/script/reg.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python3 +def RegFromComment2(comment:str): + import re + field_pattern = r'\*\s+(\d\d)(:(\d\d))*\s*([^\s]+)\s+(.*)' + + field_matches = re.finditer(field_pattern, comment) + + for g in field_matches: + fname = g.group(4) + msb = int(g.group(1)) + lsb = g.group(3) + val = g.group(5) + if val.startswith("0x"): + val = int(val, 16) + else: + val = int(val) + if not lsb: + lsb = msb + else: + lsb = int(lsb) + yield fname, msb, lsb, val + + +def getregs(fname, pattern='name'): + import re + state = "idle" + regs = [] + if pattern == 'name': + name_pattern = r'\* @(name) ([^\s]+)' + else: + name_pattern = r'\* @(brief) ([^\s]+)' + addr_pattern = r'#define .*_OFFSET\s+0x([0-9A-F]+)' + name = '' + for i in open(fname).readlines(): + if state == "idle": + g = re.search(name_pattern, i) + if g: + name = g.group(2) + regs.append(i) + state = "find_reg" + elif state == "find_reg": + g = re.search(addr_pattern, i) + if g: + yield name, "".join(regs), int(g.group(1), 16) & 0xFFFFF + regs.clear() + state = "idle" + else: + regs.append(i) + + +binfile = open("../blobs/regdump_44C0B000-44C0CFFF.bin", "rb").read(0x2000) + + +import struct +for rname, r, offset in getregs('../blobs/reg_riu.h', pattern='brief'): + regdefault = binfile[offset:offset+4] + print(regdefault) + regdefault = int.from_bytes(regdefault, byteorder='little') + matched = True + print(f"Reg {rname}, val {regdefault} offset {hex(offset)}") + for name, msb, lsb, val in RegFromComment2(r): + vreset = (regdefault >> lsb) & ((2**(msb - lsb+1) - 1)) + print(f"\t{name}, expected {hex(val)}, get {hex(vreset)}") + if vreset != val: + matched = False From 9f91b711557aa1934339a659ab7960d71e309eee Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 28 Oct 2021 00:47:10 -0500 Subject: [PATCH 060/148] preliminary decompiled code --- .../driver/phy/phy_rf/bl602_rf_calib_data.c | 10 + .../driver/phy/phy_rf/bl602_rf_private.c | 1727 +++++++++++++++++ src/bl602_wifi/driver/phy/phy_rf/macro.h | 47 + .../{ => driver/phy/phy_rf}/phy_adapt.c | 10 +- .../{ => driver/phy/phy_rf}/phy_bl602.c | 151 +- .../{ => driver/phy/phy_rf}/phy_hal.c | 2 +- .../{ => driver/phy/phy_rf}/phy_helper.c | 2 +- .../{ => driver/phy/phy_rf}/phy_tcal.c | 14 +- .../{ => driver/phy/phy_rf}/phy_trpc.c | 8 +- src/bl602_wifi/{ => driver/phy/phy_rf}/rf.c | 12 +- .../driver/phy/phy_rf/rf_private_save.h | 29 + src/bl602_wifi/driver/phy/phy_rf/rfc_bl602.c | 784 ++++++++ .../{ => driver/phyif}/phyif_utils.c | 2 +- src/bl602_wifi/phy.h | 8 - src/bl602_wifi/rfc_bl602.c | 169 -- src/bl602_wifi/rfc_bl602.h | 9 - src/{bl602_wifi => include}/assert.h | 0 .../bl602_wifi/phy_rf/bl602_rf_calib_data.h | 58 + .../bl602_wifi/phy_rf}/bl602_rf_private.h | 77 +- .../bl602_wifi/phy_rf}/hal_desc.h | 13 +- src/include/bl602_wifi/phy_rf/phy.h | 74 + .../bl602_wifi/phy_rf}/phy_adapt.h | 2 +- .../bl602_wifi/phy_rf}/phy_bl602.h | 36 +- .../bl602_wifi/phy_rf}/phy_hal.h | 0 .../bl602_wifi/phy_rf}/phy_helper.h | 0 .../bl602_wifi/phy_rf}/phy_tcal.h | 0 .../bl602_wifi/phy_rf}/phy_trpc.h | 0 .../bl602_wifi/phy_rf}/rf.h | 0 src/include/bl602_wifi/phy_rf/rfc_bl602.h | 199 ++ .../bl602_wifi/phyif}/phyif_utils.h | 0 src/{bl602_wifi => include}/utils.h | 2 +- 31 files changed, 3161 insertions(+), 284 deletions(-) create mode 100644 src/bl602_wifi/driver/phy/phy_rf/bl602_rf_calib_data.c create mode 100644 src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c create mode 100644 src/bl602_wifi/driver/phy/phy_rf/macro.h rename src/bl602_wifi/{ => driver/phy/phy_rf}/phy_adapt.c (97%) rename src/bl602_wifi/{ => driver/phy/phy_rf}/phy_bl602.c (74%) rename src/bl602_wifi/{ => driver/phy/phy_rf}/phy_hal.c (97%) rename src/bl602_wifi/{ => driver/phy/phy_rf}/phy_helper.c (99%) rename src/bl602_wifi/{ => driver/phy/phy_rf}/phy_tcal.c (87%) rename src/bl602_wifi/{ => driver/phy/phy_rf}/phy_trpc.c (96%) rename src/bl602_wifi/{ => driver/phy/phy_rf}/rf.c (52%) create mode 100644 src/bl602_wifi/driver/phy/phy_rf/rf_private_save.h create mode 100644 src/bl602_wifi/driver/phy/phy_rf/rfc_bl602.c rename src/bl602_wifi/{ => driver/phyif}/phyif_utils.c (98%) delete mode 100644 src/bl602_wifi/phy.h delete mode 100644 src/bl602_wifi/rfc_bl602.c delete mode 100644 src/bl602_wifi/rfc_bl602.h rename src/{bl602_wifi => include}/assert.h (100%) create mode 100644 src/include/bl602_wifi/phy_rf/bl602_rf_calib_data.h rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/bl602_rf_private.h (62%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/hal_desc.h (91%) create mode 100644 src/include/bl602_wifi/phy_rf/phy.h rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/phy_adapt.h (98%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/phy_bl602.h (87%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/phy_hal.h (100%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/phy_helper.h (100%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/phy_tcal.h (100%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/phy_trpc.h (100%) rename src/{bl602_wifi => include/bl602_wifi/phy_rf}/rf.h (100%) create mode 100644 src/include/bl602_wifi/phy_rf/rfc_bl602.h rename src/{bl602_wifi => include/bl602_wifi/phyif}/phyif_utils.h (100%) rename src/{bl602_wifi => include}/utils.h (90%) diff --git a/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_calib_data.c b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_calib_data.c new file mode 100644 index 0000000..db68925 --- /dev/null +++ b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_calib_data.c @@ -0,0 +1,10 @@ +#include + +#if 0 +#define RF_CALIB_DATA_ADDR (0x40020000) + +rf_calib_data_tag* rf_calib_data = (rf_calib_data_tag *)RF_CALIB_DATA_ADDR; +#else +static rf_calib_data_tag data = {0}; +rf_calib_data_tag* rf_calib_data = &data; +#endif \ No newline at end of file diff --git a/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c new file mode 100644 index 0000000..1d42423 --- /dev/null +++ b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c @@ -0,0 +1,1727 @@ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define kHz *1000 +#define MHz *1000*1000 +#define NUM_CHANNELS (21) +#define NUM_WIFI_CHANNELS (14) + +static uint32_t channel_div_table[21] = { + 0x14088889, 0x14111111, 0x1419999A, 0x14222222, + 0x142AAAAB, 0x14333333, 0x143BBBBC, 0x14444444, + 0x144CCCCD, 0x14555555, 0x145DDDDE, 0x14666666, + 0x146EEEEF, 0x14777777, 0x14800000, 0x14888889, + 0x14911111, 0x1499999A, 0x14A22222, 0x14AAAAAB, + 0x14B33333 +}; + +static uint16_t channel_cnt_table[21] = { + 0xA6EB, 0xA732, 0xA779, 0xA7C0, + 0xA808, 0xA84F, 0xA896, 0xA8DD, + 0xA924, 0xA96B, 0xA9B2, 0xA9F9, + 0xAA40, 0xAA87, 0xAACF, 0xAB16, + 0xAB5D, 0xABA4, 0xABEB, 0xAC32, + 0xAC79 +}; + +static uint16_t fcal_div = 0x855; + +static tx_pwr_index data; +tx_pwr_index* tp_index = &data; + +void rf_pri_config_bandwidth(uint32_t bw) { + RF->rbb3.rbb_bw = bw; +} + +static uint16_t channel_cnt_range[3] = { + 0xA6A0, 0xA6E0, 0xACE0 +}; + +static uint16_t channel_cw_table[21]; +static uint16_t channel_cnt_opt_table[40]; + +// meas = measure? +uint16_t rf_pri_fcal_meas(uint32_t cw) { + RF->vco1.lo_vco_freq_cw = cw; + BL602_Delay_US(100); + RF->vco4.fcal_cnt_start = 1; + do { + if (RF->vco4.fcal_cnt_rdy) break; + } while (1); + uint16_t fcal_meas = RF->vco3.fcal_cnt_op; + RF->vco4.fcal_cnt_start = 0; + return fcal_meas; +} + +typedef struct { +#define RF_PRI_SAVE(field) uint32_t field; +#include "rf_private_save.h" +} rf_state_save_t; + +static rf_state_save_t rf_state; + +static void rf_pri_save_state_for_cal() { +#define RF_PRI_SAVE(field) rf_state.field = RF->field.value; +#include "rf_private_save.h" +} + + +static void rf_pri_restore_state_for_cal() { +#define RF_PRI_SAVE(field) RF->field.value = rf_state.field; +#include "rf_private_save.h" +} + +#include "macro.h" +#define mapper0(x) new_pucr1.x = 0; +#define mapper1(x) new_pucr1.x = 1; +#define P_CLR(...) APPLY(mapper0, __VA_ARGS__) +#define P_SET(...) APPLY(mapper1, __VA_ARGS__) + +static void rf_pri_manu_pu(uint32_t mode) { + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; + RF->rfctrl_hw_en.value = 0; + + __typeof__ (((rf_regs* )(RF_BASE))->pucr1) new_pucr1 = RF->pucr1; + + switch (mode) { + case E_RF_MODE_RCCAL: + P_CLR(pu_lna, pu_rmxgm, pu_rmx, pu_pkdet, + pu_pwrmx, pu_pa, pu_tmx, pu_tbb, + pu_rxbuf, pu_txbuf, pu_tosdac); + P_SET(pu_osmx, pu_pfd, pu_fbdv, pu_vco, + pu_rbb, pu_adc, adc_clk_en, pu_rosdac, + pu_dac, trsw_en); + break; + case E_RF_MODE_TXCAL: + P_CLR(pu_lna, pu_rmxgm, pu_rmx, pu_pkdet, pu_rosdac, pu_rxbuf); + P_SET(pu_txbuf, trsw_en, pu_tosdac, pu_osmx, + pu_pfd, pu_fbdv, pu_vco, pu_rbb, + pu_adc, adc_clk_en, pu_pwrmx, pu_pa, + pu_tmx, pu_tbb, pu_dac); + break; + + case E_RF_MODE_LO_ACAL: + case E_RF_MODE_LO_FCAL: + P_CLR(pu_lna, pu_rmxgm, pu_rmx, pu_tosdac, + pu_rbb, pu_adc, adc_clk_en, pu_pkdet, + pu_rosdac ,pu_pwrmx, pu_pa, pu_tmx, + pu_tbb,pu_dac,pu_rxbuf,pu_txbuf, + trsw_en); + P_SET(pu_osmx, pu_pfd, pu_fbdv, pu_vco); + break; + // in the leak code, this function treat + // 0...2 + default cases with the same code as 6...7 code + // however, in the binary, it uses the same logic + // as case 3 for 0...2 + default cases + // this branch should never touched unless mode == 3 + // so the 0...2 and default should never be used. + // that is why an error is added here. + default: + case E_RF_MODE_IDLE ... E_RF_MODE_RX: + printf("unexpected values for rf_pri_manu_pu\r\n"); + case E_RF_MODE_ROSCAL: + P_CLR(pu_lna, pu_pkdet, pu_pwrmx, pu_pa, + pu_tmx, pu_tbb, pu_dac, pu_txbuf, + pu_tosdac); + P_SET(pu_osmx, pu_pfd, pu_fbdv, pu_vco, + pu_rmxgm, pu_rmx, pu_rbb, pu_adc, + adc_clk_en, pu_rxbuf, trsw_en, pu_rosdac); + break; + } + RF->pucr1 = new_pucr1; +} + +static void rf_pri_config_mode(uint32_t mode) { + rf_pri_manu_pu(mode); +} + +#undef P_SET +#undef P_CLR +#undef mapper0 +#undef mapper1 + + +void rf_pri_fcal(void) { + RF->rfcal_status.fcal_status = 0x1; + + rf_pri_save_state_for_cal(); // TBI + rf_pri_config_mode(E_RF_MODE_LO_FCAL); // TBI + + RF->rfcal_ctrlen.fcal_en = 1; + + RF->vco1.lo_vco_freq_cw = 0x80; + RF->fbdv.lo_fbdv_sel_fb_clk = 0; + RF->vco3.fcal_div = fcal_div; + // frequency counter counts # RF periods within a counter + // clock cycle fcal_div is a divider for the counter clock. + + RF->sdm2.value = 0x1000000; + RF->sdm1.lo_sdm_bypass = 1; + + RF->sdm1.lo_sdm_rstb = 0; + RF->fbdv.lo_fbdv_rst = 1; + + BL602_Delay_US(10); + + RF->sdm1.lo_sdm_rstb = 1; + RF->fbdv.lo_fbdv_rst = 0; + + BL602_Delay_US(50); + + RF->vco2.lo_vco_vbias_cw = 2; + + BL602_Delay_US(50); + + uint16_t c0 = (uint16_t)channel_cnt_range[0]; + uint16_t c1 = (uint32_t)channel_cnt_range[1]; + uint16_t c2 = (uint16_t)channel_cnt_range[2]; + + uint16_t cw = 0x80; + while (1) { + for (int j = 6; j >= 0; j--) { + if (rf_pri_fcal_meas(cw) < c0) { + cw -= (1 << j); + } else { + if (rf_pri_fcal_meas(cw) > c1) { + cw += (1 << j); + } else break; + } + } + + if (cw >= 15) + break; + + printf("Unexpected cw %ld\r\n", cw); + + /// reset + RF->sdm1.lo_sdm_rstb = 0; + RF->fbdv.lo_fbdv_rst = 1; + BL602_Delay_US(0x32); + RF->sdm1.lo_sdm_rstb = 1; + RF->fbdv.lo_fbdv_rst = 0; + BL602_Delay_US(0x32); + } + + cw++; + channel_cnt_opt_table[0] = rf_pri_fcal_meas(cw); + + for (int i = 1; i < 40; i++) { + uint16_t cnt = rf_pri_fcal_meas(cw-i); + channel_cnt_opt_table[i] = cnt; + if (cnt > c2) break; + } + + for (int i = 0, j = 0; i < 21; i++) { + while (channel_cnt_opt_table[j] < channel_cnt_table[i]) j++; + channel_cw_table[i] = cw - (j - 1); /// hmmm what if j = 0?\ + /// or it can't because cw was + 1.. + if (j > 0) j--; + } + + rf_pri_restore_state_for_cal(); + + for (int i = 0; i < 21; i++) { + rf_calib_data->lo[i].fcal = channel_cw_table[i]; + printf("%ldth channel,lo_vco_freq_cw=%ld\r\n", i + 1, (uint32_t)(channel_cw_table[i])); + } + + RF->rfcal_status.fcal_status = 3; // 0b11 +} + +void rf_pri_start_rxdfe() { + PACK(RF->rfif_dfe_ctrl0, rfif_dfe_ctrl0) { + rfif_dfe_ctrl0.rx_dfe_en_4s_en = 0; + rfif_dfe_ctrl0.rx_dfe_en_4s = 0; + } + + PACK(RF->rfif_dfe_ctrl0, rfif_dfe_ctrl0) { + rfif_dfe_ctrl0.rfckg_rxclk_4s_on = 1; + rfif_dfe_ctrl0.rx_dfe_en_4s = 1; + rfif_dfe_ctrl0.rx_dfe_en_4s_en = 1; + } +} + +// TODO: verify me +void rf_pri_start_txdfe() { + PACK(RF->rfif_dfe_ctrl0, rfif_dfe_ctrl0) { + rfif_dfe_ctrl0.tx_dfe_en_4s_en = 0; + rfif_dfe_ctrl0.tx_dfe_en_4s = 0; + } + + PACK(RF->rfif_dfe_ctrl0, rfif_dfe_ctrl0) { + rfif_dfe_ctrl0.rfckg_txclk_4s_on = 1; + rfif_dfe_ctrl0.tx_test_sel = 2; + rfif_dfe_ctrl0.tx_dfe_en_4s = 1; + } + + RF->rfif_dfe_ctrl0.tx_dfe_en_4s_en = 1; +} + +static void rf_pri_config_channel(uint32_t channel_index) { + // sdm = sigma-delta modulator ? + PACK(RF->vco1, vco1) { + vco1.lo_vco_freq_cw = rf_calib_data->lo[channel_index].fcal; + vco1.lo_vco_idac_cw = rf_calib_data->lo[channel_index].acal; + } + RF->lodist.lo_osmx_cap = rf_calib_data->lo[channel_index].fcal >> 4; + RF->sdm2.lo_sdmin = channel_div_table[channel_index]; + RF->sdm1.lo_sdm_bypass = 0; + + while (1) { + RF->fbdv.lo_fbdv_rst = 1; + BL602_Delay_US(10); + + RF->fbdv.lo_fbdv_rst = 0; + BL602_Delay_US(50); + + RF->pfdcp.lo_pfd_rst_csd = 1; + BL602_Delay_US(10); + + RF->pfdcp.lo_pfd_rst_csd = 0; + BL602_Delay_US(50); + + __typeof__ (((rf_regs* )(RF_BASE))->lo) mylo = RF->lo; + + if (mylo.lo_slipped_dn || mylo.lo_slipped_up) { + printf("."); + } else { + printf("LO locked %ld %ld\r\n", channel_index, (uint32_t)rf_calib_data->lo[channel_index].fcal); + break; + } + } +} + +static int32_t rf_pri_pm_pwr_avg(uint32_t iq, uint32_t acc_len) { + PACK(RF->dfe_ctrl_6, dfe_ctrl_6) { + RF->dfe_ctrl_6.rx_pm_en = 0; + RF->dfe_ctrl_6.rx_pm_freqshift_en = 0; + } + //RF->dfe_ctrl_6.value &= 0xdfefffff; + RF->dfe_ctrl_7.rx_pm_acc_len = acc_len; + + RF->dfe_ctrl_6.rx_pm_en = 1; + + for (; !(RF->dfe_ctrl_6.rx_pm_done);); + + int32_t iqacc = 0; + if (iq) { + // iq = 1 => i + iqacc = RF->dfe_ctrl_8.rx_pm_iqacc_i; + } else { + // iq = 0 => q + iqacc = RF->dfe_ctrl_9.rx_pm_iqacc_q; + } + iqacc = (iqacc << 7) >> 7; + //RF->dfe_ctrl_6.value &= 0xdfefffff; + PACK(RF->dfe_ctrl_6, dfe_ctrl_6) { + RF->dfe_ctrl_6.rx_pm_en = 0; + RF->dfe_ctrl_6.rx_pm_freqshift_en = 0; + } + return iqacc; +} + +static void rf_pri_roscal_config(uint32_t iq,uint32_t rosdac) { + uint32_t tmpVal = 0; + if (iq) { + RF->rbb1.rosdac_i = rosdac; + } else { + RF->rbb1.rosdac_q = rosdac; + } +} + +static uint32_t rf_pri_roscal_iq(uint32_t iq, uint32_t sram_start_addr, uint32_t length) { + uint32_t rosdac = 0; + for (int i = 5; i >= 0; i--) { + uint32_t uvar7 = rosdac + (1 << i); + rf_pri_roscal_config(iq, uvar7); + if (rf_pri_pm_pwr_avg(iq, 1024) < 1) // leak code says <= 0? + rosdac = uvar7; + } + + uint8_t seq_pattern = 0; + + for (int i = 0; i < 63; i++) { + rf_pri_roscal_config(iq, rosdac); + int32_t pwr = rf_pri_pm_pwr_avg(iq, 1024); + if (pwr < 1) { + seq_pattern = (seq_pattern << 1) & 0xf; + rosdac++; + } else { + seq_pattern = ((seq_pattern << 1) + 1) & 0xf; + rosdac--; + } + if ((seq_pattern == 0b1010) || (seq_pattern == 0b0101)) + break; + } + + return rosdac; +} + +void rf_pri_roscal() { + if (RF->rfcal_stateen.roscal_sten == 0) { + RF->rfcal_status.ros_status = 0; + return ; + } + + RF->rfcal_status.ros_status = 1; + // td + rf_pri_save_state_for_cal(); + rf_pri_config_mode(E_RF_MODE_ROSCAL); + RF->rfcal_ctrlen.roscal_en = 1; + + rf_pri_config_channel(3); // in the leak source the value here is 9. + + RF->trx_gain1.gc_rbb2 = 6; + RF->trx_gain1.gc_rbb1 = 3; + + uint32_t rosdac = rf_pri_roscal_iq(1, 0 /* unused */, 0 /* unused */); + + rf_calib_data->rxcal[3].rosdac_i = rosdac; + + RF->rosdac_ctrl_hw2.rosdac_i_gc3 = rosdac; + printf("rosdac_i_gc3=%ld\r\n", rosdac); + + rf_calib_data->rxcal[2].rosdac_i = rosdac; + + RF->rosdac_ctrl_hw2.rosdac_i_gc2 = rosdac; + printf("rosdac_i_gc2=%ld\r\n", rosdac); + + rf_calib_data->rxcal[1].rosdac_i = rosdac; + + RF->rosdac_ctrl_hw1.rosdac_i_gc1 = rosdac; + printf("rosdac_i_gc1=%ld\r\n", rosdac); + + rf_calib_data->rxcal[0].rosdac_i = rosdac; + + RF->rosdac_ctrl_hw1.rosdac_i_gc0 = rosdac; + printf("rosdac_i_gc0=%ld\r\n", rosdac); + + rosdac = rf_pri_roscal_iq(0, 0 /* unused */, 0 /* unused */); + + rf_calib_data->rxcal[3].rosdac_q = rosdac; + + RF->rosdac_ctrl_hw2.rosdac_q_gc3 = rosdac; + printf("rosdac_q_gc3=%ld\r\n", rosdac); + + rf_calib_data->rxcal[2].rosdac_q = rosdac; + + RF->rosdac_ctrl_hw2.rosdac_q_gc2 = rosdac; + printf("rosdac_q_gc2=%ld\r\n", rosdac); + + rf_calib_data->rxcal[1].rosdac_q = rosdac; + + RF->rosdac_ctrl_hw1.rosdac_q_gc1 = rosdac; + printf("rosdac_q_gc1=%ld\r\n", rosdac); + + rf_calib_data->rxcal[0].rosdac_q = rosdac; + + RF->rosdac_ctrl_hw1.rosdac_q_gc0 = rosdac; + printf("rosdac_q_gc0=%ld\r\n", rosdac); + + rf_pri_restore_state_for_cal(); + + RF->rfcal_status.ros_status = 3; +} + +void rf_pri_full_cal(void) { + // dfe + rf_pri_start_rxdfe(); + rf_pri_start_txdfe(); + rf_pri_fcal(); + rf_pri_lo_acal(); + rf_pri_roscal(); + rf_pri_rccal(); + rf_pri_txcal(); + + PACK(RF->rfctrl_hw_en, rfctrl_hw_en) { + rfctrl_hw_en.rx_gain_ctrl_hw = 1; + rfctrl_hw_en.tx_gain_ctrl_hw = 1; + } + + PACK(RF->rfif_dfe_ctrl0, rfif_dfe_ctrl0) { + rfif_dfe_ctrl0.rfckg_rxclk_4s_on = 0; + rfif_dfe_ctrl0.rx_dfe_en_4s_en = 0; + rfif_dfe_ctrl0.rx_dfe_en_4s = 0; + } + + PACK(RF->rfif_dfe_ctrl0, rfif_dfe_ctrl0) { + rfif_dfe_ctrl0.rfckg_txclk_4s_on = 0; + rfif_dfe_ctrl0.tx_dfe_en_4s_en = 0; + rfif_dfe_ctrl0.tx_dfe_en_4s = 0; + rfif_dfe_ctrl0.tx_test_sel = 0; + } +} +static int32_t rx_notch_para[14][2] = { + {0,0}, {0,0}, {0,0}, {0,0}, + {1,8 MHz}, + {1,3 MHz}, + {1,-2 MHz}, + {1,-7 MHz}, + {0,0}, {0,0}, {0,0}, {0,0}, + {1,8 MHz}, + {1,-4 MHz}, +}; + +void rf_pri_get_notch_param(uint32_t chanfreq_MHz, uint8_t * ncf_on, int32_t * ncf_freq_Hz) { + uint32_t channel_id; + channel_id = 13; + if (chanfreq_MHz < 2473) { + channel_id = (chanfreq_MHz - 2412) / 5; + } + + *ncf_on = (uint8_t)rx_notch_para[channel_id][0]; + *ncf_freq_Hz = rx_notch_para[channel_id][1]; +} + +uint32_t rf_pri_get_vco_freq_cw(uint32_t chanfreq_MHz) { + int32_t a = (int32_t)((chanfreq_MHz-2404)/4 + 0.5); + a = a < 0 ? 0 : a; + if (a > NUM_CHANNELS - 1) + a = NUM_CHANNELS - 1; + return rf_calib_data->lo[a].fcal; +} + +uint32_t rf_pri_get_vco_idac_cw(uint32_t chanfreq_MHz) { + int32_t a = (int32_t)((chanfreq_MHz-2404)/4 + 0.5); + a = a < 0 ? 0 : a; + if (a > NUM_CHANNELS - 1) + a = NUM_CHANNELS - 1; + return rf_calib_data->lo[a].acal; +} + +void rf_pri_lo_acal(void) { + RF->rfcal_status.acal_status = 0x1; + rf_pri_save_state_for_cal(); + rf_pri_config_mode(E_RF_MODE_LO_ACAL); + + for (int i = 0; i < 21; i++) { + RF->rfcal_ctrlen.acal_en = 1; + RF->vco2.acal_vref_cw = 4; + RF->vco1.lo_vco_idac_cw = 0x10; + RF->vco1.lo_vco_freq_cw = rf_calib_data->lo[i].fcal; + RF->sdm2.lo_sdmin = channel_div_table[i]; + BL602_Delay_US(1); + uint32_t cw = 0x10; + for (int j = 3; j >= 0; j--) { + RF->vco1.lo_vco_idac_cw = cw; + BL602_Delay_US(1); + if (RF->vco2.acal_vco_ud) { + cw -= (1 << j); + } else { + cw += (1 << j); + } + } + RF->vco1.lo_vco_idac_cw = cw; + BL602_Delay_US(1); + if (!RF->vco2.acal_vco_ud) { + if (cw != (1<<5) - 1) { + cw++; + } + } + rf_calib_data->lo[i].acal = cw; + } + rf_pri_restore_state_for_cal(); + RF->rfcal_status.acal_status = 0x3; +} + + +static void rf_pri_rccal_config(uint32_t iq, uint32_t rbb_fc) { + PACK(RF->rbb2, rbb2) + if (iq) { + // i + rbb2.rbb_cap1_fc_i = rbb_fc; + rbb2.rbb_cap2_fc_i = rbb_fc; + } else { + rbb2.rbb_cap1_fc_q = rbb_fc; + rbb2.rbb_cap2_fc_q = rbb_fc; + } +} + + +static void rf_pri_singen_config(uint32_t fcw, uint32_t start_addr_i, uint32_t start_addr_q) { + RF->singen_ctrl0.singen_inc_step0 = fcw; + RF->singen_ctrl2.singen_start_addr0_i = start_addr_i; // 0; + RF->singen_ctrl3.singen_start_addr0_q = start_addr_q; // 0x300; +} + +static void rf_pri_singen_start(void) { + RF->singen_ctrl0.singen_en = 0; + + RF->singen_ctrl0.singen_en = 1; +} + +static void rf_pri_singen_amplitude(uint32_t gain_i, uint32_t gain_q) { + RF->singen_ctrl2.singen_gain_i = gain_i; + RF->singen_ctrl3.singen_gain_q = gain_q; +} + +static uint32_t rf_pri_pm_pwr() { + PACK(RF->dfe_ctrl_6, dfe) { + dfe.rx_pm_freqshift_en = 0; + dfe.rx_pm_en = 0; + } + + PACK(RF->dfe_ctrl_6, dfe) { + dfe.rx_pm_freqshift_en = 1; + dfe.rx_pm_en = 1; + } + + for (; ! RF->dfe_ctrl_6.rx_pm_done; ); + + int32_t pm_iacc = RF->dfe_ctrl_8.value; + pm_iacc = (pm_iacc << 7) >> (7 + 9); + + int32_t pm_qacc = RF->dfe_ctrl_9.value; + pm_qacc = (pm_qacc << 7) >> (7 + 9); + + + PACK(RF->dfe_ctrl_6, dfe) { + dfe.rx_pm_freqshift_en = 0; + dfe.rx_pm_en = 0; + } + + return pm_iacc * pm_iacc + pm_qacc * pm_qacc; +} + + +static uint32_t rf_pri_rccal_iq(uint32_t iq) { + if (iq) { + RF->dfe_ctrl_3.rx_adc_4s_q_en = 0; + RF->dfe_ctrl_3.rx_adc_4s_i_en = 1; + } else { + RF->dfe_ctrl_3.rx_adc_4s_i_en = 0; + RF->dfe_ctrl_3.rx_adc_4s_q_en = 1; + } + + PACK(RF->trx_gain1, trx_gain1) { + trx_gain1.gc_rbb1 = 1; + trx_gain1.gc_rbb2 = 3; + } + + int k1 = 3, k2 = 181; + rf_pri_singen_config(k1, 0, 0x300); + + rf_pri_singen_amplitude(0x3ff, 0x3ff); + + rf_pri_singen_start(); + rf_pri_start_txdfe(); + RF->dfe_ctrl_6.rx_pm_freqshift_cw = k1 << 10; + rf_pri_pm_pwr_avg(iq, 0x400); + + double rccal_power_scale = 0.9 * 0.9; + uint32_t rccal_ref = (uint32_t)(rccal_power_scale * rf_pri_pm_pwr()); + + + PACK(RF->trx_gain1, trx_gain1) { + trx_gain1.gc_rbb1 = 2; + trx_gain1.gc_rbb2 = 6; + } + + rf_pri_singen_config(k2, 0x0, 0x300); + rf_pri_singen_start(); + rf_pri_start_txdfe(); + + RF->dfe_ctrl_6.rx_pm_freqshift_cw = k2 << 10; + + uint32_t rbb_fc = 0; + for (int i = 5; i >= 0; i--) { + rf_pri_rccal_config(iq, rbb_fc + (1 << i)); + uint32_t rccal_val = rf_pri_pm_pwr(); + if (rccal_val > rccal_ref) { + rbb_fc += (1 << i); + } + } + + uint8_t seq_pattern = 0; + for (int i = 0; i < 63; i++) { + rf_pri_rccal_config(iq, rbb_fc); + uint32_t rccal_val = rf_pri_pm_pwr(); + if (rccal_ref < rccal_val) { + seq_pattern = ((seq_pattern << 1) | 1) & 0xf; + rbb_fc++; + } else { + seq_pattern = (seq_pattern << 1) & 0xf; + rbb_fc--; + } + if ((seq_pattern == 0b0101) || (seq_pattern == 0b1010)) + return 3; + } + + return 2; +} + +// resistor-capacitor? +void rf_pri_rccal(void) { + if (RF->rfcal_stateen.rccal_sten) { + RF->rfcal_status.rccal_status = 0; + } else { + RF->rfcal_status.rccal_status = 1; + rf_pri_save_state_for_cal(); + rf_pri_config_mode(E_RF_MODE_RCCAL); + RF->rbb3.rbb_bw = 2; + RF->adda1.dac_rccalsel = 1; + RF->rfcal_ctrlen.rccal_en = 1; + uint32_t i = rf_pri_rccal_iq(1); + uint32_t q = rf_pri_rccal_iq(0); + + __typeof__ (RF->rbb2) data = RF->rbb2; + + rf_calib_data->cal.rbb_cap1_fc_i = data.rbb_cap1_fc_i; + rf_calib_data->cal.rbb_cap1_fc_q = data.rbb_cap1_fc_q; + rf_calib_data->cal.rbb_cap2_fc_i = data.rbb_cap2_fc_i; + rf_calib_data->cal.rbb_cap2_fc_q = data.rbb_cap2_fc_q; + + printf("rbb_cap1_fc_i=%ld,rbb_cap2_fc_i=%ld,rbb_cap1_fc_q=%ld,rbb_cap2_fc_q=%ld\r\n", + (uint32_t)(rf_calib_data->cal.rbb_cap1_fc_i), + (uint32_t)(rf_calib_data->cal.rbb_cap2_fc_i), + (uint32_t)(rf_calib_data->cal.rbb_cap1_fc_q), + (uint32_t)(rf_calib_data->cal.rbb_cap2_fc_q)); + int32_t maxcw = MAX( MAX(rf_calib_data->cal.rbb_cap1_fc_i, rf_calib_data->cal.rbb_cap1_fc_q), + MAX(rf_calib_data->cal.rbb_cap2_fc_i, rf_calib_data->cal.rbb_cap2_fc_q)); + //int32_t tgt_offset_cw = 24; + //int32_t offset_cw = (max_cw + tgt_offset_cw) <= 63 ? tgt_offset_cw : 63 - max_cw; + int32_t offset_cw = 24; + if (maxcw > 39) + offset_cw = 63 - maxcw; + rf_calib_data->cal.rbb_cap1_fc_i += offset_cw; + rf_calib_data->cal.rbb_cap1_fc_q += offset_cw; + rf_calib_data->cal.rbb_cap2_fc_i += offset_cw; + rf_calib_data->cal.rbb_cap2_fc_q += offset_cw; + + rf_pri_rccal_config(1, rf_calib_data->cal.rbb_cap1_fc_i); + rf_pri_rccal_config(0, rf_calib_data->cal.rbb_cap1_fc_q); + + printf("new rbb_cap1_fc_i=%ld,rbb_cap2_fc_i=%ld,rbb_cap1_fc_q=%ld,rbb_cap2_fc_q=%ld\r\n", + (uint32_t)(rf_calib_data->cal.rbb_cap1_fc_i), + (uint32_t)(rf_calib_data->cal.rbb_cap2_fc_i), + (uint32_t)(rf_calib_data->cal.rbb_cap1_fc_q), + (uint32_t)(rf_calib_data->cal.rbb_cap2_fc_q)); + + rf_pri_restore_state_for_cal(); + + if ((i == 2) || (q == 2)) { + RF->rfcal_status.rccal_status = 2; + } else { + RF->rfcal_status.rccal_status = 3; + } + } +} + +static uint32_t txcal_para[E_RF_TXCAL_GAIN_CNT][4]; +static uint32_t txcal_para_a0[E_RF_TXCAL_GAIN_CNT][4] = { + { 0, 2, 6, 256}, + { 0, 2, 1, 256}, + { 0, 2, 0, 304}, + { 0, 4, 0, 240}, + { 0, 4, 0, 304}, + { 0, 4, 0, 352}, + { 0, 4, 0, 416}, + { 0, 4, 0, 416} +}; + +static uint32_t txcal_para_a1[E_RF_TXCAL_GAIN_CNT][4] = { + { 0, 2, 14, 256}, + { 0, 2, 5, 256}, + { 0, 2, 1, 256}, + { 0, 4, 2, 272}, + { 0, 4, 0, 224}, + { 0, 4, 0, 272}, + { 0, 4, 0, 288}, + { 0, 4, 0, 304} +}; + +static void rf_pri_config_txgain(uint32_t gc_tbb_boost, uint32_t gc_tmx, uint32_t gc_tbb) { + PACK(RF->trx_gain1, value) { + value.gc_tbb_boost = gc_tbb_boost; + value.gc_tmx = gc_tmx; + value.gc_tbb = gc_tbb; + } +} + +static int32_t tx_pwr_os = 0; // channel offset +static int32_t tx_pwr_os_temperature = 0; // temperature offset + +static int32_t tx_pwr_table[E_RF_TXPWR_TBL_CNT][7]; +static int32_t tx_pwr_table_origin[E_RF_TXPWR_TBL_CNT][7]; +static int32_t tx_pwr_table_a0[E_RF_TXPWR_TBL_CNT][7] = { + // gain_ctrl_gc_tbb, gain_ctrl_gc_tmx, gain_ctrl_dac_bias_sel, gain_ctrl_gc_tbb_boost + {0, 1, 7, 0x14, 32, 4, 233}, + {0, 1, 7, 0x14, 32, 0, 223}, + {0, 1, 7, 0xe, 32, 4, 212}, + {0, 1, 7, 0xe, 32, 0, 202}, + {0, 1, 7, 0xa, 32, 4 + 1, 188 + 3}, + {0, 1, 7, 0xa, 32, 0 + 1, 178 + 3}, + {0, 1, 7, 8, 32, 4 - 1, 173 - 3}, + {0, 1, 7, 8, 32, 0 - 1, 163 - 3}, + {0, 1, 7, 6, 32, 4 - 1, 153 - 3}, + {0, 1, 7, 6, 32, 0 - 1, 143 - 3}, + {0, 1, 6, 5, 32, 4 + 1, 129 + 3}, + {0, 1, 6, 5, 32, 0 + 1, 119 + 3}, + {0, 1, 6, 4, 32, 4 - 1, 114 - 3}, + {0, 1, 6, 4, 32, 0 - 1, 104 - 3}, + {0, 1, 5, 4, 32, 0, 91}, + {0, 1, 5, 4, 32, -4, 81}, +}; + +static int32_t tx_pwr_table_a1[E_RF_TXPWR_TBL_CNT][7] = { + // gain_ctrl_gc_tbb, gain_ctrl_gc_tmx, gain_ctrl_dac_bias_sel, gain_ctrl_gc_tbb_boost + { 0, 1, 7, 27, 32, -4, 230}, + { 0, 1, 7, 27, 32, -8, 220}, + { 0, 1, 7, 20, 32, -4, 210}, + { 0, 1, 7, 20, 32, -8, 200}, + { 0, 1, 7, 15, 32, -4, 190}, + { 0, 1, 7, 15, 32, -8, 180}, + { 0, 1, 7, 11, 32, -4, 170}, + { 0, 1, 7, 11, 32, -8, 160}, + { 0, 1, 6, 10, 32, -4, 150}, + { 0, 1, 6, 10, 32, -8, 140}, + { 0, 1, 6, 8, 32, -5, 130}, + { 0, 1, 6, 8, 32, -9, 120}, + { 0, 1, 5, 7, 32, -4, 110}, + { 0, 1, 5, 7, 32, -8, 100}, + { 0, 1, 4, 7, 32, -5, 90}, + { 0, 1, 4, 7, 32, -9, 80} +}; + +void rf_pri_query_txgain_table(uint32_t index, uint32_t * rfg_index, uint32_t * dg) { + if (index > 15) index = 15; + *rfg_index = 7 - (index >> 1); + *dg = tx_pwr_table[index][5]; +} + +static int32_t tx_pwr_ch_os[NUM_WIFI_CHANNELS]; // TBD +static int32_t tx_pwr_ch_os_a0[NUM_WIFI_CHANNELS] = { + -16, -13, -10, -8, -5, -2, 0, 2, 5, 7, 9, 11, 14, 18 +}; +static int32_t tx_pwr_ch_os_a1[NUM_WIFI_CHANNELS] = { + // not assigned in the binary, put something here... + // TODO: get some values.. + 13, //2412MHz + 15, //2417MHz + 16, //2422MHz + 18, //2427MHz + 21, //2432MHz + 23, //2437MHz + 0, //2442MHz + 0, //2447MHz + 5, //2452MHz + 7, //2457MHz + 9, //2462MHz + 11, //2467MHz + 14, //2472MHz + 18 //2484MHz +}; + +void rf_pri_update_power_offset(int32_t * power_offset) { + for (int i = 0; i < NUM_WIFI_CHANNELS; i++) { + tx_pwr_ch_os[i] = power_offset[i]; + tx_pwr_ch_os_a1[i] = power_offset[i]; + } +} + +static void rf_pri_set_gain_table_regs() { + // Little-endian? looks okay.. + typedef struct { + uint32_t gain_ctrl_gc_tbb : 5; + uint32_t pad0 : 3; + uint32_t gain_ctrl_gc_tmx : 3; + uint32_t pad1 : 1; + uint32_t gain_ctrl_dac_bias_sel : 2; + uint32_t gain_ctrl_gc_tbb_boost : 2; + } __attribute__((packed)) tbb_gain_t; + union { + tbb_gain_t vals[8]; + uint32_t pack[4]; + } tbb_gain = {.pack = {0}}; + + for (int i = 0, idx = 14; i < 8; i++, idx-=2) { + tbb_gain.vals[i].gain_ctrl_gc_tbb = tx_pwr_table[idx][3]; + tbb_gain.vals[i].gain_ctrl_gc_tmx = tx_pwr_table[idx][2]; + tbb_gain.vals[i].gain_ctrl_dac_bias_sel = tx_pwr_table[idx][1]; + tbb_gain.vals[i].gain_ctrl_gc_tbb_boost = tx_pwr_table[idx][0]; + } + + RF->tbb_gain_index1.value = tbb_gain.pack[0]; + RF->tbb_gain_index2.value = tbb_gain.pack[1]; + RF->tbb_gain_index3.value = tbb_gain.pack[2]; + RF->tbb_gain_index4.value = tbb_gain.pack[3]; +} + +void rf_pri_update_tx_power_offset(uint8_t channel, int8_t * power_offset) { + uint8_t po = power_offset[channel]; + memcpy(tx_pwr_table, tx_pwr_table_origin, sizeof(tx_pwr_table_origin)); + for (int i = 0; i < E_RF_TXPWR_TBL_CNT; i++) { + tx_pwr_table[i][5] = tx_pwr_table[i][5] + po % 4; + tx_pwr_table[i][6] = tx_pwr_table[i][6] + ((int)po / 4) * -10; + } + rf_pri_set_gain_table_regs(); +} + +static uint32_t Tchannels[6] = { + 2412, 2417, 2427, 2442, + 2457, 2472 +}; + +static int32_t Tchannel_os[6] = {2, 3, 3, 4, 6, 8}; +static int32_t Tchannel_os_low[6] = {0, 0, 1, 2, 4, 7}; +static int32_t temps[13] = {-65, -45, -25, -5, 15, 51, + 75, 95, 120, 145, 170, 195, 220}; + +static regs_to_opti opti_regs_data_a0 = { + .vbcore = 10, + .iet = 3, + .vbcore_11n = 10, + .iet_11n = 3, + .vbcore_11g = 10, + .iet_11g = 3, + .vbcore_11b = 10, + .iet_11b = 3, + .lo_fbdv_halfstep_en = 0, + .lo_fbdv_halfstep_en_tx = 0, + .lo_fbdv_halfstep_en_rx = 0, + .clkpll_reset_postdiv = 0, + .clkpll_dither_sel = 0, +}; + +static regs_to_opti opti_regs_data_a1 = { + .vbcore = 0xc, + .iet = 5, + .vbcore_11n = 0xc, + .iet_11n = 5, + .vbcore_11g = 0xc, + .iet_11g = 5, + .vbcore_11b = 0xc, + .iet_11b = 5, + .lo_fbdv_halfstep_en = 1, + .lo_fbdv_halfstep_en_tx = 1, + .lo_fbdv_halfstep_en_rx = 1, + .clkpll_reset_postdiv = 1, + .clkpll_dither_sel = 2, +}; + +regs_to_opti *opti_regs = &opti_regs_data_a1; + +static uint16_t tmxcss[3] = {5,5,5}; + +static int32_t index_os_pre; +static int32_t index_os_pre_mdb; +static int32_t dvga_os_pre; +static int32_t up_dn; + +static void rf_pri_singen_pwrmx_dc(uint32_t amp, uint32_t num_data, int32_t adc_mean_max, int32_t adc_mean_min){ + uint32_t step; + int32_t adc_mean_i = 0; + step = amp >> 1; + while(1) { + rf_pri_singen_amplitude(amp, amp); + rf_pri_singen_start(); + rf_pri_start_txdfe(); + + BL602_Delay_US(10); + adc_mean_i = rf_pri_pm_pwr_avg(1, num_data); + adc_mean_i = adc_mean_i>>10; + printf("amp=%ld,step=%ld,adc_mean_i=%ld\r\n", amp, step, adc_mean_i); + + if(adc_mean_i > adc_mean_max) + amp -= step; + else if (adc_mean_i < adc_mean_min) + amp += step; + else + break; + if(step > 0) + step = step >> 1; + else + break; + } +} + +// TODO: verify me +static void rf_pri_txcal_config(uint32_t param_ind, int32_t val) { + switch (param_ind) { + case E_RF_GAIN: { + PACK(RF->dfe_ctrl_0, dfe) { + dfe.tx_iqc_gain = val; + dfe.tx_iqc_gain_en = 1; + } + break; + } + case E_RF_PHASE: { + val = val >= 0 ? val : (val+0x400); + PACK(RF->dfe_ctrl_0, dfe) { + dfe.tx_iqc_phase = val; + dfe.tx_iqc_phase_en = 1; + } + break; + } + case E_RF_BRANCH_I: { + RF->tbb.tbb_tosdac_i = val; + break; + } + case E_RF_BRANCH_Q: { + RF->tbb.tbb_tosdac_i = val; + break; + } + default: + break; + } +} + +// kinda like Gradient descent to find minimum point? +// todo: verify me +static int32_t rf_pri_txcal_search_core(uint32_t param_ind, uint32_t center, uint32_t delta, uint32_t meas_freq) { + rf_pri_txcal_config(param_ind, center); + BL602_Delay_US(10); + + RF->dfe_ctrl_6.rx_pm_freqshift_cw = meas_freq << 10; + + uint32_t y_center = rf_pri_pm_pwr(); + + int32_t x_center = center; + int32_t x_delta = delta; + + for (int32_t x_left, x_right, y_left, y_right; x_delta; x_delta >>= 1) { + x_left = x_center - x_delta; + x_right = x_center + x_delta; + switch (param_ind) { + case E_RF_BRANCH_I ... E_RF_BRANCH_Q: + x_left = x_left < 0 ? 0 : x_left; + x_right = x_right > 63 ? 63 : x_right; + break; + case E_RF_GAIN: + x_left = x_left < 0 ? 0 : x_left; + x_right = x_right > 2047 ? 2047 : x_right; + break; + case E_RF_PHASE: + x_left = x_left < -512 ? -512 : x_left; + x_right = x_right > 511 ? 511 : x_right; + break; + } + + // left + rf_pri_txcal_config(param_ind, x_left); + BL602_Delay_US(10); + y_left = rf_pri_pm_pwr(); + + if (y_center <= y_left) { + // right + + rf_pri_txcal_config(param_ind, x_right); + BL602_Delay_US(10); + y_right = rf_pri_pm_pwr(); + + if (y_center > y_right) { + x_center = x_right; + y_center = y_right; + } + } else { + x_center = x_left; + y_center = y_left; + } + } + + return x_center; +} + +static void rf_pri_txcal_config_hw() { + typedef struct { + uint32_t tbb_tosdac_i_gc0 : 6; // @ 5 -- 0 # 0xffffffc0 + uint32_t pad0 : 2; + uint32_t tbb_tosdac_q_gc0 : 6; // @ 13 -- 8 # 0xffffc0ff + uint32_t pad1 : 2; + } __attribute__((packed)) tosdac_t; + union { + tosdac_t vals[8]; + uint32_t pack[4]; + } tosdac = {.pack = {0}}; + for (int i = 0; i < 8; i++) { + tosdac.vals[i].tbb_tosdac_i_gc0 = rf_calib_data->txcal[i].tosdac_i; + tosdac.vals[i].tbb_tosdac_q_gc0 = rf_calib_data->txcal[i].tosdac_q; + } + RF->tosdac_ctrl_hw1.value = tosdac.pack[0]; + RF->tosdac_ctrl_hw2.value = tosdac.pack[1]; + RF->tosdac_ctrl_hw3.value = tosdac.pack[2]; + RF->tosdac_ctrl_hw4.value = tosdac.pack[3]; + + __typeof__ (RF->tx_iq_gain_hw0) iq_gain[8]; + + for (int i = 0; i < 8; i++) { + iq_gain[i].tx_iq_gain_comp_gc0 = rf_calib_data->txcal[i].tx_iq_gain_comp; + iq_gain[i].tx_iq_phase_comp_gc0 = rf_calib_data->txcal[i].tx_iq_phase_comp; + } + + RF->tx_iq_gain_hw0.value = iq_gain[0].value; + RF->tx_iq_gain_hw1.value = iq_gain[1].value; + RF->tx_iq_gain_hw2.value = iq_gain[2].value; + RF->tx_iq_gain_hw3.value = iq_gain[3].value; + RF->tx_iq_gain_hw4.value = iq_gain[4].value; + RF->tx_iq_gain_hw5.value = iq_gain[5].value; + RF->tx_iq_gain_hw6.value = iq_gain[6].value; + RF->tx_iq_gain_hw7.value = iq_gain[7].value; +} + +void rf_pri_txcal(void) { + // + PACK(RF->rfcal_status, rfcal_status) { + rfcal_status.lo_leakcal_status = 1; + rfcal_status.tiqcal_status_resv = 1; + } + // + rf_pri_save_state_for_cal(); + rf_pri_config_mode(E_RF_MODE_TXCAL); + rf_pri_config_channel(E_RF_CHANNEL_2424M); // E_RF_CHANNEL_2440M in the leak code + + // + PACK(RF->rfcal_ctrlen, rfcal_ctrlen) { + rfcal_ctrlen.tiqcal_en = 1; + rfcal_ctrlen.lo_leakcal_en = 1; + } + // + RF->rbb3.pwr_det_en = 1; + + RF->pa1.pa_pwrmx_dac_pn_switch = 1; + + RF->tmx.tmx_cs = tmxcss[0]; // leak code use 3 + + uint32_t k1 = 61; + rf_pri_singen_config(k1, 0x0, 0x300); + + for (int i = 0; i < 8; i++) { + // + PACK(RF->pa1, pa1) { + pa1.pa_att_gc = txcal_para[i][0]; + pa1.pa_pwrmx_osdac = txcal_para[i][2]; + } + // + RF->ten_ac.atest_gain_r5 = txcal_para[i][1]; + + // + rf_pri_config_txgain(tx_pwr_table[i<<1][0], 7, tx_pwr_table[i<<1][3]); + // + + BL602_Delay_US(10); + + int32_t adc_mean_min=192; + int32_t adc_mean_max=320; + uint32_t num_data=1024; + rf_pri_singen_pwrmx_dc(txcal_para[i][3],num_data,adc_mean_max,adc_mean_min); + + rf_pri_pm_pwr_avg(1, 0x1000); + + uint32_t tos_i = rf_pri_txcal_search_core(E_RF_BRANCH_I, 32, 16, k1); + rf_pri_txcal_config(E_RF_BRANCH_I, tos_i); + + uint32_t tos_q = rf_pri_txcal_search_core(E_RF_BRANCH_Q, 32, 16, k1); + rf_pri_txcal_config(E_RF_BRANCH_Q, tos_q); + + tos_i = rf_pri_txcal_search_core(E_RF_BRANCH_I, tos_i, 2, k1); + rf_pri_txcal_config(E_RF_BRANCH_I, tos_i); + + uint32_t gain = rf_pri_txcal_search_core(E_RF_GAIN, 0x400, 0x80, 2 * k1); + rf_pri_txcal_config(E_RF_GAIN, gain); + + uint32_t phase = rf_pri_txcal_search_core(E_RF_PHASE, 0, 0x40, 2 * k1); + rf_pri_txcal_config(E_RF_PHASE, phase); + + gain = rf_pri_txcal_search_core(E_RF_GAIN, gain, 0x40, 2 * k1); + rf_pri_txcal_config(E_RF_GAIN, gain); + + phase = rf_pri_txcal_search_core(E_RF_PHASE, 0, 0x20, 2 * k1); + rf_pri_txcal_config(E_RF_PHASE, phase); + + rf_calib_data->txcal[E_RF_TXCAL_GAIN_CNT - 1 - i].tosdac_i = tos_i; + rf_calib_data->txcal[E_RF_TXCAL_GAIN_CNT - 1 - i].tosdac_q = tos_q; + rf_calib_data->txcal[E_RF_TXCAL_GAIN_CNT - 1 - i].tx_iq_gain_comp = gain; + rf_calib_data->txcal[E_RF_TXCAL_GAIN_CNT - 1 - i].tx_iq_phase_comp = phase; + + printf("tosdac_i=%ld,tosdac_q=%ld,tx_iq_gain_comp=%ld,tx_iq_phase_comp=%ld\r\n", + tos_i, tos_q, gain, phase); + } + + rf_pri_txcal_config_hw(); + PACK(RF->rfcal_ctrlen, rfcal_ctrlen) { + rfcal_ctrlen.lo_leakcal_en = 0; + rfcal_ctrlen.tiqcal_en = 0; + } + rf_pri_restore_state_for_cal(); + + PACK(RF->rfcal_status, rfcal_status) { + rfcal_status.lo_leakcal_status = 0x3; + rfcal_status.tiqcal_status_resv = 0x3; + } + + PACK(RF->tbb, tbb) { + tbb.tbb_tosdac_i = rf_calib_data->txcal[3].tosdac_i; + tbb.tbb_tosdac_q = rf_calib_data->txcal[3].tosdac_q; + } + + PACK(RF->dfe_ctrl_0, dfe_ctrl_0) { + dfe_ctrl_0.tx_iqc_gain = rf_calib_data->txcal[3].tx_iq_gain_comp; + dfe_ctrl_0.tx_iqc_phase = rf_calib_data->txcal[3].tx_iq_phase_comp; + } +} + + +void rf_pri_update_param(uint32_t chanfreq_MHz) { + uint32_t low_chan = 7; + int32_t i4 = 8; + + index_os_pre = 0; + index_os_pre_mdb = 0; + dvga_os_pre = 0; + up_dn = 0; + + for (int i = 1; i < 6; i++) { + if (chanfreq_MHz < Tchannels[i]) { + low_chan = i - 1; + break; + } + } + + if (low_chan != 7) { + uint32_t low_chanfreq_Mhz = Tchannels[low_chan]; + int freq_diff = chanfreq_MHz - low_chanfreq_Mhz; + int high_ch = low_chan + 1; + i4 = (uint32_t)((Tchannel_os[high_ch] - Tchannel_os[low_chan]) + * freq_diff) / (Tchannels[high_ch] - low_chanfreq_Mhz) + + Tchannel_os[low_chan]; + + low_chan = (uint32_t)((Tchannel_os_low[high_ch] - Tchannel_os_low[low_chan]) * freq_diff) / + (Tchannels[high_ch] - low_chanfreq_Mhz) + Tchannel_os_low[low_chan]; + } + + int d = 0; + for (int i = 10, j = 4; i != -10; i -=5, j -= 1) { + int i2 = (temps[j] + d) - (20 - low_chan); + d = 0; + if (i2 > i) { + d = i2 - i; + i2 = i; + } + temps[j - 1] = i2; + } + + d = 0; + for (int i = 56, j = 5; i != 91; i += 5, j++) { + int i8 = (temps[j] - d) + (20 - i4); + if (i8 > 95) { + i8 = i8 + (5 - i4 / 4); + } + d = 0; + if (i8 < i) { + d = i - i8; + i8 = i; + } + temps[j + 1] = i8; + } + + temps[4] = 15; + temps[5] = 51; + + // the leak code use tmx_csl/tmx_csh from rf_calib_data + if (chanfreq_MHz < 2438) { + RF->tmx.tmx_cs = tmxcss[1]; + } else { + RF->tmx.tmx_cs = tmxcss[2]; + } + + switch(chanfreq_MHz){ + case 2412: + tx_pwr_os = tx_pwr_ch_os[0]; + break; + case 2417: + tx_pwr_os = tx_pwr_ch_os[1]; + break; + case 2422: + tx_pwr_os = tx_pwr_ch_os[2]; + break; + case 2427: + tx_pwr_os = tx_pwr_ch_os[3]; + break; + case 2432: + tx_pwr_os = tx_pwr_ch_os[4]; + break; + case 2437: + tx_pwr_os = tx_pwr_ch_os[5]; + break; + case 2442: + tx_pwr_os = tx_pwr_ch_os[6]; + break; + case 2447: + tx_pwr_os = tx_pwr_ch_os[7]; + break; + case 2452: + tx_pwr_os = tx_pwr_ch_os[8]; + break; + case 2457: + tx_pwr_os = tx_pwr_ch_os[9]; + break; + case 2462: + tx_pwr_os = tx_pwr_ch_os[10]; + break; + case 2467: + tx_pwr_os = tx_pwr_ch_os[11]; + break; + case 2472: + tx_pwr_os = tx_pwr_ch_os[12]; + break; + case 2484: + tx_pwr_os = tx_pwr_ch_os[13]; + break; + default: + tx_pwr_os = 0; + break; + } + +} + +static int32_t Tthr; + +static int8_t temps_dvga[16] = { + -4, -8, -4, -8, + -4, -8, -4, -8, + -4, -8, -5, -9, + -4, -8, -5, -9, +}; + +void rf_pri_update_dvga_os(int8_t dvga_os) { + for (int i = 0; i < 16; i++) { + temps_dvga[i] = tx_pwr_table[i][5] + dvga_os; + } +} + +// TODO: re-verify this function +void rf_pri_tx_gain_comp(int32_t Tsens) { + + if (((up_dn == 1) && ((Tthr <= Tsens) || (Tsens <= Tthr + -5))) + || ((((up_dn != -1 && up_dn != 1) || (Tsens <= Tthr)) || (Tthr + 5 <= Tsens)))) { + uint32_t dvga_os = 0; + int i; + for (i = 12; i >= 0; i--) { + if (temps[i] <= Tsens) + break; + } + if (i == -1) i = 0; + int32_t index_os = i - 4; + int32_t T = temps[i]; + Tthr = T; + if (Tsens < 35) { + if (T < Tsens) { + Tthr = temps[i + 1]; + if (34 < temps[i + 1]) { + Tthr = T; + } + } else { + index_os = i - 5; + } + } else { + if (T < 36) { + Tthr = temps[i + 1]; + } + } + + if (index_os_pre_mdb < index_os) { + up_dn = 1; + } else { + if (index_os_pre_mdb > index_os) + up_dn = -1; + } + if (index_os < 1) { + dvga_os = 0; + index_os_pre = index_os; + if (index_os != 0) { + dvga_os = -1; + if ((index_os & 1) != 0) { + dvga_os = 1; + } + index_os_pre = (index_os - 1) / 2; + } + } else { + dvga_os = (index_os + 1) & 1; + if (dvga_os == 0) { + dvga_os = -1; + } + index_os_pre = (index_os + 1) / 2; + } + tx_pwr_os_temperature = index_os_pre * -10; + dvga_os_pre = dvga_os; + index_os_pre_mdb = index_os; + } else { + tx_pwr_os_temperature = index_os_pre * -10; + } + + rf_pri_update_dvga_os(dvga_os_pre); + rfc_apply_tx_dvga(temps_dvga); +} + + +void rf_pri_update_txgain_tempos(int16_t tempos) { + tx_pwr_os_temperature = tempos; +} + +int32_t rf_pri_get_txgain_max(void) { + return tx_pwr_table[0][6] + tx_pwr_os + tx_pwr_os_temperature; +} + +int32_t rf_pri_get_txgain_min(void) { + return tx_pwr_table[15][6] + tx_pwr_os + tx_pwr_os_temperature; +} + +uint32_t rf_pri_get_txgain_index(int32_t pwr, uint32_t mode) { + pwr += tx_pwr_os; + if (mode == E_RF_MODE_11B) { + pwr -= 33; + } + for (int i = 0; i < E_RF_TXPWR_TBL_CNT; i++) { + if (pwr >= tx_pwr_table[i][6]) { + return i; + } + } + return E_RF_TXPWR_TBL_CNT - 1; +} + + +static void rf_pri_chipv(uint8_t chipv) { + #define cpy_rev(dest, rev) memcpy(dest, dest##_a##rev, sizeof(dest##_a##rev)); + // init based on chip revision + if (chipv == 0) { + tmxcss[0] = 3; + tmxcss[1] = 6; + tmxcss[2] = 6; + cpy_rev(tx_pwr_table, 0); + memcpy(tx_pwr_table_origin, tx_pwr_table_a0, sizeof(tx_pwr_table_a0)); + cpy_rev(tx_pwr_ch_os, 0); + cpy_rev(txcal_para, 0); + opti_regs = &opti_regs_data_a0; + } + if (chipv == 1) { + tmxcss[0] = 5; + tmxcss[1] = 5; + tmxcss[2] = 5; + cpy_rev(tx_pwr_table, 1); + memcpy(tx_pwr_table_origin, tx_pwr_table_a1, sizeof(tx_pwr_table_a1)); + cpy_rev(tx_pwr_ch_os, 1); + cpy_rev(txcal_para, 1); + opti_regs = &opti_regs_data_a1; + } +} + +static int32_t init_fast = 0; + +static void rf_pri_fixed_val_regs(){ + AON->dcdc18_top_0.dcdc18_vpfm_aon = 3; + HBN->HBN_GLB.sw_ldo11_rt_vout_sel = 8; + PACK(RF->pucr1, pucr1) { + pucr1.pu_sfreg = 1; + pucr1.pu_adda_ldo = 1; + } + AON->xtal_cfg.xtal_capcode_extra_aon = 1; + // leak code also set xtal_capcode_out_aon and xtal_capcode_in_aon + + if (!init_fast) { + BL602_Delay_MS(10); + } + + PACK(RF->pa1, pa1) { + pa1.pa_iaq = 2; + pa1.pa_iet = opti_regs->iet; + pa1.pa_vbcore = opti_regs->vbcore; + pa1.pa_vbcas = 4; + } + PACK(RF->pa_reg_ctrl_hw1, pa_reg_ctrl_hw1) { + pa_reg_ctrl_hw1.pa_iet_11n = opti_regs->iet_11n; + pa_reg_ctrl_hw1.pa_vbcas_11n = 4; + pa_reg_ctrl_hw1.pa_vbcore_11n = opti_regs->vbcore_11n; + } + PACK(RF->pa_reg_ctrl_hw2, pa_reg_ctrl_hw2) { + pa_reg_ctrl_hw2.pa_iet_11g = opti_regs->iet_11g; + pa_reg_ctrl_hw2.pa_vbcore_11g = opti_regs->vbcore_11g; + pa_reg_ctrl_hw2.pa_vbcas_11g = 4; + + pa_reg_ctrl_hw2.pa_iet_11b = opti_regs->iet_11b; + pa_reg_ctrl_hw2.pa_vbcore_11b = opti_regs->vbcore_11b; + pa_reg_ctrl_hw2.pa_vbcas_11b = 4; + } + + RF->adda2.adc_gt_rm = 1; + + RF->fbdv.lo_fbdv_halfstep_en = opti_regs->lo_fbdv_halfstep_en; + + PACK(RF->lo_reg_ctrl_hw1, lo_reg_ctrl_hw1) { + lo_reg_ctrl_hw1.lo_fbdv_halfstep_en_tx = opti_regs->lo_fbdv_halfstep_en_tx; + lo_reg_ctrl_hw1.lo_fbdv_halfstep_en_rx = opti_regs->lo_fbdv_halfstep_en_rx; + // the disassembly uses lo_fbdv_halfstep_en_tx for both, and + // in chipv it also uses lo_fbdv_halfstep_en_tx for both, + // I think it's typo + } + + PACK(RF->lo_reg_ctrl_hw1, lo_reg_ctrl_hw1) { + lo_reg_ctrl_hw1.lo_lf_rz_tx = 0; + lo_reg_ctrl_hw1.lo_lf_cz_tx = 3; + lo_reg_ctrl_hw1.lo_cp_sel_tx = 0; + } + + PACK(RF->pa_reg_wifi_ctrl_hw, pa_reg_wifi_ctrl_hw) { + pa_reg_wifi_ctrl_hw.pa_half_on_wifi = 0; + pa_reg_wifi_ctrl_hw.pa_ib_fix_wifi = 0; + } +} + +static void rf_pri_restore_cal_reg(void) { + PACK(RF->rosdac_ctrl_hw1, rosdac) { + rosdac.rosdac_i_gc0 = rf_calib_data->rxcal[0].rosdac_i; + rosdac.rosdac_q_gc0 = rf_calib_data->rxcal[0].rosdac_q; + rosdac.rosdac_i_gc1 = rf_calib_data->rxcal[1].rosdac_i; + rosdac.rosdac_q_gc1 = rf_calib_data->rxcal[1].rosdac_q; + } + PACK(RF->rosdac_ctrl_hw2, rosdac) { + rosdac.rosdac_i_gc2 = rf_calib_data->rxcal[2].rosdac_i; + rosdac.rosdac_q_gc2 = rf_calib_data->rxcal[2].rosdac_q; + rosdac.rosdac_i_gc3 = rf_calib_data->rxcal[3].rosdac_i; + rosdac.rosdac_q_gc3 = rf_calib_data->rxcal[3].rosdac_q; + } + PACK(RF->rbb2, rbb2) { + rbb2.rbb_cap1_fc_i = rf_calib_data->cal.rbb_cap1_fc_i; + rbb2.rbb_cap1_fc_q = rf_calib_data->cal.rbb_cap1_fc_q; + rbb2.rbb_cap2_fc_i = rf_calib_data->cal.rbb_cap2_fc_i; + rbb2.rbb_cap2_fc_q = rf_calib_data->cal.rbb_cap2_fc_q; + } + + PACK(RF->tbb, tbb) { + tbb.tbb_tosdac_i = rf_calib_data->txcal[3].tosdac_i; + tbb.tbb_tosdac_q = rf_calib_data->txcal[3].tosdac_q; + } + + PACK(RF->dfe_ctrl_0, dfe_ctrl_0) { + dfe_ctrl_0.tx_iqc_gain = rf_calib_data->txcal[3].tx_iq_gain_comp; + dfe_ctrl_0.tx_iqc_phase = rf_calib_data->txcal[3].tx_iq_phase_comp; + } +} + +void rf_pri_init(uint8_t reset, uint8_t chipv) { + rf_pri_chipv(chipv); + init_fast = reset == 0; + + rf_pri_fixed_val_regs(); + + PDS->pu_rst_clkpll.clkpll_reset_postdiv = opti_regs->clkpll_reset_postdiv; + PDS->clkpll_sdm.clkpll_dither_sel = opti_regs->clkpll_dither_sel; + RF->adda1.dac_dvdd_sel = 2; + HBN->HBN_GLB.sw_ldo11soc_vout_sel_aon = 0xc; + + rf_pri_set_gain_table_regs(); + + PDS->clkpll_top_ctrl.clkpll_refclk_sel = 1; + PACK(PDS->clkpll_output_en, clkpll_output_en) { + clkpll_output_en.clkpll_en_480m = 1; + clkpll_output_en.clkpll_en_240m = 1; + clkpll_output_en.clkpll_en_192m = 1; + clkpll_output_en.clkpll_en_160m = 1; + clkpll_output_en.clkpll_en_120m = 1; + clkpll_output_en.clkpll_en_96m = 1; + clkpll_output_en.clkpll_en_80m = 1; + clkpll_output_en.clkpll_en_48m = 1; + } + + if (rf_calib_data->inited && !reset) { + rf_pri_restore_cal_reg(); + } else { + rf_pri_full_cal(); + rf_calib_data->inited = 1; + } +} + +void rf_pri_init_fast(uint32_t flag) { + init_fast = flag; +} + +/// data for different crystal freq +static uint32_t channel_div_table_24M[21] = { + 0x21638e39, 0x2171c71c, 0x21800000, 0x218e38e4, 0x219c71c7, + 0x21aaaaab, 0x21b8e38e, 0x21c71c72, 0x21d55555, 0x21e38e39, + 0x21f1c71c, 0x22000000, 0x220e38e4, 0x221c71c7, 0x222aaaab, + 0x2238e38e, 0x22471c72, 0x22555555, 0x22638e39, 0x2271c71c, + 0x22800000 +}; +static uint16_t channel_cnt_table_24M[21] = { + 0xa6f2, 0xa739, 0xa780, 0xa7c7, 0xa80e, 0xa855, 0xa89c, 0xa8e4, + 0xa92b, 0xa972, 0xa9b9, 0xaa00, 0xaa47, 0xaa8e, 0xaad5, 0xab1c, + 0xab64, 0xabab, 0xabf2, 0xac39, 0xac80 +}; +static uint16_t channel_cnt_range_24M[21] = { + 0xa6a7, 0xa6e7, 0xace7 +}; +static int32_t rx_notch_para_24M[14][2] = { + {0, 0}, {1, 7000000}, {1, 2000000}, {1, -3000000}, {1, -8000000}, {0, 0}, + {1, 6000000}, {1, 1000000}, {1, -4000000}, {1, -9000000}, {0, 0}, {1, 5000000}, + {1, 0}, {0, 0} +}; +static uint16_t fcal_div_24M = 1280; + +static uint32_t channel_div_table_26M[21] = { + 0x1ed20d21, 0x1edf2df3, 0x1eec4ec5, 0x1ef96f97, 0x1f069069, + 0x1f13b13b, 0x1f20d20d, 0x1f2df2df, 0x1f3b13b1, 0x1f483483, + 0x1f555555, 0x1f627627, 0x1f6f96f9, 0x1f7cb7cb, 0x1f89d89e, + 0x1f96f970, 0x1fa41a42, 0x1fb13b14, 0x1fbe5be6, 0x1fcb7cb8, + 0x1fd89d8a +}; +static uint16_t channel_cnt_table_26M[21] = { + 0xa6fc, 0xa743, 0xa78a, 0xa7d1, 0xa819, 0xa860, 0xa8a7, 0xa8ee, + 0xa935, 0xa97c, 0xa9c3, 0xaa0a, 0xaa52, 0xaa99, 0xaae0, 0xab27, + 0xab6e, 0xabb5, 0xabfc, 0xac43, 0xac8b +}; +static uint16_t channel_cnt_range_26M[21] = { + 0xa6b1, 0xa6f1, 0xacf2 +}; +static int32_t rx_notch_para_26M[14][2] = { + {1, 6000000}, {1, 1000000}, {1, -4000000}, {1, -9000000}, {0, 0}, {1, 7000000}, + {1, 2000000}, {1, -3000000}, {1, -8000000}, {0, 0}, {1, 8000000}, {1, 3000000}, + {1, -2000000}, {0, 0} +}; +static uint16_t fcal_div_26M = 1387; + +static uint32_t channel_div_table_32M[21] = { + 0x190aaaab, 0x19155555, 0x19200000, 0x192aaaab, 0x19355555, + 0x19400000, 0x194aaaab, 0x19555555, 0x19600000, 0x196aaaab, + 0x19755555, 0x19800000, 0x198aaaab, 0x19955555, 0x19a00000, + 0x19aaaaab, 0x19b55555, 0x19c00000, 0x19caaaab, 0x19d55555, + 0x19e00000 +}; +static uint16_t channel_cnt_table_32M[21] = { + 0xa6fa, 0xa741, 0xa788, 0xa7d0, 0xa817, 0xa85e, 0xa8a5, 0xa8ec, + 0xa933, 0xa97a, 0xa9c1, 0xaa09, 0xaa50, 0xaa97, 0xaade, 0xab25, + 0xab6c, 0xabb3, 0xabfa, 0xac42, 0xac89 +}; +static uint16_t channel_cnt_range_32M[21] = { + 0xa6af, 0xa6ef, 0xacf0 +}; +static int32_t rx_notch_para_32M[14][2] = { + {0, 0}, {0, 0}, {1, 10000000}, {1, 5000000}, {1, 0}, {1, -5000000}, + {1, -10000000}, {0, 0}, {0, 0}, {1, 7000000}, {1, 2000000}, {1, -3000000}, + {1, -8000000}, {0, 0} +}; +static uint16_t fcal_div_32M = 1707; + +static uint32_t channel_div_table_38M4[21] = { + 0x14de38e4, 0x14e71c72, 0x14f00000, 0x14f8e38e, 0x1501c71c, + 0x150aaaab, 0x15138e39, 0x151c71c7, 0x15255555, 0x152e38e4, + 0x15371c72, 0x15400000, 0x1548e38e, 0x1551c71c, 0x155aaaab, + 0x15638e39, 0x156c71c7, 0x15755555, 0x157e38e4, 0x15871c72, + 0x15900000 +}; +static uint16_t channel_cnt_table_38M4[21] = { + 0xa6f2, 0xa739, 0xa780, 0xa7c7, 0xa80e, 0xa855, 0xa89c, 0xa8e4, + 0xa92b, 0xa972, 0xa9b9, 0xaa00, 0xaa47, 0xaa8e, 0xaad5, 0xab1c, + 0xab64, 0xabab, 0xabf2, 0xac39, 0xac80 +}; +static uint16_t channel_cnt_range_38M4[21] = { + 0xa6a7, 0xa6e7, 0xace7 +}; +static int32_t rx_notch_para_38M4[14][2] = { + {1, 7200000}, {1, 2200000}, {1, -2800000}, {1, -7800000}, {0, 0}, {0, 0}, + {0, 0}, {0, 0}, {1, 5600000}, {1, 600000}, {1, -4400000}, {1, -9400000}, + {0, 0}, {0, 0} +}; +static uint16_t fcal_div_38M4 = 2048; + +static uint32_t channel_div_table_40M[21] = { + 0x14088889, 0x14111111, 0x1419999a, 0x14222222, 0x142aaaab, + 0x14333333, 0x143bbbbc, 0x14444444, 0x144ccccd, 0x14555555, + 0x145dddde, 0x14666666, 0x146eeeef, 0x14777777, 0x14800000, + 0x14888889, 0x14911111, 0x1499999a, 0x14a22222, 0x14aaaaab, + 0x14b33333 +}; +static uint16_t channel_cnt_table_40M[21] = { + 0xa6eb, 0xa732, 0xa779, 0xa7c0, 0xa808, 0xa84f, + 0xa896, 0xa8dd, 0xa924, 0xa96b, 0xa9b2, 0xa9f9, + 0xaa40, 0xaa87, 0xaacf, 0xab16, 0xab5d, 0xaba4, + 0xabeb, 0xac32, 0xac79 +}; +static uint16_t channel_cnt_range_40M[21] = { + 0xa6a0, 0xa6e0, 0xace0 +}; +static int32_t rx_notch_para_40M[14][2] = { + {0, 0}, {0, 0}, {0, 0}, {0, 0}, {1, 8000000}, {1, 3000000}, + {1, -2000000}, {1, -7000000}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, + {1, 8000000}, {1, -4000000} +}; +static uint16_t fcal_div_40M = 2133; + +static uint32_t channel_div_table_52M[21] = { + 0xf690690, 0xf6f96f9, 0xf762762, 0xf7cb7cb, 0xf834835, + 0xf89d89e, 0xf906907, 0xf96f970, 0xf9d89d9, 0xfa41a42, + 0xfaaaaab, 0xfb13b14, 0xfb7cb7d, 0xfbe5be6, 0xfc4ec4f, + 0xfcb7cb8, 0xfd20d21, 0xfd89d8a, 0xfdf2df3, 0xfe5be5c, + 0xfec4ec5 +}; +static uint16_t channel_cnt_table_52M[21] = { + 0xa6ed, 0xa734, 0xa77b, 0xa7c2, 0xa809, 0xa850, + 0xa897, 0xa8de, 0xa925, 0xa96d, 0xa9b4, 0xa9fb, + 0xaa42, 0xaa89, 0xaad0, 0xab17, 0xab5e, 0xaba5, + 0xabec, 0xac34, 0xac7b +}; +static uint16_t channel_cnt_range_52M[21] = { + 0xa6a2, 0xa6e2, 0xace2 +}; +static int32_t rx_notch_para_52M[14][2] = { + {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {1, 7000000}, + {1, 2000000}, {1, -3000000}, {1, -8000000}, {0, 0}, {0, 0}, {0, 0}, + {0, 0}, {0, 0} +}; +static uint16_t fcal_div_52M = 2773; + +void rf_pri_xtalfreq(uint32_t xtalfreq) { + switch (xtalfreq) { + case E_RF_XTAL_24M: + memcpy(channel_div_table, channel_div_table_24M, sizeof(channel_div_table)); + memcpy(channel_cnt_table, channel_cnt_table_24M, sizeof(channel_cnt_table)); + memcpy(channel_cnt_range, channel_cnt_range_24M, sizeof(channel_cnt_range)); + memcpy(rx_notch_para, rx_notch_para_24M, sizeof(rx_notch_para)); + fcal_div = fcal_div_24M; + break; + case E_RF_XTAL_26M: + memcpy(channel_div_table, channel_div_table_26M, sizeof(channel_div_table)); + memcpy(channel_cnt_table, channel_cnt_table_26M, sizeof(channel_cnt_table)); + memcpy(channel_cnt_range, channel_cnt_range_26M, sizeof(channel_cnt_range)); + memcpy(rx_notch_para, rx_notch_para_26M, sizeof(rx_notch_para)); + fcal_div = fcal_div_26M; + break; + case E_RF_XTAL_32M: + memcpy(channel_div_table, channel_div_table_32M, sizeof(channel_div_table)); + memcpy(channel_cnt_table, channel_cnt_table_32M, sizeof(channel_cnt_table)); + memcpy(channel_cnt_range, channel_cnt_range_32M, sizeof(channel_cnt_range)); + memcpy(rx_notch_para, rx_notch_para_32M, sizeof(rx_notch_para)); + fcal_div = fcal_div_32M; + break; + case E_RF_XTAL_38M4: + default: + memcpy(channel_div_table, channel_div_table_38M4, sizeof(channel_div_table)); + memcpy(channel_cnt_table, channel_cnt_table_38M4, sizeof(channel_cnt_table)); + memcpy(channel_cnt_range, channel_cnt_range_38M4, sizeof(channel_cnt_range)); + memcpy(rx_notch_para, rx_notch_para_38M4, sizeof(rx_notch_para)); + fcal_div = fcal_div_38M4; + break; + case E_RF_XTAL_40M: + memcpy(channel_div_table, channel_div_table_40M, sizeof(channel_div_table)); + memcpy(channel_cnt_table, channel_cnt_table_40M, sizeof(channel_cnt_table)); + memcpy(channel_cnt_range, channel_cnt_range_40M, sizeof(channel_cnt_range)); + memcpy(rx_notch_para, rx_notch_para_40M, sizeof(rx_notch_para)); + fcal_div = fcal_div_40M; + break; + case E_RF_XTAL_52M: + memcpy(channel_div_table, channel_div_table_52M, sizeof(channel_div_table)); + memcpy(channel_cnt_table, channel_cnt_table_52M, sizeof(channel_cnt_table)); + memcpy(channel_cnt_range, channel_cnt_range_52M, sizeof(channel_cnt_range)); + memcpy(rx_notch_para, rx_notch_para_52M, sizeof(rx_notch_para)); + fcal_div = fcal_div_52M; + break; + } +} diff --git a/src/bl602_wifi/driver/phy/phy_rf/macro.h b/src/bl602_wifi/driver/phy/phy_rf/macro.h new file mode 100644 index 0000000..2b706f6 --- /dev/null +++ b/src/bl602_wifi/driver/phy/phy_rf/macro.h @@ -0,0 +1,47 @@ +#ifndef _MACRO_H_ +#define _MACRO_H_ + +#define EXPAND(...) __VA_ARGS__ + +#define EVAL5(...) EXPAND(EXPAND(__VA_ARGS__)) +#define EVAL4(...) EVAL5(EVAL5(__VA_ARGS__)) +#define EVAL3(...) EVAL4(EVAL4(__VA_ARGS__)) +#define EVAL2(...) EVAL3(EVAL3(__VA_ARGS__)) +#define EVAL1(...) EVAL2(EVAL2(__VA_ARGS__)) +#define EVAL(...) EVAL1(EVAL1(__VA_ARGS__)) + +#define FIRST(a, ...) a +#define SECOND(a, b, ...) b + +#define IS_PROBE(...) SECOND(__VA_ARGS__, 0) +#define PROBE() 0,1 +#define NOT_0 PROBE() +#define NOT(x) IS_PROBE(CAT(NOT_, x)) +#define BOOL(x) NOT(NOT(x)) + + +#define EAT(...) +#define DEFER(x) x EMPTY() +#define DEFER2(x) x EMPTY EMPTY()() +#define EMPTY() + +#define CAT(a,b) a ## b + +#define IF(c) _IF(BOOL(c)) +#define _IF(c) CAT(_IF_,c) +#define _IF_0(...) +#define _IF_1(...) __VA_ARGS__ + +#define HAS_ARGS(...) BOOL(FIRST(_END_OF_ARGUMENTS_ __VA_ARGS__)(0)) +#define _END_OF_ARGUMENTS_(...) BOOL(FIRST(__VA_ARGS__)) + +#define APPLY_NEXT(func, a, ...) \ + func(a) \ + IF(HAS_ARGS(__VA_ARGS__)) (DEFER2(_APPLY_NEXT)()(func, __VA_ARGS__)) +#define APPLY(func, ...) \ + IF(HAS_ARGS(__VA_ARGS__)) (EVAL(APPLY_NEXT(func, ##__VA_ARGS__))) +#define _APPLY_NEXT() APPLY_NEXT + +#define PACK(var, name) for (int tip = 1; tip;) for (__typeof__ (var) name = var; tip; tip = 0, var = name) + +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_adapt.c b/src/bl602_wifi/driver/phy/phy_rf/phy_adapt.c similarity index 97% rename from src/bl602_wifi/phy_adapt.c rename to src/bl602_wifi/driver/phy/phy_rf/phy_adapt.c index 8235b71..8f8a888 100644 --- a/src/bl602_wifi/phy_adapt.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_adapt.c @@ -1,7 +1,7 @@ -#include "phy_adapt.h" -#include "utils.h" -#include "phy_hal.h" -#include "assert.h" +#include +#include +#include +#include static pa_state_t pa_env[4]; // :136:19 @@ -117,7 +117,7 @@ void pa_init(void) { float calc_ppm_dsss(uint8_t rxv_freqoff) { - return ((double)rxv_freqoff) * 0.7; + return ((double)((int8_t)rxv_freqoff)) * 0.7; } float calc_ppm_ofdm(uint16_t rxv_freqoff) { diff --git a/src/bl602_wifi/phy_bl602.c b/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c similarity index 74% rename from src/bl602_wifi/phy_bl602.c rename to src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c index 4d98ce9..8d4173e 100644 --- a/src/bl602_wifi/phy_bl602.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c @@ -3,14 +3,17 @@ #include #include #include - -#include "phy_bl602.h" -#include "phy_trpc.h" -#include "rfc_bl602.h" -#include "phy_adapt.h" -#include "phy_tcal.h" -#include "rf.h" -#include "assert.h" +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include "macro.h" static int8_t rxgain_offset_vs_temperature; // :79:15 static int8_t poweroffset[14]; // :80:15 @@ -37,13 +40,21 @@ void phy_get_channel(struct phy_channel_info *info, uint8_t index) { } uint8_t phy_get_mac_freq(void) { - return 0x28; + return PHY_BL602_MACCORE_FREQ_MHZ; } uint8_t phy_get_nss(void) { return (uint8_t)(( (int8_t)(MDM->version.nss & 0xf) )- 1); } +uint8_t phy_get_nsts(void) { + return (uint8_t)(( (int8_t)(MDM->version.nsts & 0xf) )- 1); +} + +uint8_t phy_get_ntx(){ + return (uint8_t)(( (int8_t)(MDM->version.ntx & 0xf) )- 1); +} + void phy_get_version(uint32_t *version_1,uint32_t *version_2) { *version_1 = MDM->version.value; *version_2 = 0; @@ -119,18 +130,21 @@ void agc_config(void) { } void bz_phy_reset(void) { + int tx_rampup_time_us = 8; + int tx_rampdn_time_us = 4; // 4 + int tx_padzero_time_us = 0; BZ_PHY->r0x2808.bz_phy_tx_rampup_fm_on = 0x1; - BZ_PHY->r0x2808.bz_phy_tx_rampup_time_us = 0x8; + BZ_PHY->r0x2808.bz_phy_tx_rampup_time_us = tx_rampup_time_us; BZ_PHY->r0x280c.bz_phy_tx_rampdn_fm_on = 0x1; - BZ_PHY->r0x280c.bz_phy_tx_rampdn_time_us = 0x4; - BZ_PHY->r0x280c.bz_phy_tx_rampdn_pad0_time_us = 0x0; + BZ_PHY->r0x280c.bz_phy_tx_rampdn_time_us = tx_rampdn_time_us; + BZ_PHY->r0x280c.bz_phy_tx_rampdn_pad0_time_us = tx_padzero_time_us; BZ_PHY->r0x2854.bz_phy_rx_proc_time_mlsd_us = 0x20; BZ_PHY->r0x2854.bz_phy_rx_proc_time_direct_us = 0x1e; BZ_PHY->r0x2854.bz_phy_rx_proc_time_eq_us = 0xa; BZ_PHY->r0x2854.bz_phy_rx_proc_time_viterbi_us = 0x1e; BZ_PHY->r0x2810.bz_phy_rx_dfe_notch_en = 0x0; BZ_PHY->r0x2810.bz_phy_rx_dfe_toc_en = 0x1; - BZ_PHY->r0x2cac.bz_agc_rbb_ind_min = 0x4; + BZ_PHY_AGC->r0x2cac.bz_agc_rbb_ind_min = 0x4; return ; } @@ -158,7 +172,7 @@ void phy_get_rf_gain_capab(int8_t *max,int8_t *min) { } void phy_get_rf_gain_idx(int8_t *power,uint8_t *idx) { - *idx = (uint8_t)rfc_get_power_level(2, (int)*power * 10); + *idx = (uint8_t)rfc_get_power_level(RFC_FORMATMOD_11N, (int)*power * 10); } void phy_get_rf_gain_idx_vs_mode(uint8_t mode,int8_t *power,uint8_t *idx) { @@ -190,15 +204,22 @@ void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t cha MDM->rxchan.rxdsssen = 1; MDM->mdmconf = 0; mdm_reset(); - MDM->txstartdelay = 0xb4; - MDM->txctrl1 = 0x1c13; - MDM->txctrl3 = 0x2d00438; - MDM->TBECTRL0.tbe_count_adjust_20 = 0; - MDM->DCESTIMCTRL.value = 0xf0f; - MDM->DCESTIMCTRL.WAITHTSTF = 7; + + MDM->txstartdelay = 180; + MDM->txctrl1 = 0x1c13; // (txfeofdm80delay = 19, txfeofdm40delay = 28, txfeofdm20delay = 0, txfedsssdelay = 0)(txfeofdm80delay = 0x13, txfeofdm40delay = 0x1c, txfeofdm20delay = 0, txfedsssdelay = 0) + MDM->txctrl3 = 0x2d00438; // mdm_txctrl3_pack(txphyrdyhtdelay = 720, txphyrdynonhtdelay = 1080) + + MDM->TBECTRL0.tbe_count_adjust_20 = 0; // TBE for 60MHz + + MDM->DCESTIMCTRL.value = 0xf0f; // (starthtdc = 0, startdc = 0, delaysynctd20 = 0, delaysync = 0xf, waithtstf = 0xf) + + MDM->DCESTIMCTRL.WAITHTSTF = 7; // For FPGA, divide value by 2 due to timing constraints + MDM->r834.tddchtstfmargin = 0x6; - MDM->SMOOTHCTRL.value = 0x1880c06; + MDM->SMOOTHCTRL.value = 0x1880c06; // smooth enable/auto-selection MDM->tbectrl2 = 0x7f03; + + // No ACI margin in BW=20MHz due to latency on HTSIG decoding AGC->riu_rwnxagcaci20marg0 = 0; AGC->riu_rwnxagcaci20marg1 = 0; AGC->riu_rwnxagcaci20marg2 = 0; @@ -209,7 +230,7 @@ void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t cha AGC->riu_iqestiterclr = 1; } - rf_set_channel(chantype,freq1); + rf_set_channel(chantype, freq1); uint8_t channel = 0; @@ -231,19 +252,54 @@ void phy_set_channel(uint8_t band,uint8_t type,uint16_t prim20_freq,uint16_t cen extern uint32_t agcmem[]; -void phy_init(phy_cfg_tag *config) { - MDM->mdmconf = 0; +static void agc_download() { + AGC->RWNXAGCCNTL.agcfsmreset = 1; + + MDM->r0x874.mdm_agcmemclkforce = 1; + + for (int i = 0; i < PHY_BL602_AGC_MEM_SIZE / 4; i++) + AGCRAM->agcram[i] = agcmem[i]; + + MDM->r0x874.mdm_agcmemclkforce = 0; + AGC->RWNXAGCCNTL.agcfsmreset = 0; + AGC->r0xc020.rc_paoff_delay = 0x14; +} + +static void phy_hw_init(const struct phy_bl602_cfg_tag *cfg) { + MDM->mdmconf = BW_20MHZ; mdm_reset(); + + // realname = rxmode MDM->rxchan.value = 0x20d; + /* + PACK(MDM->rxchan, rxmode) { + rxmode.rxdsssen = 1; // MDM_RXDSSSEN_BIT + rxmode.pad0 = 0b11; // bit 2-3 MDM_RXMMEN_BIT MDM_RXGFEN_BIT + rxmode.pad2 = 1; // bit 9 MDM_RXSTBCEN_BIT + } + */ MDM->rxchan.rxnssmax = phy_get_nss(); - MDM->rxchan.rxndpnstsmax = MDM->version.nsts; + MDM->rxchan.rxndpnstsmax = phy_get_nsts(); MDM->rxchan.rxldpcen = MDM->version.ldpcdec; MDM->rxchan.rxvhten = phy_vht_supported(); MDM->rxchan.rxmumimoen = MDM->version.mu_mimo_rx; - MDM->r3024.precomp = 0x2D; + MDM->r3024.precomp = 45; + + // Rx frame violation check + // [31:15]: VHT + // [14: 4]: HT + // [ 3: 0]: NON-HT MDM->rxframeviolationmask = 0xffffffff; MDM->txchan.value = 0x20d; + /* + PACK(MDM->txchan, txmode) { + txmode.txdsssen = 1; // MDM_TXDSSSEN_BIT + txmode.pad1 = 0b11; // bit 2-3 MDM_TXMMEN_BIT MDM_TXGFEN_BIT + txmode.pad3 = 1; // bit 9 MDM_TXSTBCEN_BIT + } + */ + MDM->txchan.txnssmax = phy_get_nss(); MDM->txchan.ntxmax = phy_get_ntx(); MDM->txchan.txcbwmax = MDM->version.chbw; @@ -251,10 +307,16 @@ void phy_init(phy_cfg_tag *config) { MDM->txchan.vht = phy_vht_supported(); MDM->txchan.txmumimoen = MDM->version.mu_mimo_tx; + // AGC reset mode + // Don't turn off RF if rxreq de-asserted for few cycles after a RXERR MDM->r834.rxtdctrl1 = 1; + + // Enable automatic smoothing filter selection from SNR, then disable force MDM->SMOOTHCTRL.CFGSMOOTHFORCE = 0; MDM->SMOOTHSNRTHR.smoothsnrthrhigh = 0x1b; MDM->SMOOTHSNRTHR.smoothsnrthrmid = 0xf; + + // limit NDBPSMAX to 1x1 80 MCS7 LGI(292.5Mb/s) / SGI (325.0Mb/s) MDM->rxctrl1 = 0x4920492; MDM->r0x874.rcclkforce = 1; @@ -266,27 +328,33 @@ void phy_init(phy_cfg_tag *config) { AGC->r0xb110.riu_rxiqgaincompen = 0; AGC->riu_iqestiterclr = 0; } + + // limit RIU to 1 or 2 antenna active depending on modem capabilities AGC->activeant = 1; + + // limit AGC with a single antenna (path0) AGC->RWNXAGCCNTL.combpathsel = 1; + + // CCA timeout AGC->RWNXAGCCCATIMEOUT = 4000000; AGC->irqmacccatimeouten.irqmacccatimeouten = 1; + agc_config(); - AGC->RWNXAGCCNTL.agcfsmreset = 1; - MDM->r0x874.mdm_agcmemclkforce = 1; + agc_download(); +} + +void phy_init(phy_cfg_tag *config) { + const struct phy_bl602_cfg_tag *cfg = (const struct phy_bl602_cfg_tag *)&config->parameters; + phy_hw_init(cfg); - for (int i = 0; i < 0x200; i++) - AGCRAM->agcram[i] = agcmem[i]; - - MDM->r0x874.mdm_agcmemclkforce = 0; - AGC->RWNXAGCCNTL.agcfsmreset = 0; - AGC->r0xc020.rc_paoff_delay = 0x14; phy_env[0].cfg.reserved = (config->parameters)[0]; - phy_env[0].chnl_center1_freq = 0xff; - phy_env[0].chnl_center2_freq = 0xff; - phy_env[0].chnl_prim20_freq = 0xff; - phy_env[0].band = 0x00; + phy_env[0].chnl_center1_freq = PHY_UNUSED; + phy_env[0].chnl_center2_freq = PHY_UNUSED; + phy_env[0].chnl_prim20_freq = PHY_UNUSED; + phy_env[0].band = PHY_BAND_2G4; phy_env[0].chnl_type = PHY_CHNL_BW_OTHER; + trpc_init(); pa_init(); phy_tcal_reset(); @@ -294,9 +362,9 @@ void phy_init(phy_cfg_tag *config) { } uint8_t phy_vht_supported() { - if (MDM->version.vht) // TODO: verify this cond + if (MDM->version.vht) return 1; - return ((MDM->version.chbw) >> 1) & 1; + return MDM->version.chbw > PHY_CHNL_BW_40; } uint8_t phy_ldpc_rx_supported(void) { @@ -322,7 +390,8 @@ uint8_t phy_mu_mimo_tx_supported(void) { void phy_rc_isr(void) { uint32_t val = AGC->rwnxmacintstatmasked.value; AGC->rwnxmacintack = val; - if (val & 0x100) { + if (val & 0x100) { + // RIU_IRQMACCCATIMEOUTMASKED_BIT mdm_reset(); } } diff --git a/src/bl602_wifi/phy_hal.c b/src/bl602_wifi/driver/phy/phy_rf/phy_hal.c similarity index 97% rename from src/bl602_wifi/phy_hal.c rename to src/bl602_wifi/driver/phy/phy_rf/phy_hal.c index 3d44b30..2875832 100644 --- a/src/bl602_wifi/phy_hal.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_hal.c @@ -1,4 +1,4 @@ -#include "phy_hal.h" +#include #include static struct phy_hal_tag hal_env; diff --git a/src/bl602_wifi/phy_helper.c b/src/bl602_wifi/driver/phy/phy_rf/phy_helper.c similarity index 99% rename from src/bl602_wifi/phy_helper.c rename to src/bl602_wifi/driver/phy/phy_rf/phy_helper.c index 45a5c1f..e342402 100644 --- a/src/bl602_wifi/phy_helper.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_helper.c @@ -1,4 +1,4 @@ -#include "phy_helper.h" +#include #include #include #include diff --git a/src/bl602_wifi/phy_tcal.c b/src/bl602_wifi/driver/phy/phy_rf/phy_tcal.c similarity index 87% rename from src/bl602_wifi/phy_tcal.c rename to src/bl602_wifi/driver/phy/phy_rf/phy_tcal.c index 5d625b8..c2cdded 100644 --- a/src/bl602_wifi/phy_tcal.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_tcal.c @@ -1,14 +1,14 @@ -#include "phy_tcal.h" -#include "phy_hal.h" -#include "phy_bl602.h" -#include "phy_trpc.h" -#include "bl602_rf_private.h" -#include "utils.h" +#include +#include +#include +#include +#include +#include static struct tcal_tag tcal_env; // :41:24 void phy_tcal_reset(void) { - memset(&tcal_env,0,0x38); + memset(&tcal_env, 0, sizeof(tcal_env)); tcal_env.prev_temperature = 0x19; tcal_env.last_action_temperature[0] = 0x19; tcal_env.last_action_temperature[1] = 0x19; diff --git a/src/bl602_wifi/phy_trpc.c b/src/bl602_wifi/driver/phy/phy_rf/phy_trpc.c similarity index 96% rename from src/bl602_wifi/phy_trpc.c rename to src/bl602_wifi/driver/phy/phy_rf/phy_trpc.c index ac39fe9..1e758d6 100644 --- a/src/bl602_wifi/phy_trpc.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_trpc.c @@ -1,7 +1,7 @@ -#include "phy_trpc.h" -#include "phy_bl602.h" -#include "bl602_rf_private.h" -#include "utils.h" +#include +#include +#include +#include static int8_t txpwr_vs_rate_table[3][8] = { {0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12}, diff --git a/src/bl602_wifi/rf.c b/src/bl602_wifi/driver/phy/phy_rf/rf.c similarity index 52% rename from src/bl602_wifi/rf.c rename to src/bl602_wifi/driver/phy/phy_rf/rf.c index 8c6b786..cc2d079 100644 --- a/src/bl602_wifi/rf.c +++ b/src/bl602_wifi/driver/phy/phy_rf/rf.c @@ -1,5 +1,5 @@ -#include "rf.h" -#include "rfc_bl602.h" +#include +#include void rf_set_channel(uint8_t bandwidth, uint16_t channel_freq) { rfc_config_channel(channel_freq); @@ -10,12 +10,8 @@ void rf_clkpll_isr(void) { } void rf_init(void) { - __asm( - "csrrci a5, mstatus, 0x8\n\t" - "andi a5, a5, 0x8\n\t" - "beqz a5, .L0\n\t" - "csrrsi zero, mstatus, 0x8\n\t" - ".L0:" + __asm("csrci mstatus, 8\n\t" + "csrsi mstatus, 8\n\t" ); } diff --git a/src/bl602_wifi/driver/phy/phy_rf/rf_private_save.h b/src/bl602_wifi/driver/phy/phy_rf/rf_private_save.h new file mode 100644 index 0000000..06aa13b --- /dev/null +++ b/src/bl602_wifi/driver/phy/phy_rf/rf_private_save.h @@ -0,0 +1,29 @@ +#ifdef RF_PRI_SAVE +RF_PRI_SAVE(rf_fsm_ctrl_hw); +RF_PRI_SAVE(rfctrl_hw_en); +RF_PRI_SAVE(rfcal_ctrlen); +RF_PRI_SAVE(pucr1); +RF_PRI_SAVE(fbdv); +RF_PRI_SAVE(sdm1); +RF_PRI_SAVE(sdm2); +RF_PRI_SAVE(rbb3); +RF_PRI_SAVE(adda1); +RF_PRI_SAVE(dfe_ctrl_0); +RF_PRI_SAVE(dfe_ctrl_3); +RF_PRI_SAVE(dfe_ctrl_6); +RF_PRI_SAVE(dfe_ctrl_7); +RF_PRI_SAVE(trx_gain1); +RF_PRI_SAVE(singen_ctrl0); +RF_PRI_SAVE(singen_ctrl2); +RF_PRI_SAVE(singen_ctrl3); +RF_PRI_SAVE(rf_sram_ctrl0); +RF_PRI_SAVE(rf_sram_ctrl1); +RF_PRI_SAVE(rf_sram_ctrl2); +RF_PRI_SAVE(rf_resv_reg_1); +RF_PRI_SAVE(pa1); +RF_PRI_SAVE(ten_ac); +RF_PRI_SAVE(rfif_dfe_ctrl0); +RF_PRI_SAVE(tbb); +RF_PRI_SAVE(vco2); +#undef RF_PRI_SAVE +#endif \ No newline at end of file diff --git a/src/bl602_wifi/driver/phy/phy_rf/rfc_bl602.c b/src/bl602_wifi/driver/phy/phy_rf/rfc_bl602.c new file mode 100644 index 0000000..c3374ed --- /dev/null +++ b/src/bl602_wifi/driver/phy/phy_rf/rfc_bl602.c @@ -0,0 +1,784 @@ + +#include +#include +#include + +#include +#include +#include +#include + +#define prefix "[RFC] " + +static int inited = 0; +static double xtalfreq_MHz = 40.0; +static void wait_us(uint32_t); +static void wait_ms(uint32_t); +static void _set_rfc(); +static void _set_mdm(); +static void _set_rf_channel_sw(uint32_t); +static void _set_rf_channel_hw(uint32_t); +static uint32_t _calc_sdm_cw(float xtalfreq_MHz, float freq); +//static void _calc_sdm_params(uint32_t xtalfreq,uint32_t *lo_center_freq_mhz,uint32_t *lo_sdmin_center,uint32_t *lo_sdmin_1m,uint32_t *lo_sdmin_if); +static void _set_rfc_powercontrol(uint32_t pc_mode); + +// todo: check me +static void _sync_tx_power_offset() { + uint32_t rfg_index; + uint32_t dg; + + typedef struct { + uint32_t rf_tbb_ind_gc : 3; // @ 2 -- 0 # 0xfffffff8 + uint32_t pad0 : 1; + } __attribute__((packed)) rf_tbb_ind_t; + union { + rf_tbb_ind_t val[16]; + uint32_t pack[2]; + } rf_tbb_ind = {.pack = {0}}; + typedef struct { + uint32_t tx_dvga_gain_qdb_gc : 7; // @ 6 -- 0 # 0xffffff80 + uint32_t pad0 : 1; + } __attribute__((packed)) dvga_gain_t; + union { + dvga_gain_t val[16]; + uint32_t pack[4]; + } dvga_gain = {.pack = {0}}; + for (int i = 0; i < 16; i++) { + rf_pri_query_txgain_table(i, &rfg_index, &dg); + rf_tbb_ind.val[i].rf_tbb_ind_gc = rfg_index & 7; + dvga_gain.val[i].tx_dvga_gain_qdb_gc = dg; + } + RF->dfe_ctrl_16.value = rf_tbb_ind.pack[0]; + RF->dfe_ctrl_12.value = dvga_gain.pack[0]; + RF->dfe_ctrl_13.value = dvga_gain.pack[1]; + RF->dfe_ctrl_17.value = rf_tbb_ind.pack[1]; + RF->dfe_ctrl_14.value = dvga_gain.pack[2]; + RF->dfe_ctrl_15.value = dvga_gain.pack[3]; +} + +void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset) { + rf_pri_update_tx_power_offset(channel, power_offset); + _sync_tx_power_offset(); +} + +// todo: check me +void rfc_apply_tx_dvga(int8_t *dvga_qdb) { + uint32_t dvga_qdb_align[4]; + memcpy(dvga_qdb_align, dvga_qdb, sizeof(dvga_qdb_align)); + dvga_qdb_align[0] &= 0x7f7f7f7f; + dvga_qdb_align[1] &= 0x7f7f7f7f; + dvga_qdb_align[2] &= 0x7f7f7f7f; + dvga_qdb_align[3] &= 0x7f7f7f7f; + RF->dfe_ctrl_12.value = dvga_qdb_align[0]; + RF->dfe_ctrl_13.value = dvga_qdb_align[1]; + RF->dfe_ctrl_14.value = dvga_qdb_align[2]; + RF->dfe_ctrl_15.value = dvga_qdb_align[3]; +} + +// todo: verify me +void rfc_apply_tx_dvga_offset(int8_t offset_qdb) { + volatile uint8_t * gain = (volatile uint8_t *) (&RF->dfe_ctrl_12); + for (int i = 0; i < 16; i++) { + uint8_t vold_gain = gain[i]; + int old_gain = ((int)vold_gain << 0x19) >> 0x19; + int new_gain = RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc0 + offset_qdb; + if (new_gain > 24) + new_gain = 24; + if (new_gain < -48) + new_gain = -48; + gain[i] = (vold_gain & 0x80) | (new_gain & 0x7f); + } +} + +void rfc_rxdfe_set_notch0(uint8_t en, uint8_t alpha, int8_t nrmfc) { + RF->r0x1700.rf_rx_notch0_en = en; + RF->r0x1700.rf_rx_notch0_alpha = alpha; + RF->r0x1700.rf_rx_notch0_nrmfc = nrmfc; +} + +static void _set_rf_channel_hw(uint32_t channel_freq) { + RF->rf_fsm_ctrl0.rf_ch_ind_wifi = channel_freq & 0xfff; + RF->rf_fsm_ctrl1.rf_fsm_lo_rdy_rst = 1; + wait_us(10); + RF->rf_fsm_ctrl1.rf_fsm_lo_rdy_rst = 0; + wait_us(10); + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; + wait_us(10); + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 1; + wait_us(10); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg = 1; + wait_us(10); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 1; + wait_us(10); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg = 2; + wait_us(100); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 0; + wait_us(10); +} + +static void _print_channel_info() { + printf("Channel information:\r\n"); + printf(" lo_sdmin_hw %lx\r\n", RF->sdm3.lo_sdmin_hw); + printf(" lo_sdmbypass_hw %ld\r\n", RF->sdm1.lo_sdm_bypass_hw); + printf(" lo_vco_idac_cw_hw %lx\r\n", RF->vco1.lo_vco_idac_cw_hw); + printf(" lo_vco_freq_cw_hw %lx\r\n", RF->vco1.lo_vco_freq_cw_hw); + printf(" lo_unlocked %ld\r\n", RF->rf_fsm_ctrl_sw.lo_unlocked); + printf(" lo_halfstep_en_hw %ld\r\n", RF->fbdv.lo_fbdv_halfstep_en_hw); + printf(" lo_slipped_up"); + for (int i = 0; i < 8; i++) { + wait_us(1000); + printf("%ld", RF->lo.lo_slipped_up ? (uint32_t)1 : (uint32_t)0); + } + printf("\r\n"); + printf(" lo_slipped_dn "); + for (int i = 0; i < 8; i++) { + wait_us(1000); + printf("%ld", RF->lo.lo_slipped_dn ? (uint32_t)1 : (uint32_t)0); + } + printf("\r\n"); +} + +void rfc_config_channel(uint32_t channel_freq) { + RF->rfif_dig_ctrl.rfif_int_lo_unlocked_mask = 1; + RF->rfctrl_hw_en.lo_ctrl_hw = 1; + RF->rfctrl_hw_en.sdm_ctrl_hw = 1; + RF->rfctrl_hw_en.pu_ctrl_hw = 1; + + _set_rf_channel_hw(channel_freq); + _print_channel_info(); + rf_pri_update_param(channel_freq); + uint8_t ncf_on; + int32_t ncf_freq_Hz; + rf_pri_get_notch_param(channel_freq, &ncf_on, (int32_t *)&ncf_freq_Hz); + double freq = ncf_freq_Hz; + freq /= 40000000.0; + freq *= 256.0; + freq += 0.5; + int32_t new_freq = freq; + rfc_rxdfe_set_notch0(ncf_on, 1, new_freq); + RF->rfif_dig_ctrl.rfif_int_lo_unlocked_mask = 0; +} + +void rfc_config_channel_sw(uint32_t channel_freq) { + RF->rfctrl_hw_en.lo_ctrl_hw = 0; + RF->rfctrl_hw_en.sdm_ctrl_hw = 0; + RF->rfctrl_hw_en.pu_ctrl_hw = 0; + _set_rf_channel_sw(channel_freq); + + rf_pri_update_param(channel_freq); + uint8_t ncf_on; + int32_t ncf_freq_Hz; + rf_pri_get_notch_param(channel_freq, &ncf_on, &ncf_freq_Hz); + double ncf_fs_Hz = 40 * 1000 * 1000; + int8_t ncf_nrmfc = (int8_t)((ncf_freq_Hz / ncf_fs_Hz) * (1 << 8) + 0.5); + uint8_t ncf_alpha = 1; + rfc_rxdfe_set_notch0(ncf_on, ncf_alpha, ncf_nrmfc); +} + + +void rfc_config_power(uint32_t mode, uint32_t tbb_boost, uint32_t tbb, uint32_t tmx) { + _set_rfc_powercontrol(mode); + + RF->trx_gain1.gc_tbb_boost = tbb_boost; + RF->trx_gain1.gc_tbb = tbb; + RF->trx_gain1.gc_tmx = tmx; +} + + +void rfc_config_bandwidth(uint32_t mode) { + if (mode == RFC_BW_20M) { + // dac + PDS->clkpll_output_en.clkpll_en_div2_480m = 0; + + // adc + RF->adda2.adc_clk_div_sel = 1; + RF->rfif_dig_ctrl.rfckg_rxclk_div2_mode = 0; + + // rbb bw + RF->rbb3.rbb_bw = 2; + // rmxgm + RF->rmxgm.rmxgm_10m_mode_en = 0; + } + else if (mode == RFC_BW_10M) { + // dac + PDS->clkpll_output_en.clkpll_en_div2_480m = 1; + + // adc + + RF->adda2.adc_clk_div_sel = 0; + RF->rfif_dig_ctrl.rfckg_rxclk_div2_mode = 1; + + // rbb bw + RF->rbb3.rbb_bw = 1; + + // rmxgm + RF->rmxgm.rmxgm_10m_mode_en = 1; + } +} + + +uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power) { + if (formatmod > 2) + formatmod = 0; + return rf_pri_get_txgain_index(power, formatmod) << 2; +} + +void rfc_init(uint32_t xtalfreq_hz) { + RF->rfif_dfe_ctrl0.bbmode_4s = 0; + RF->rfif_dfe_ctrl0.bbmode_4s_en = 1; + int xtal_mode = 4; + switch (xtalfreq_hz) { + case 24000000: + xtal_mode = 1; + break; + case 32000000: + xtal_mode = 2; + break; + case 38400000: + xtal_mode = 3; + break; + case 52000000: + xtal_mode = 5; + break; + case 40000000: + default: + break; + } + rf_pri_xtalfreq(xtal_mode); + rf_pri_init(!inited, 1); + inited = 1; + + + _set_rfc(xtalfreq_hz); + _set_mdm(); + + RF->rfif_dfe_ctrl0.bbmode_4s_en = 0; + + // leak code has RF Optimized and CFG_RF_ICAL here + RF->rf_fsm_ctrl_hw.rf_fsm_t2r_cal_mode = 0; + + PDS->clkpll_output_en.clkpll_en_80m = 0; + wait_us(1); + RF->rf_fsm_ctrl_hw.rf_fsm_t2r_cal_mode = 1; + wait_us(1); + PDS->clkpll_output_en.clkpll_en_80m = 1; + + // _check_config(); skipped + printf("rf controller init done\r\n"); +} + +void rfc_reset() { + inited = 0; + rfc_init(xtalfreq_MHz * 1000 * 1000); +} + +static uint32_t _calc_sdm_cw(float xtalfreq_MHz, float freq) { + return (((freq * 4.0) / 3.0) / xtalfreq_MHz) * (1<<22); +} + +void rfc_ver_set(uint8_t ver) { + return ; +} + +void rfc_wlan_mode_force(uint32_t force_mode) { + if (force_mode < 3) { + RF->rfif_dfe_ctrl0.wifimode_4s = force_mode; + RF->rfif_dfe_ctrl0.wifimode_4s_en = 1; + } else { + RF->rfif_dfe_ctrl0.wifimode_4s = 0; + RF->rfif_dfe_ctrl0.wifimode_4s_en = 0; + } +} + +void rfc_txdfe_start() { + RF->rfif_dfe_ctrl0.tx_dfe_en_4s = 1; + wait_us(1); + RF->rfif_dfe_ctrl0.tx_dfe_en_4s_en = 1; +} + +void rfc_txdfe_stop() { + RF->rfif_dfe_ctrl0.tx_dfe_en_4s = 0; + wait_us(1); + RF->rfif_dfe_ctrl0.tx_dfe_en_4s_en = 0; +} + +void rfc_txdfe_mux(int8_t signal_source) { + RF->rfif_dfe_ctrl0.tx_test_sel = signal_source & 3; +} + +void rfc_txdfe_set_dvga(int8_t dvga_qdb) { + if (dvga_qdb < -48 || dvga_qdb > +24) { + printf(prefix "dvga_qdb out of range -48~+24,skip\r\n"); + return ; + } + RF->dfe_ctrl_0.tx_dvga_gain_qdb = dvga_qdb; +} + +void rfc_txdfe_set_iqgaincomp(uint8_t en,uint16_t coeff) { + RF->dfe_ctrl_0.tx_iqc_gain_en = en; + RF->dfe_ctrl_0.tx_iqc_gain = coeff; +} + +void rfc_txdfe_set_iqphasecomp(uint8_t en,int16_t coeff) { + RF->dfe_ctrl_0.tx_iqc_phase_en = en; + RF->dfe_ctrl_0.tx_iqc_phase = coeff; +} + +void rfc_txdfe_set_dccomp(int16_t dcc_i,int16_t dcc_q) { + RF->dfe_ctrl_1.tx_dac_os_i = dcc_i; + RF->dfe_ctrl_1.tx_dac_os_q = dcc_q; + +} + +void rfc_txdfe_set_iqswap(uint8_t swap_on) { + RF->dfe_ctrl_1.tx_dac_iq_swap = swap_on; +} + +void rfc_rxdfe_start() {} +void rfc_rxdfe_stop(); +void rfc_rxdfe_set_iqgaincomp(uint8_t en,uint16_t coeff); +void rfc_rxdfe_set_iqphasecomp(uint8_t en,int16_t coeff); +void rfc_rxdfe_set_dccomp(int16_t dcc_i,int16_t dcc_q); +void rfc_rxdfe_set_iqswap(uint8_t swap_on); +void rfc_rxdfe_set_notch0(uint8_t en,uint8_t alpha,int8_t nrmfc); +void rfc_rxdfe_set_notch1(uint8_t en,uint8_t alpha,int8_t nrmfc); + + +void rfc_sg_start(uint32_t inc_step,uint32_t gain_i,uint32_t gain_q,uint32_t addr_i,uint32_t addr_q) { + RF->singen_ctrl0.singen_en = 0; + RF->singen_ctrl0.singen_inc_step0 = inc_step; + RF->singen_ctrl0.singen_clkdiv_n = 0; // work clock + RF->singen_ctrl1.singen_mode_i = RFC_SG_SINGLE_TONE; // 0: single tone, 1: two tone, 2: ramp + RF->singen_ctrl1.singen_mode_q = RFC_SG_SINGLE_TONE; // 0: single tone, 1: two tone, 2: ramp + + RF->singen_ctrl2.singen_gain_i = gain_i; + RF->singen_ctrl3.singen_gain_q = gain_q; + + RF->singen_ctrl2.singen_start_addr0_i = addr_i; + RF->singen_ctrl3.singen_start_addr0_q = addr_q; + + RF->singen_ctrl0.singen_en = 1; +} + +void rfc_sg_stop() { + RF->singen_ctrl0.singen_en = 0; +} + +uint32_t rfc_pm_start(uint32_t insel,int32_t freq_cw,uint32_t acclen,uint32_t rshiftlen, + int32_t *raw_acc_i,int32_t *raw_acc_q) { + + // turn off and configure power meter + RF->dfe_ctrl_6.rx_pm_en = 0; + + RF->dfe_ctrl_7.rx_pm_start_ofs = 1024; + + RF->dfe_ctrl_7.rx_pm_acc_len = acclen; + RF->dfe_ctrl_6.rx_pm_freqshift_en = (freq_cw != 0); + RF->dfe_ctrl_6.rx_pm_freqshift_cw = freq_cw; + + RF->dfe_ctrl_6.rx_pm_in_sel = insel; + RF->dfe_ctrl_6.rx_pm_en = 1; + + wait_us(100); + + int32_t iqacc_i = RF->dfe_ctrl_8.rx_pm_iqacc_i; // 25BIT + int32_t iqacc_q = RF->dfe_ctrl_9.rx_pm_iqacc_q; // 25BIT + iqacc_i = iqacc_i << 7 >> 7; + iqacc_q = iqacc_q << 7 >> 7; + + if (raw_acc_i) { + *raw_acc_i = iqacc_i; + } + if (raw_acc_q) { + *raw_acc_q = iqacc_q; + } + + iqacc_i = iqacc_i >> rshiftlen; + iqacc_q = iqacc_q >> rshiftlen; + + uint64_t pwr64 = (int64_t)iqacc_i * (int64_t)iqacc_i + (int64_t)iqacc_q * (int64_t)iqacc_q; + + if ((pwr64 >> 32) != 0) { + printf(prefix "overflow occurred\r\n"); + } + + return (uint32_t)(pwr64 & 0xffffffff); +} + +void rfc_pm_stop() { + RF->dfe_ctrl_6.rx_pm_en = 0; + RF->dfe_ctrl_6.rx_pm_freqshift_en = 0; +} + +void rfc_hwctrl_txrfgain(uint8_t hwctrl_on) { + RF->rfctrl_hw_en.tx_gain_ctrl_hw = hwctrl_on; +} + +void rfc_hwctrl_rxgain(uint8_t hwctrl_on) { + RF->rfctrl_hw_en.rx_gain_ctrl_hw = hwctrl_on; +} + +void rfc_hwctrl_txdvga(uint8_t hwctrl_on) { + RF->dfe_ctrl_0.tx_dvga_gain_ctrl_hw = hwctrl_on; +} + +void rfc_hwctrl_calparam(uint8_t hwctrl_on) { + RF->rfctrl_hw_en.trxcal_ctrl_hw = hwctrl_on; +} + +void rfc_fsm_force(uint8_t state) { + if (state != RFC_FSM_FORCE_OFF) { + RF->rf_fsm_ctrl2.rf_fsm_st_dbg = state; + wait_us(20); + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 1; + } else { + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 0; + } +} + +void rfc_rc_fsm_force(uint8_t state) { + if (state == RFC_FSM_FORCE_OFF) { + RF->rf_fsm_ctrl_hw.rf_rc_state_dbg = 0; + wait_us(20); + RF->rf_fsm_ctrl_hw.rf_rc_state_dbg_en = 0; + } else { + RF->rf_fsm_ctrl_hw.rf_rc_state_dbg = state; + wait_us(20); + RF->rf_fsm_ctrl_hw.rf_rc_state_dbg_en = 1; + } +} + +void rfc_coex_force_to(uint32_t force_enable, uint32_t bbmode) { + // reset rf_fsm, fpga_fsm, state_cci + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; + + wait_us(10); + + // force coex + RF->rfif_dfe_ctrl0.bbmode_4s = bbmode; + RF->rfif_dfe_ctrl0.bbmode_4s_en = force_enable ? 1 : 0; + + wait_us(10); + + // start fsm + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 1; +} + +void rfc_dump() { + struct rfc_status_tag *p_test_read; + uint32_t test_read[2]; + static char* rc_state_str[8] = { + "RC_IDLE", + "RC_RX2ON", + "RC_TX2ON", + "RC_RXON", + "RC_TX2PAON", + "RC_TXPAON", + "UNKNOWN", + "UNKNOWN" + }; + static char* rf_state_str[8] = { + "RF_PD", + "RF_SB", + "RF_LO", + "RF_RX", + "RF_TX", + "RF_T2RI", + "RF_R2T", + "RF_MS" + }; + + + RF->rfif_dfe_ctrl0.test_sel = 1; + test_read[0] = RF->rfif_test_read.value; + + RF->rfif_dfe_ctrl0.test_sel = 2; + test_read[1] = RF->rfif_test_read.value; + + p_test_read = (struct rfc_status_tag*)test_read; + + printf("******************************** [RFC DUMP START] *****************************\r\n"); + printf(" rc_state : %s\r\n", rc_state_str[p_test_read->rf_rc_state]); + printf(" rf_state : %s\r\n", rf_state_str[p_test_read->rf_fsm_state]); + printf(" fsm_pu_lna : %d\r\n", p_test_read->fsm_pu_lna ); + printf(" fsm_pu_rmxgm : %d\r\n", p_test_read->fsm_pu_rmxgm ); + printf(" fsm_pu_rmx : %d\r\n", p_test_read->fsm_pu_rmx ); + printf(" fsm_pu_rbb : %d\r\n", p_test_read->fsm_pu_rbb ); + printf(" fsm_pu_pkdet : %d\r\n", p_test_read->fsm_pu_pkdet ); + printf(" fsm_pu_adc : %d\r\n", p_test_read->fsm_pu_adc ); + printf(" fsm_trsw_en : %d\r\n", p_test_read->fsm_trsw_en ); + printf(" fsm_pu_dac : %d\r\n", p_test_read->fsm_pu_dac ); + printf(" fsm_pu_tosdac : %d\r\n", p_test_read->fsm_pu_tosdac); + printf(" fsm_pu_rxbuf : %d\r\n", p_test_read->fsm_pu_rxbuf ); + printf(" fsm_pu_txbuf : %d\r\n", p_test_read->fsm_pu_txbuf ); + + printf("\r\n\r\n"); + printf(" tx_gain_ctrl_hw : %ld\r\n", RF->rfctrl_hw_en.tx_gain_ctrl_hw); + printf(" rx_gain_ctrl_hw : %ld\r\n", RF->rfctrl_hw_en.rx_gain_ctrl_hw); + printf(" trxcal_ctrl_hw : %ld\r\n", RF->rfctrl_hw_en.trxcal_ctrl_hw); + printf(" lo_ctrl_hw : %ld\r\n", RF->rfctrl_hw_en.lo_ctrl_hw); + printf(" lna_ctrl_hw : %ld\r\n", RF->rfctrl_hw_en.lna_ctrl_hw); + printf(" pu_ctrl_hw : %ld\r\n", RF->rfctrl_hw_en.pu_ctrl_hw); + + printf("\r\n\r\n"); + printf(" rf_lo_vco_freq_cw_hw : %ld\r\n", RF->vco1.lo_vco_freq_cw_hw); + printf(" rf_lo_vco_idac_cw_hw : %ld\r\n", RF->vco1.lo_vco_idac_cw_hw); + printf(" rf_lo_sdmin_hw : %ld\r\n", RF->sdm3.lo_sdmin_hw); + printf(" rf_ch_ind_wifi : %ld\r\n", RF->rf_fsm_ctrl0.rf_ch_ind_wifi); + + + if (RF->rf_fsm_ctrl_sw.lo_unlocked) { + printf("rf_lo_unlocked_getf = 1\r\n"); + printf("rf_lo_unlocked_getf (after csd reset) = "); + for (int i = 0; i < 8; i++) { + RF->pfdcp.lo_pfd_rst_csd = 1; + wait_us(10); + RF->pfdcp.lo_pfd_rst_csd = 0; + wait_us(10); + printf("%ld", RF->rf_fsm_ctrl_sw.lo_unlocked); + } + printf("\r\n"); + } + else { + printf("rf_lo_unlocked_getf = 0\r\n"); + } + + printf("******************************** [RFC DUMP END] *****************************\r\n"); + +} + +_Bool rfc_config_power_ble(int32_t pwr_dbm) { + int i2 = 0; + if ((uint32_t)pwr_dbm < 16) { + if (pwr_dbm < 4) { + RF->pa1.pa_ib_fix = 1; + RF->pa1.pa_half_on = 1; + RF->pa1.pa_vbcas = 4; + RF->pa1.pa_vbcore = 9; + RF->pa1.pa_etb_en = 0; // weird, this 9 will always be 0 + RF->tmx.tmx_cs = 5; + RF->trx_gain1.gc_tbb = 2; + RF->trx_gain1.gc_tmx = 5; + i2 = pwr_dbm * 4 - 18; + } else { + if (pwr_dbm < 7) { + RF->pa1.pa_ib_fix = 1; + RF->pa1.pa_half_on = 1; + RF->pa1.pa_vbcas = 4; + RF->pa1.pa_vbcore = 9; + RF->pa1.pa_etb_en = 0; // weird, this 9 will always be 0 + RF->tmx.tmx_cs = 5; + RF->trx_gain1.gc_tbb = 2; + RF->trx_gain1.gc_tmx = 7; + i2 = pwr_dbm * 4 - 30; + } else { + if (pwr_dbm < 10) { + RF->pa1.pa_ib_fix = 1; + RF->pa1.pa_half_on = 1; + RF->pa1.pa_vbcas = 4; + + RF->pa1.pa_vbcore = 9; + RF->pa1.pa_etb_en = 0; // weird, this 9 will always be 0 + + RF->tmx.tmx_cs = 5; + RF->trx_gain1.gc_tbb = 3; + RF->trx_gain1.gc_tmx = 7; + i2 = pwr_dbm - 10; + } else { + if (pwr_dbm < 12) { + RF->pa1.pa_ib_fix = 1; + RF->pa1.pa_half_on = 1; + RF->pa1.pa_vbcas = 4; + + RF->pa1.pa_vbcore = 9; + RF->pa1.pa_etb_en = 0; // weird, this 9 will always be 0 + + RF->tmx.tmx_cs = 5; + RF->trx_gain1.gc_tbb = 4; + RF->trx_gain1.gc_tmx = 7; + i2 = pwr_dbm - 12; + } else { + RF->pa1.pa_ib_fix = 1; + RF->pa1.pa_half_on = 1; + RF->pa1.pa_vbcas = 4; + + RF->pa1.pa_vbcore = 9; + RF->pa1.pa_etb_en = 0; // weird, this 9 will always be 0 + + RF->tmx.tmx_cs = 5; + RF->trx_gain1.gc_tbb = 6; + RF->trx_gain1.gc_tmx = 7; + i2 = pwr_dbm - 15; + } + } + i2 = i2 << 2; + } + } + uint32_t u2 = i2 - 1; + RF->dfe_ctrl_18.tx_dvga_gain_qdb_ble_gc0 = u2 & 0x7f; + RF->dfe_ctrl_18.tx_dvga_gain_qdb_ble_gc1 = u2 & 0x7f; + RF->dfe_ctrl_18.tx_dvga_gain_qdb_ble_gc2 = u2 & 0x7f; + } +} + + + + +static void _set_rfc(uint32_t xtalfreq_hz) { + xtalfreq_MHz = xtalfreq_hz / 1000000; + float xtal_MHz = xtalfreq_hz / 1000000; + uint32_t lo_center_freq_mhz; + /// _calc_sdm_params + if (xtalfreq_hz == 40000000) { + lo_center_freq_mhz = 2430.0; + } else { + lo_center_freq_mhz = 2448.0; + } + RF->lo_sdm_ctrl_hw5.lo_center_freq_mhz = lo_center_freq_mhz; //??? + uint32_t lo_sdmin_center = _calc_sdm_cw(xtal_MHz, lo_center_freq_mhz); + uint32_t lo_sdmin_1m = _calc_sdm_cw(xtal_MHz, 1.0); + uint32_t lo_sdmin_if = _calc_sdm_cw(xtal_MHz, 1.25); + RF->lo_sdm_ctrl_hw6.lo_sdmin_center = lo_sdmin_center; + RF->lo_sdm_ctrl_hw7.lo_sdmin_1m = lo_sdmin_1m; + RF->lo_sdm_ctrl_hw8.lo_sdmin_if = lo_sdmin_if; + + union { + uint8_t seq[2][2]; + uint32_t val; + } lo_cw = {.val = 0}; + volatile uint32_t *ptr = (volatile uint32_t *)&(RF->lo_cal_ctrl_hw1); + for (int freq = 2404, i = 0; freq <= 2484; freq += 4, i += 1) { + int freq_cw = rf_pri_get_vco_freq_cw(freq); + int idac_cw = rf_pri_get_vco_idac_cw(freq); + if (freq == 2404) freq_cw += 1; + lo_cw.seq[i&1][0] = idac_cw; + lo_cw.seq[i&1][1] = freq_cw; + if ((freq == 2484) || (i&1)) { + *ptr = lo_cw.val; + lo_cw.val = 0; + ptr++; + } + } + + _sync_tx_power_offset(); + + // configure rf_fsm related params + RF->rf_fsm_ctrl_hw.rf_rc_state_dbg_en = 0; + RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 0; + RF->rf_fsm_ctrl1.rf_fsm_lo_time = 0x1040; + RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 1; + + // configure tx gain control + RF->rfctrl_hw_en.tx_gain_ctrl_hw = 1; + RF->dfe_ctrl_0.tx_dvga_gain_ctrl_hw = 1; + RF->dfe_ctrl_0.tx_dvga_gain_qdb = 0; + + // configure rf compensation paramas + // turn off trxcal if ROSDAC table changes vs gain to prevent pkdet false triggers + // caused by the transient response of ROSDAC + RF->rfctrl_hw_en.trxcal_ctrl_hw = 1; + + // configure rx gain control + RF->rfctrl_hw_en.rx_gain_ctrl_hw = 1; + +} + +static void _set_mdm() { + AGC->rc218.txhbf20coeffsel = 0; + MDM->r3030 = 0; + MDM->r3034 = 0xa027f7f; + MDM->r3038 = 0x23282317; + MDM->r303c = 0x7f020a17; + MDM->r3040 = 0x7f; +} + + + + + +static void wait_us(uint32_t us) +{ + volatile uint32_t n; + us = (us >= (1<<24)-1) ? (1<<24)-1 : us; + // if (us < 2) { + // return; + // } + // else + { + n = us << 4; + while(n--); + } +} + +__attribute__((unused)) static void wait_ms(uint32_t ms) +{ + wait_us(1000*ms); +} + +static void _set_rfc_powercontrol(uint32_t pc_mode) { + RF->pa1.pa_ib_fix = 0; + RF->tmx.tmx_cs = 6; + switch (pc_mode) { + case RFC_PC_AUTO: + RF->pa_reg_ctrl_hw2.pa_vbcore_11b = 0xf; + RF->pa_reg_ctrl_hw1.pa_vbcore_11n = 0xa; + RF->pa_reg_ctrl_hw2.pa_vbcore_11g = 0xa; + + RF->pa_reg_ctrl_hw2.pa_vbcas_11b = 5; + RF->pa_reg_ctrl_hw1.pa_vbcas_11n = 5; + RF->pa_reg_ctrl_hw2.pa_vbcas_11g = 5; + + RF->pa_reg_ctrl_hw2.pa_iet_11b = 7; + RF->pa_reg_ctrl_hw1.pa_iet_11n = 5; + RF->pa_reg_ctrl_hw2.pa_iet_11g = 5; + case RFC_PC_WLAN_11B: + case RFC_PC_BT_BLE: + RF->pa1.pa_vbcore = 0xf; + RF->pa1.pa_vbcas = 5; + RF->pa1.pa_iet = 7; + break; + case RFC_PC_WLAN_11N: + case RFC_PC_WLAN_11G: + RF->pa1.pa_vbcore = 0xa; + RF->pa1.pa_vbcas = 5; + RF->pa1.pa_iet = 5; + break; + } + RF->trx_gain1.gc_tbb_boost = 0; + RF->trx_gain1.gc_tbb = 6; + RF->trx_gain1.gc_tmx = 5; + RF->adda1.dac_bias_sel = 1; +} + +static void _set_rf_channel_sw(uint32_t channel_freq) { + uint32_t sdmin = (uint32_t)(channel_freq*4.0/3/xtalfreq_MHz*(1<<22)); + + RF->rfctrl_hw_en.lo_ctrl_hw = 0; + RF->rfctrl_hw_en.sdm_ctrl_hw = 0; + RF->pucr1.pu_vco = 1; + RF->pucr1.pu_fbdv = 1; + RF->pucr1.pu_pfd = 1; + RF->pucr1.pu_osmx = 1; + RF->rfctrl_hw_en.pu_ctrl_hw = 0; + + // set channel + // rf_lo_fbdv_halfstep_en_setf(1); + RF->vco1.lo_vco_freq_cw = rf_pri_get_vco_freq_cw(channel_freq); + RF->vco1.lo_vco_idac_cw = rf_pri_get_vco_idac_cw(channel_freq); + RF->lodist.lo_osmx_cap = rf_pri_get_vco_freq_cw(channel_freq) >> 4; + + RF->sdm2.lo_sdmin = sdmin; + RF->sdm1.lo_sdm_bypass = 0; + + // wait channel lock + do { + RF->fbdv.lo_fbdv_rst = 1; + wait_us(10); + RF->fbdv.lo_fbdv_rst = 0; + wait_us(50); + RF->pfdcp.lo_pfd_rst_csd = 1; + wait_us(10); + RF->pfdcp.lo_pfd_rst_csd = 0; + wait_us(50); + } while (0); +} \ No newline at end of file diff --git a/src/bl602_wifi/phyif_utils.c b/src/bl602_wifi/driver/phyif/phyif_utils.c similarity index 98% rename from src/bl602_wifi/phyif_utils.c rename to src/bl602_wifi/driver/phyif/phyif_utils.c index 92e0623..6715d87 100644 --- a/src/bl602_wifi/phyif_utils.c +++ b/src/bl602_wifi/driver/phyif/phyif_utils.c @@ -1,4 +1,4 @@ -#include "phyif_utils.h" +#include typedef struct { uint32_t leg_length:12; // +0 diff --git a/src/bl602_wifi/phy.h b/src/bl602_wifi/phy.h deleted file mode 100644 index db83a71..0000000 --- a/src/bl602_wifi/phy.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _PHY_H_ -#define _PHY_H_ -#include -struct phy_channel_info { - uint32_t info1; // +0 - uint32_t info2; // +4 -}; // :97:8 -#endif \ No newline at end of file diff --git a/src/bl602_wifi/rfc_bl602.c b/src/bl602_wifi/rfc_bl602.c deleted file mode 100644 index c16622e..0000000 --- a/src/bl602_wifi/rfc_bl602.c +++ /dev/null @@ -1,169 +0,0 @@ - -#include "rfc_bl602.h" -#include "bl602_rf_private.h" -#include "utils.h" - -#include - -void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset){ - rf_pri_update_tx_power_offset(channel, power_offset); - uint32_t rfg_index, dg; - rf_pri_query_txgain_table(0, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc0 = rfg_index & 7; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc0 = dg; - rf_pri_query_txgain_table(1, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc1 = rfg_index & 7; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc1 = dg; - rf_pri_query_txgain_table(2, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc2 = rfg_index & 7; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc2 = dg; - rf_pri_query_txgain_table(3, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc3 = rfg_index & 7; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc3 = dg; - rf_pri_query_txgain_table(4, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc4 = rfg_index & 7; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc4 = dg; - rf_pri_query_txgain_table(5, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc5 = rfg_index & 7; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc5 = dg; - rf_pri_query_txgain_table(6, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc6 = rfg_index & 7; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc6 = dg; - rf_pri_query_txgain_table(7, &rfg_index, &dg); - RF->dfe_ctrl_16.rf_tbb_ind_gc7 = rfg_index & 7; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc7 = dg; - rf_pri_query_txgain_table(8, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc8 = rfg_index & 7; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc8 = dg; - rf_pri_query_txgain_table(9, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc9 = rfg_index & 7; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc9 = dg; - rf_pri_query_txgain_table(10, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc10 = rfg_index & 7; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc10 = dg; - rf_pri_query_txgain_table(11, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc11 = rfg_index & 7; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc11 = dg; - rf_pri_query_txgain_table(12, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc12 = rfg_index & 7; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc12 = dg; - rf_pri_query_txgain_table(13, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc13 = rfg_index & 7; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc13 = dg; - rf_pri_query_txgain_table(14, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc14 = rfg_index & 7; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc14 = dg; - rf_pri_query_txgain_table(15, &rfg_index, &dg); - RF->dfe_ctrl_17.rf_tbb_ind_gc15 = rfg_index & 7; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc15 = dg; - -} - - - -void rfc_apply_tx_dvga(int8_t *dvga_qdb) { - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc0 = dvga_qdb[0]; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc1 = dvga_qdb[1]; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc2 = dvga_qdb[2]; - RF->dfe_ctrl_12.tx_dvga_gain_qdb_gc3 = dvga_qdb[3]; - - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc4 = dvga_qdb[4]; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc5 = dvga_qdb[5]; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc6 = dvga_qdb[6]; - RF->dfe_ctrl_13.tx_dvga_gain_qdb_gc7 = dvga_qdb[7]; - - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc8 = dvga_qdb[8]; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc9 = dvga_qdb[9]; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc10 = dvga_qdb[10]; - RF->dfe_ctrl_14.tx_dvga_gain_qdb_gc11 = dvga_qdb[11]; - - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc12 = dvga_qdb[12]; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc13 = dvga_qdb[13]; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc14 = dvga_qdb[14]; - RF->dfe_ctrl_15.tx_dvga_gain_qdb_gc15 = dvga_qdb[15]; -} - -void rfc_coex_force_to(uint32_t force_enable, uint32_t bbmode) { - RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; - wait_us(10); - RF->rfif_dfe_ctrl0.bbmode_4s = bbmode & 1; - RF->rfif_dfe_ctrl0.bbmode_4s_en = (force_enable != 0); -} - -void rfc_config_channel(uint32_t channel_freq) { - RF->rfif_dig_ctrl.rfif_int_lo_unlocked_mask = 1; - RF->rfctrl_hw_en.lo_ctrl_hw = 1; - RF->rfctrl_hw_en.sdm_ctrl_hw = 1; - RF->rfctrl_hw_en.pu_ctrl_hw = 1; - RF->rf_fsm_ctrl0.rf_ch_ind_wifi = channel_freq & 0xfff; - RF->rf_fsm_ctrl1.rf_fsm_lo_rdy_rst = 1; - wait_us(10); - RF->rf_fsm_ctrl1.rf_fsm_lo_rdy_rst = 0; - wait_us(10); - RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 0; - wait_us(10); - RF->rf_fsm_ctrl_hw.rf_fsm_ctrl_en = 1; - wait_us(10); - RF->rf_fsm_ctrl2.rf_fsm_st_dbg = 1; - wait_us(10); - RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 1; - wait_us(10); - RF->rf_fsm_ctrl2.rf_fsm_st_dbg = 2; - wait_us(100); - RF->rf_fsm_ctrl2.rf_fsm_st_dbg_en = 0; - wait_us(10); - _print_channel_info(); - rf_pri_update_param(channel_freq); - uint8_t ncf_on; - int32_t ncf_freq_Hz; - rf_pri_get_notch_param(channel_freq, &ncf_on, (int32_t *)&ncf_freq_Hz); - double freq = ncf_freq_Hz; - freq /= 40000000.0; - freq *= 256.0; - freq += 0.5; - int32_t new_freq = freq; - rfc_rxdfe_set_notch0(ncf_on, 1, new_freq); - RF->rfif_dig_ctrl.rfif_int_lo_unlocked_mask = 0; -} - -uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power) { - if (formatmod > 2) - formatmod = 0; - return rf_pri_get_txgain_index(power, formatmod) << 2; -} - -void rfc_init(uint32_t xtalfreq_hz) { - RF->rfif_dfe_ctrl0.bbmode_4s = 0; - RF->rfif_dfe_ctrl0.bbmode_4s_en = 1; - int xtal_mode = 2; - if (xtalfreq_hz != 32000000) { - if (xtalfreq_hz < 0x1e84801) { - xtal_mode = 0; - if (xtalfreq_hz == 24000000) { - xtal_mode = 1; - } else { - xtal_mode = 4; - } - } else { - if (xtalfreq_hz != 40000000) { - xtal_mode = 5; - if (xtalfreq_hz != 52000000) { - if (xtalfreq_hz == 38400000) { - xtal_mode = 3; - } else { - xtal_mode = 4; - } - } - } - } - } -} - -void _print_channel_info() { - for (int i = 0; i < 8; i++) { - wait_us(1000); - } - for (int i = 0; i < 8; i++) { - wait_us(1000); - } -} \ No newline at end of file diff --git a/src/bl602_wifi/rfc_bl602.h b/src/bl602_wifi/rfc_bl602.h deleted file mode 100644 index 51987a9..0000000 --- a/src/bl602_wifi/rfc_bl602.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _RFC_BL602_H_ -#define _RFC_BL602_H_ -#include -uint32_t rfc_get_power_level(uint32_t formatmod, int32_t power); // :1479:10 -void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset); // :1643:6 -void rfc_config_channel(uint32_t channel_freq); -void rfc_apply_tx_dvga(int8_t *dvga_qdb); -void _print_channel_info(); -#endif \ No newline at end of file diff --git a/src/bl602_wifi/assert.h b/src/include/assert.h similarity index 100% rename from src/bl602_wifi/assert.h rename to src/include/assert.h diff --git a/src/include/bl602_wifi/phy_rf/bl602_rf_calib_data.h b/src/include/bl602_wifi/phy_rf/bl602_rf_calib_data.h new file mode 100644 index 0000000..72faa65 --- /dev/null +++ b/src/include/bl602_wifi/phy_rf/bl602_rf_calib_data.h @@ -0,0 +1,58 @@ +#ifndef _BL602_RF_CALIB_DATA_H_ +#define _BL602_RF_CALIB_DATA_H_ +#include +typedef struct { + uint32_t gpadc_oscode:12; // +0 + uint32_t rx_offset_i:10; // +0 + uint32_t rx_offset_q:10; // +0 + uint32_t rbb_cap1_fc_i:6; // +4 + uint32_t rbb_cap1_fc_q:6; // +4 + uint32_t rbb_cap2_fc_i:6; // +4 + uint32_t rbb_cap2_fc_q:6; // +4 + uint32_t tx_dc_comp_i:12; // +8 + uint32_t tx_dc_comp_q:12; // +8 + uint32_t tmx_cs:3; // +8 + uint32_t txpwr_att_rec:3; // +8 + uint32_t pa_pwrmx_osdac:4; // +12 + uint32_t tmx_csh:3; // +12 + uint32_t tmx_csl:3; // +12 + uint32_t tsen_refcode_rfcal:12; // +12 + uint32_t tsen_refcode_corner:12; // +16 + uint32_t rc32k_code_fr_ext:10; // +16 + uint32_t rc32m_code_fr_ext:8; // +16 + uint32_t saradc_oscode:10; // +20 + uint16_t fcal_4osmx:4; // +20 +} rf_calib1_tag; // :37:3 + +typedef struct { + uint16_t fcal:8; // +0 + uint16_t acal:5; // +0 +} rf_calib2_tag; // :44:3 + +typedef struct { + uint32_t rosdac_i:6; // +0 + uint32_t rosdac_q:6; // +0 + uint32_t rx_iq_gain_comp:11; // +0 + uint32_t rx_iq_phase_comp:10; // +4 +} rf_calib3_tag; // :53:3 + +typedef struct { + uint32_t tosdac_i:6; // +0 + uint32_t tosdac_q:6; // +0 + uint32_t tx_iq_gain_comp:11; // +0 + uint32_t tx_iq_phase_comp:10; // +4 +} rf_calib4_tag; // :62:3 + +typedef volatile struct { + uint32_t inited; // +0 + rf_calib1_tag cal; // +4 + rf_calib2_tag lo[21]; // +28 + rf_calib3_tag rxcal[4]; // +72 + rf_calib4_tag txcal[8]; // +104 +} rf_calib_data_tag; // :72:3 + +extern rf_calib_data_tag *rf_calib_data; // :75:27 +// void rf_pri_init_calib_mem(void); +// unused + +#endif \ No newline at end of file diff --git a/src/bl602_wifi/bl602_rf_private.h b/src/include/bl602_wifi/phy_rf/bl602_rf_private.h similarity index 62% rename from src/bl602_wifi/bl602_rf_private.h rename to src/include/bl602_wifi/phy_rf/bl602_rf_private.h index 27a630f..0ac7f1e 100644 --- a/src/bl602_wifi/bl602_rf_private.h +++ b/src/include/bl602_wifi/phy_rf/bl602_rf_private.h @@ -1,7 +1,7 @@ #ifndef _BL602_RF_PRIVATE_H_ #define _BL602_RF_PRIVATE_H_ #include - +#define RF_PRIVATE_PRESENT 1 struct anon_struct1 { uint32_t index; int32_t dvga; @@ -78,4 +78,79 @@ void rf_pri_update_power_offset(int32_t * power_offset); void rf_pri_update_tx_power_offset(uint8_t channel, int8_t * power_offset); void rf_pri_update_txgain_tempos(int16_t tempos); void rf_pri_xtalfreq(uint32_t xtalfreq); + +enum { + E_RF_XTAL_24M = 0, + E_RF_XTAL_26M = 1, + E_RF_XTAL_32M = 2, + E_RF_XTAL_38M4 = 3, + E_RF_XTAL_40M = 4, + E_RF_XTAL_52M = 5, +}; + +enum +{ + E_RF_CHANNEL_2404M = 0, + E_RF_CHANNEL_2408M, + E_RF_CHANNEL_2412M, + E_RF_CHANNEL_2416M, + E_RF_CHANNEL_2420M, + E_RF_CHANNEL_2424M, + E_RF_CHANNEL_2428M, + E_RF_CHANNEL_2432M, + E_RF_CHANNEL_2436M, + E_RF_CHANNEL_2440M, + E_RF_CHANNEL_2444M, + E_RF_CHANNEL_2448M, + E_RF_CHANNEL_2452M, + E_RF_CHANNEL_2456M, + E_RF_CHANNEL_2460M, + E_RF_CHANNEL_2464M, + E_RF_CHANNEL_2468M, + E_RF_CHANNEL_2472M, + E_RF_CHANNEL_2476M, + E_RF_CHANNEL_2480M, + E_RF_CHANNEL_2484M, + E_RF_CHANNEL_NUM +}; + +enum { + E_RF_BRANCH_I = 0, + E_RF_BRANCH_Q = 1, + E_RF_GAIN = 2, + E_RF_PHASE = 3 +}; + +enum { + E_RF_MODE_11B = 0, + E_RF_MODE_11G = 1, + E_RF_MODE_11N = 2, +}; + +enum { + E_RF_GC_TBB_0DB = 0, + E_RF_GC_TBB_6DB = 1, + E_RF_GC_TBB_12DB = 2, + E_RF_GC_TBB_18DB = 3, + E_RF_GC_TBB_24DB = 4 +}; + +enum { + E_RF_MODE_IDLE = 0, + E_RF_MODE_TX, + E_RF_MODE_RX, + E_RF_MODE_ROSCAL, + E_RF_MODE_RCCAL, + E_RF_MODE_TXCAL, + E_RF_MODE_LO_ACAL, + E_RF_MODE_LO_FCAL +}; + +enum { + E_RF_RXCAL_GAIN_CNT = 4, + E_RF_TXCAL_GAIN_CNT = 8, + E_RF_TXPWR_TBL_CNT = 16, +}; + + #endif \ No newline at end of file diff --git a/src/bl602_wifi/hal_desc.h b/src/include/bl602_wifi/phy_rf/hal_desc.h similarity index 91% rename from src/bl602_wifi/hal_desc.h rename to src/include/bl602_wifi/phy_rf/hal_desc.h index 849e16b..936b96f 100644 --- a/src/bl602_wifi/hal_desc.h +++ b/src/include/bl602_wifi/phy_rf/hal_desc.h @@ -2,7 +2,18 @@ #ifndef _HAL_DESC_H_ #define _HAL_DESC_H_ #include -#include "phy.h" +#include + +/// 20 MHz bandwidth +#define BW_20MHZ 0 +/// 40 MHz bandwidth +#define BW_40MHZ 1 +/// 80 MHz bandwidth +#define BW_80MHZ 2 +/// 160 or 80+80 MHz bandwidth +#define BW_160MHZ 3 + + struct tx_policy_tbl { uint32_t upatterntx; // +0 uint32_t phycntrlinfo1; // +4 diff --git a/src/include/bl602_wifi/phy_rf/phy.h b/src/include/bl602_wifi/phy_rf/phy.h new file mode 100644 index 0000000..2a646a4 --- /dev/null +++ b/src/include/bl602_wifi/phy_rf/phy.h @@ -0,0 +1,74 @@ +#ifndef _PHY_H_ +#define _PHY_H_ +#include + + +/// Invalid value for some octet parameters reserved for the future +#define PHY_UNUSED 0xFF + +/// Maximum number of words in the configuration buffer +#define PHY_CFG_BUF_SIZE 16 + + +/* + * DEFINES + **************************************************************************************** + */ +/// Invalid value for some octet parameters reserved for the future +#define PHY_UNUSED 0xFF + +/// Maximum number of words in the configuration buffer +#define PHY_CFG_BUF_SIZE 16 + +enum +{ + /// 2.4GHz Band + PHY_BAND_2G4, + /// 5GHz band + PHY_BAND_5G, + /// Number of bands + PHY_BAND_MAX, +}; + +enum +{ + PHY_CHNL_BW_20, + PHY_CHNL_BW_40, + PHY_CHNL_BW_80, + PHY_CHNL_BW_160, + PHY_CHNL_BW_80P80, + PHY_CHNL_BW_OTHER, +}; + +enum +{ + /// Primary radar detection chain (i.e for the operating channel) + PHY_PRIM, + /// Secondary radar detection chain + PHY_SEC, +}; + +/// Structure containing the information about the PHY channel that was used for this RX +struct phy_channel_info +{ + /// PHY channel information 1 + uint32_t info1; + /// PHY channel information 2 + uint32_t info2; +}; + +struct phy_radar_pulse +{ + /// In our PHY a radar pulse is only one 32-bit word + uint32_t pulse; +}; + +/// Structure containing the parameters of the PHY configuration +struct phy_cfg_tag +{ + /// Buffer containing the parameters specific for the PHY used + uint32_t parameters[PHY_CFG_BUF_SIZE]; +}; + +typedef struct phy_cfg_tag phy_cfg_tag; +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phy_adapt.h b/src/include/bl602_wifi/phy_rf/phy_adapt.h similarity index 98% rename from src/bl602_wifi/phy_adapt.h rename to src/include/bl602_wifi/phy_rf/phy_adapt.h index 33e074e..b5a938b 100644 --- a/src/bl602_wifi/phy_adapt.h +++ b/src/include/bl602_wifi/phy_rf/phy_adapt.h @@ -1,7 +1,7 @@ #ifndef _PHY_ADAPT_H_ #define _PHY_ADAPT_H_ #include -#include "hal_desc.h" +#include typedef struct { int8_t rssi; // +0 diff --git a/src/bl602_wifi/phy_bl602.h b/src/include/bl602_wifi/phy_rf/phy_bl602.h similarity index 87% rename from src/bl602_wifi/phy_bl602.h rename to src/include/bl602_wifi/phy_rf/phy_bl602.h index dfd8b48..d74e62a 100644 --- a/src/bl602_wifi/phy_bl602.h +++ b/src/include/bl602_wifi/phy_rf/phy_bl602.h @@ -1,25 +1,16 @@ #ifndef _PHY_BL602_H_ #include -#include "phy.h" -enum -{ - /// 2.4GHz Band - PHY_BAND_2G4, - /// 5GHz band - PHY_BAND_5G, - /// Number of bands - PHY_BAND_MAX, -}; +#include -enum -{ - PHY_CHNL_BW_20, - PHY_CHNL_BW_40, - PHY_CHNL_BW_80, - PHY_CHNL_BW_160, - PHY_CHNL_BW_80P80, - PHY_CHNL_BW_OTHER, -}; +/// Maximum output power TODO +#define PHY_BL602_MAX_PWR_24G (20) +/// Minimum output power TODO +#define PHY_BL602_MIN_PWR_24G (-6) +/// MAC core clock frequency in MHz +#define PHY_BL602_MACCORE_FREQ_MHZ (40) +/// AGC memory address and size +#define PHY_BL602_AGC_MEM_ADDR (0x54c0a000) +#define PHY_BL602_AGC_MEM_SIZE (2048) enum { @@ -28,13 +19,6 @@ enum PHY_FORMATMOD_11N, }; -typedef struct phy_cfg_tag phy_cfg_tag; - -struct phy_cfg_tag { - uint32_t parameters[16]; -}; - - struct phy_bl602_cfg_tag { uint32_t reserved; }; // :48:8 diff --git a/src/bl602_wifi/phy_hal.h b/src/include/bl602_wifi/phy_rf/phy_hal.h similarity index 100% rename from src/bl602_wifi/phy_hal.h rename to src/include/bl602_wifi/phy_rf/phy_hal.h diff --git a/src/bl602_wifi/phy_helper.h b/src/include/bl602_wifi/phy_rf/phy_helper.h similarity index 100% rename from src/bl602_wifi/phy_helper.h rename to src/include/bl602_wifi/phy_rf/phy_helper.h diff --git a/src/bl602_wifi/phy_tcal.h b/src/include/bl602_wifi/phy_rf/phy_tcal.h similarity index 100% rename from src/bl602_wifi/phy_tcal.h rename to src/include/bl602_wifi/phy_rf/phy_tcal.h diff --git a/src/bl602_wifi/phy_trpc.h b/src/include/bl602_wifi/phy_rf/phy_trpc.h similarity index 100% rename from src/bl602_wifi/phy_trpc.h rename to src/include/bl602_wifi/phy_rf/phy_trpc.h diff --git a/src/bl602_wifi/rf.h b/src/include/bl602_wifi/phy_rf/rf.h similarity index 100% rename from src/bl602_wifi/rf.h rename to src/include/bl602_wifi/phy_rf/rf.h diff --git a/src/include/bl602_wifi/phy_rf/rfc_bl602.h b/src/include/bl602_wifi/phy_rf/rfc_bl602.h new file mode 100644 index 0000000..2fa9add --- /dev/null +++ b/src/include/bl602_wifi/phy_rf/rfc_bl602.h @@ -0,0 +1,199 @@ +#ifndef _RFC_BL602_H_ +#define _RFC_BL602_H_ +#include + + +enum +{ + RFC_OFF = 0, + RFC_ON = 1 +}; + +enum +{ + RFC_PM_MUX_TO_ADC = 0, + RFC_PM_MUX_TO_IQCOMP = 1, + RFC_PM_MUX_TO_BLE = 2 +}; + +enum +{ + RFC_TXDFE_IN_MUX_TO_BB = 0, + RFC_TXDFE_IN_MUX_TO_SRAM = 1, + RFC_TXDFE_IN_MUX_TO_SINGEN = 2, + RFC_TXDFE_IN_MUX_TO_PAD = 3 +}; + +enum +{ + RFC_FSM_PD = 0, + RFC_FSM_SB = 1, + RFC_FSM_LO = 2, + RFC_FSM_RX = 3, + RFC_FSM_TX = 4, + RFC_FSM_FORCE_OFF = 15 +}; + +enum +{ + RFC_BBMODE_WLAN = 0, + RFC_BBMODE_BLE = 1 +}; + +enum +{ + RFC_SG_SINGLE_TONE = 0, + RFC_SG_TWO_TONE, + RFC_SG_RAMP +}; + +enum { + RFC_PC_AUTO = 0, + RFC_PC_WLAN_11B, + RFC_PC_WLAN_11G, + RFC_PC_WLAN_11N, + RFC_PC_BT_BLE +}; + +enum { + RFC_FORMATMOD_11B = 0, + RFC_FORMATMOD_11G = 1, + RFC_FORMATMOD_11N = 2 +}; + +enum { + RFC_BW_20M = 0, + RFC_BW_10M = 1 +}; + +void rfc_init(uint32_t xtalfreq); +void rfc_reset(); +void rfc_ver_set(uint8_t ver); // :1047:6 +void rfc_config_channel(uint32_t channel_freq); +void rfc_config_channel_sw(uint32_t channel_freq); +// void rfc_write_reg(uint32_t a, uint32_t d); +// uint32_t rfc_read_reg(uint32_t a); + +uint32_t rfc_get_power_level(uint32_t mode, int32_t power); +void rfc_wlan_mode_force(uint32_t force_mode); // :1500:6 +/* + * TXDFE DECLARATIONS + **************************************************************************************** + */ +void rfc_txdfe_start(); +void rfc_txdfe_stop(); +void rfc_txdfe_mux(int8_t signal_source); +void rfc_txdfe_set_dvga(int8_t dvga_qdb); +void rfc_txdfe_set_iqgaincomp(uint8_t en,uint16_t coeff); +void rfc_txdfe_set_iqphasecomp(uint8_t en,int16_t coeff); +void rfc_txdfe_set_dccomp(int16_t dcc_i,int16_t dcc_q); +void rfc_txdfe_set_iqswap(uint8_t swap_on); + +/* + * RXDFE DECLARATIONS + **************************************************************************************** + */ +void rfc_rxdfe_start(); +void rfc_rxdfe_stop(); +void rfc_rxdfe_set_iqgaincomp(uint8_t en,uint16_t coeff); +void rfc_rxdfe_set_iqphasecomp(uint8_t en,int16_t coeff); +void rfc_rxdfe_set_dccomp(int16_t dcc_i,int16_t dcc_q); +void rfc_rxdfe_set_iqswap(uint8_t swap_on); +void rfc_rxdfe_set_notch0(uint8_t en,uint8_t alpha,int8_t nrmfc); +void rfc_rxdfe_set_notch1(uint8_t en,uint8_t alpha,int8_t nrmfc); + +/* + * SG DECLARATIONS + **************************************************************************************** + */ +void rfc_sg_start(uint32_t inc_step,uint32_t gain_i,uint32_t gain_q,uint32_t addr_i,uint32_t addr_q); +void rfc_sg_stop(); + +/* + * PM DECLARATIONS + **************************************************************************************** + */ + +uint32_t rfc_pm_start(uint32_t insel,int32_t freq_cw,uint32_t acclen,uint32_t rshiftlen, + int32_t *raw_acc_i,int32_t *raw_acc_q); +void rfc_pm_stop(); + +/* + * HWCTRL DECLARATIONS + **************************************************************************************** + */ +void rfc_hwctrl_txrfgain(uint8_t hwctrl_on); +void rfc_hwctrl_rxgain(uint8_t hwctrl_on); +void rfc_hwctrl_txdvga(uint8_t hwctrl_on); +void rfc_hwctrl_calparam(uint8_t hwctrl_on); + +/* + * FSM DECLARATIONS + **************************************************************************************** + */ + +void rfc_fsm_force(uint8_t state); +void rfc_rc_fsm_force(uint8_t state); // :1313:6 +/* + * COEX DECLARATIONS + **************************************************************************************** + */ +void rfc_coex_force_to(uint32_t force_enable, uint32_t bbmode); + +void rfc_dump(); + +void rfc_apply_tx_power_offset(uint8_t channel, int8_t *power_offset); // :1643:6 +void rfc_config_channel(uint32_t channel_freq); +void rfc_apply_tx_dvga(int8_t *dvga_qdb); +void rfc_apply_tx_dvga_offset(int8_t offset_qdb); // :1519:6 + +void rfc_config_power(uint32_t mode, uint32_t tbb_boost, uint32_t tbb, uint32_t tmx); +_Bool rfc_config_power_ble(int32_t pwr_dbm); +void rfc_config_bandwidth(uint32_t mode); + +struct rfc_status_tag { + uint32_t pkdet_out_raw:1; // +0 + uint32_t dig_xtal_clk_dbg:1; // +0 + uint32_t clk_ble_16m_dbg:1; // +0 + uint32_t clk_rc_dbg0:1; // +0 + uint32_t clk_adcpow_dbg:1; // +0 + uint32_t clk_fetx_dbg:1; // +0 + uint32_t clk_ferx_dbg:1; // +0 + uint32_t clkpll_postdiv_outclk_dbg:1; // +0 + uint32_t clk_soc_480m_dbg:1; // +0 + uint32_t clk_soc_240m_dbg:1; // +0 + uint32_t clk_soc_192m_dbg:1; // +0 + uint32_t clk_soc_160m_dbg:1; // +0 + uint32_t clk_soc_120m_dbg:1; // +0 + uint32_t clk_soc_96m_dbg:1; // +0 + uint32_t clk_soc_80m_dbg:1; // +0 + uint32_t clk_soc_48m_dbg:1; // +0 + uint32_t clk_soc_32m_dbg:1; // +0 + uint32_t pad_pkdet_out:1; // +0 + uint32_t pad_agc_ctrl:10; // +0 + uint32_t rf_pkdet_rst_hw:1; // +0 + uint32_t rf_cbw_wifi:2; // +0 + uint32_t lo_unlocked:1; // +0 + uint32_t fsm_pu_txbuf:1; // +4 + uint32_t fsm_pu_rxbuf:1; // +4 + uint32_t fsm_pu_tosdac:1; // +4 + uint32_t fsm_pu_dac:1; // +4 + uint32_t fsm_trsw_en:1; // +4 + uint32_t fsm_pu_adc:1; // +4 + uint32_t fsm_pu_pkdet:1; // +4 + uint32_t fsm_pu_rbb:1; // +4 + uint32_t fsm_pu_rmx:1; // +4 + uint32_t fsm_pu_rmxgm:1; // +4 + uint32_t fsm_pu_lna:1; // +4 + uint32_t clk_rc_dbg2:1; // +4 + uint32_t rf_lna_ind_hw:4; // +4 + uint32_t rf_rbb_ind_hw:4; // +4 + uint32_t rf_tx_pow_lvl_hw:4; // +4 + uint32_t rf_rc_lo_rdy:1; // +4 + uint32_t rf_fsm_state:3; // +4 + uint32_t rf_rc_state:3; // +4 + uint32_t clk_rc_dbg:1; // +4 +}; // :84:8 + + +#endif \ No newline at end of file diff --git a/src/bl602_wifi/phyif_utils.h b/src/include/bl602_wifi/phyif/phyif_utils.h similarity index 100% rename from src/bl602_wifi/phyif_utils.h rename to src/include/bl602_wifi/phyif/phyif_utils.h diff --git a/src/bl602_wifi/utils.h b/src/include/utils.h similarity index 90% rename from src/bl602_wifi/utils.h rename to src/include/utils.h index 932abb2..3cbf09b 100644 --- a/src/bl602_wifi/utils.h +++ b/src/include/utils.h @@ -6,6 +6,6 @@ int puts(char *s); int printf(char *fmt,...); void* memset(void *, int, long unsigned int); void* memcpy(void*, const void*, unsigned int); -void wait_us(uint32_t us); void BL602_Delay_US(uint32_t cnt); +void BL602_Delay_MS(uint32_t cnt); #endif \ No newline at end of file From 50d981a08c6b8f0248e4d295ce08d7c9aec9fdb4 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 03:34:44 -0600 Subject: [PATCH 061/148] add clang build option --- CMakeLists.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index be544e1..7840dc0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,6 +4,15 @@ set(CMAKE_SYSTEM_PROCESSOR riscv) SET(CMAKE_CROSSCOMPILING 1) set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") +option(USE_CLANG "build application with clang" OFF) +if(USE_CLANG) + set(CMAKE_C_COMPILER clang) + set(CMAKE_C_COMPILER_TARGET "riscv32-unknown-elf") + set(CMAKE_CXX_COMPILER clang++) + set(CMAKE_CXX_COMPILER_TARGET "riscv32-unknown-elf") + set(CMAKE_TOOLCHAIN_PREFIX llvm-) +endif() + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -march=rv32imfc -mabi=ilp32f") set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=c11 -march=rv32imfc -mabi=ilp32f") project(bl602_re VERSION 0.1.0) From c126e6a456e9e5763343457f5cb664f8e4524304 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 03:34:53 -0600 Subject: [PATCH 062/148] add github action --- .github/workflows/action-libbl602_wifi.yml | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 .github/workflows/action-libbl602_wifi.yml diff --git a/.github/workflows/action-libbl602_wifi.yml b/.github/workflows/action-libbl602_wifi.yml new file mode 100644 index 0000000..f367fbd --- /dev/null +++ b/.github/workflows/action-libbl602_wifi.yml @@ -0,0 +1,20 @@ +name: Compile libbl602_wifi +on: [push] +jobs: + build: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: Set up Clang + uses: egor-tensin/setup-clang@v1 + with: + version: latest + platform: x64 + - name: Build libbl602_wifi + run: mkdir build && cmake -DUSE_CLANG=ON .. && make -j + - name: Archive artifacts + uses: actions/upload-artifact@v2 + with: + name: libbl602_wifi + path: build/src/libbl602_wifi.a + \ No newline at end of file From e85555d92b72b3e75952739f5a90532d4c33fcac Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 03:36:30 -0600 Subject: [PATCH 063/148] update command --- .github/workflows/action-libbl602_wifi.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/action-libbl602_wifi.yml b/.github/workflows/action-libbl602_wifi.yml index f367fbd..c393cc0 100644 --- a/.github/workflows/action-libbl602_wifi.yml +++ b/.github/workflows/action-libbl602_wifi.yml @@ -11,7 +11,7 @@ jobs: version: latest platform: x64 - name: Build libbl602_wifi - run: mkdir build && cmake -DUSE_CLANG=ON .. && make -j + run: mkdir build && cd build && cmake -DUSE_CLANG=ON .. && make -j - name: Archive artifacts uses: actions/upload-artifact@v2 with: From d140eeec841c9df80c3d86033e9f8b4f6d71cab1 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 03:38:18 -0600 Subject: [PATCH 064/148] update artifact path --- .github/workflows/action-libbl602_wifi.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/action-libbl602_wifi.yml b/.github/workflows/action-libbl602_wifi.yml index c393cc0..cc66350 100644 --- a/.github/workflows/action-libbl602_wifi.yml +++ b/.github/workflows/action-libbl602_wifi.yml @@ -16,5 +16,5 @@ jobs: uses: actions/upload-artifact@v2 with: name: libbl602_wifi - path: build/src/libbl602_wifi.a + path: src/libbl602_wifi.a \ No newline at end of file From babe32bdb8bf306d0fc296cc8f92fd999be82b9f Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 03:42:18 -0600 Subject: [PATCH 065/148] update path --- .github/workflows/action-libbl602_wifi.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/action-libbl602_wifi.yml b/.github/workflows/action-libbl602_wifi.yml index cc66350..f5d80ef 100644 --- a/.github/workflows/action-libbl602_wifi.yml +++ b/.github/workflows/action-libbl602_wifi.yml @@ -11,10 +11,10 @@ jobs: version: latest platform: x64 - name: Build libbl602_wifi - run: mkdir build && cd build && cmake -DUSE_CLANG=ON .. && make -j + run: mkdir build && cd build && cmake -DUSE_CLANG=ON .. && make -j && cd .. - name: Archive artifacts uses: actions/upload-artifact@v2 with: name: libbl602_wifi - path: src/libbl602_wifi.a + path: build/src/bl602_wifi/libbl602_wifi.a \ No newline at end of file From 09b791626fbce34a5615c02eb456a4945a24e681 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 03:58:09 -0600 Subject: [PATCH 066/148] add ble --- tools/inline_annotate.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/inline_annotate.py b/tools/inline_annotate.py index e3be69f..84c8bc7 100644 --- a/tools/inline_annotate.py +++ b/tools/inline_annotate.py @@ -57,8 +57,8 @@ def peek_line(f): root = CU.get_top_DIE() is_ble = 'components/network/ble/blecontroller' in root.get_full_path() is_wifi = 'bl602/bl602_wifi/' in root.get_full_path() - if ('ble' in path and not is_ble) or ('wifi' in path and not is_wifi): - continue + #if ('ble' in path and not is_ble) or ('wifi' in path and not is_wifi): + # continue proprietary.append(root) subroutines = [] From 28e501e17ace3d340c52ffcf7863da56dbc6674b Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Sun, 19 Dec 2021 04:11:24 -0600 Subject: [PATCH 067/148] update readme --- README.adoc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/README.adoc b/README.adoc index ddf4a9b..11fa68c 100644 --- a/README.adoc +++ b/README.adoc @@ -45,6 +45,17 @@ Whatever you do, do not insert proprietary `Copyright (C) RivieraWaves` code in RivieraWaves code is known to be easily available on GitHub with simple searches, but avoid looking at it, unless you wish to forfeit your right to directly contribute code here. ==== +== BL602 wifi +I'm working on the reverse engineering of the bl602 wifi. + +The source code is located in `src/` instead of `components/**`. + +Using `cmake` to build the wifi module and it will automatically add other components +from the original `libbl602_wifi.a` and create a new one. + +This should generate a usable `libbl602_wifi.a` to link against other bl602 components. +But, I'm still working on this and it hasn't been tested yet. + == Resources * https://github.com/pine64/bl602-docs[Pine64 SDK fork's documentation], if you figure something out that's documentation-worthy, please update that documentation. From c5250a09d0bf9d1d0c17f898c55bb82632ae0802 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Tue, 21 Dec 2021 02:26:46 -0600 Subject: [PATCH 068/148] fix dup symbols --- src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c | 2 ++ src/include/bl602_wifi/phy_rf/phy_bl602.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c b/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c index 8d4173e..6a2b927 100644 --- a/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c @@ -18,6 +18,8 @@ static int8_t rxgain_offset_vs_temperature; // :79:15 static int8_t poweroffset[14]; // :80:15 +struct phy_env_tag phy_env[1]; // :75:20 + void phy_config_rxgain(int offset) { if (rxgain_offset_vs_temperature != offset) { rxgain_offset_vs_temperature = (int8_t) offset; diff --git a/src/include/bl602_wifi/phy_rf/phy_bl602.h b/src/include/bl602_wifi/phy_rf/phy_bl602.h index d74e62a..8f31b41 100644 --- a/src/include/bl602_wifi/phy_rf/phy_bl602.h +++ b/src/include/bl602_wifi/phy_rf/phy_bl602.h @@ -31,7 +31,6 @@ struct phy_env_tag { uint8_t band; uint8_t chnl_type; }; // :54:8 -struct phy_env_tag phy_env[1]; // :75:20 void phy_config_rxgain(int offset); uint8_t phy_get_mac_freq(); From d0fa9a1aea9d07ecc88e6d9e51eb62b5290f2982 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Tue, 21 Dec 2021 02:26:54 -0600 Subject: [PATCH 069/148] add rf_dump_status --- src/bl602_wifi/driver/phy/phy_rf/rf.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/bl602_wifi/driver/phy/phy_rf/rf.c b/src/bl602_wifi/driver/phy/phy_rf/rf.c index cc2d079..3ef069f 100644 --- a/src/bl602_wifi/driver/phy/phy_rf/rf.c +++ b/src/bl602_wifi/driver/phy/phy_rf/rf.c @@ -18,3 +18,7 @@ void rf_init(void) { void rf_lo_isr(void) { return ; } + +void rf_dump_status(void) { + return ; +} \ No newline at end of file From 5b994a03ed104ed9244d1c415e0ee85144b2350a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 22 Dec 2021 19:03:33 -0600 Subject: [PATCH 070/148] fix volatile attr in the pointer --- script/reglib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/script/reglib.py b/script/reglib.py index 7db82d2..ff0aeee 100755 --- a/script/reglib.py +++ b/script/reglib.py @@ -226,7 +226,7 @@ def genHeader(self): '\t};', "}" + f' {self.name}_regs;', f'#define {self.name.upper()}_BASE {hex(self.base)}', - f'#define {self.name.upper()} (({self.name}_regs* volatile)({self.name.upper()}_BASE))' + f'#define {self.name.upper()} ((volatile {self.name}_regs*)({self.name.upper()}_BASE))' ]) return s From d9ccd5d4312be1e7ec68781d832aa82897364ef2 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 22 Dec 2021 19:09:41 -0600 Subject: [PATCH 071/148] modify retry logic --- src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c index 1d42423..eb71747 100644 --- a/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c +++ b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c @@ -188,10 +188,11 @@ void rf_pri_fcal(void) { uint16_t cw = 0x80; while (1) { for (int j = 6; j >= 0; j--) { - if (rf_pri_fcal_meas(cw) < c0) { + int cnt = rf_pri_fcal_meas(cw); + if (cnt < c0) { cw -= (1 << j); } else { - if (rf_pri_fcal_meas(cw) > c1) { + if (cnt > c1) { cw += (1 << j); } else break; } @@ -201,7 +202,7 @@ void rf_pri_fcal(void) { break; printf("Unexpected cw %ld\r\n", cw); - + cw = 0x80; /// reset RF->sdm1.lo_sdm_rstb = 0; RF->fbdv.lo_fbdv_rst = 1; @@ -210,10 +211,8 @@ void rf_pri_fcal(void) { RF->fbdv.lo_fbdv_rst = 0; BL602_Delay_US(0x32); } - cw++; channel_cnt_opt_table[0] = rf_pri_fcal_meas(cw); - for (int i = 1; i < 40; i++) { uint16_t cnt = rf_pri_fcal_meas(cw-i); channel_cnt_opt_table[i] = cnt; @@ -222,7 +221,7 @@ void rf_pri_fcal(void) { for (int i = 0, j = 0; i < 21; i++) { while (channel_cnt_opt_table[j] < channel_cnt_table[i]) j++; - channel_cw_table[i] = cw - (j - 1); /// hmmm what if j = 0?\ + channel_cw_table[i] = cw - (j - 1); /// hmmm what if j = 0? /// or it can't because cw was + 1.. if (j > 0) j--; } @@ -268,6 +267,7 @@ void rf_pri_start_txdfe() { static void rf_pri_config_channel(uint32_t channel_index) { // sdm = sigma-delta modulator ? + printf("lo_vco_freq[%d] = %d, %d\n", channel_index, rf_calib_data->lo[channel_index].fcal, rf_calib_data->lo[channel_index].acal); PACK(RF->vco1, vco1) { vco1.lo_vco_freq_cw = rf_calib_data->lo[channel_index].fcal; vco1.lo_vco_idac_cw = rf_calib_data->lo[channel_index].acal; From 65ad9699dce6e9f8b2427b8331971efb924de64a Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 22 Dec 2021 19:10:47 -0600 Subject: [PATCH 072/148] change volatile order in the type --- src/include/phy/agc.h | 2 +- src/include/phy/agcram.h | 2 +- src/include/phy/bz_phy.h | 2 +- src/include/phy/bz_phy_agc.h | 2 +- src/include/phy/dma.h | 2 +- src/include/phy/ipc.h | 2 +- src/include/phy/mac_core.h | 2 +- src/include/phy/mac_pl.h | 2 +- src/include/phy/mdm.h | 2 +- src/include/phy/sysctrl.h | 2 +- src/include/phy/sysctrl92.h | 2 +- src/include/soc/AON.h | 2 +- src/include/soc/HBN.h | 2 +- src/include/soc/cci.h | 2 +- src/include/soc/cks.h | 2 +- src/include/soc/dma.h | 2 +- src/include/soc/ef_ctrl.h | 2 +- src/include/soc/ef_data_0.h | 2 +- src/include/soc/ef_data_1.h | 2 +- src/include/soc/glb.h | 2 +- src/include/soc/gpip.h | 2 +- src/include/soc/i2c.h | 2 +- src/include/soc/ir.h | 2 +- src/include/soc/l1c.h | 2 +- src/include/soc/pds.h | 2 +- src/include/soc/pwm.h | 2 +- src/include/soc/rf.h | 2 +- src/include/soc/sec_dbg.h | 2 +- src/include/soc/sec_eng.h | 2 +- src/include/soc/sf_ctrl.h | 2 +- src/include/soc/spi.h | 2 +- src/include/soc/timer.h | 2 +- src/include/soc/tzc_nsec.h | 2 +- src/include/soc/tzc_sec.h | 2 +- src/include/soc/uart.h | 2 +- 35 files changed, 35 insertions(+), 35 deletions(-) diff --git a/src/include/phy/agc.h b/src/include/phy/agc.h index a58e169..1fd0198 100644 --- a/src/include/phy/agc.h +++ b/src/include/phy/agc.h @@ -428,4 +428,4 @@ typedef union { }; } agc_regs; #define AGC_BASE 0x44c0b000 -#define AGC ((agc_regs* volatile)(AGC_BASE)) \ No newline at end of file +#define AGC ((volatile agc_regs*)(AGC_BASE)) \ No newline at end of file diff --git a/src/include/phy/agcram.h b/src/include/phy/agcram.h index e32c3c9..284b96a 100644 --- a/src/include/phy/agcram.h +++ b/src/include/phy/agcram.h @@ -6,4 +6,4 @@ typedef union { }; } agcram_regs; #define AGCRAM_BASE 0x54c0a000 -#define AGCRAM ((agcram_regs* volatile)(AGCRAM_BASE)) \ No newline at end of file +#define AGCRAM ((volatile agcram_regs*)(AGCRAM_BASE)) \ No newline at end of file diff --git a/src/include/phy/bz_phy.h b/src/include/phy/bz_phy.h index 4e30a52..f28b8b7 100644 --- a/src/include/phy/bz_phy.h +++ b/src/include/phy/bz_phy.h @@ -883,4 +883,4 @@ typedef union { }; } bz_phy_regs; #define BZ_PHY_BASE 0x40002800 -#define BZ_PHY ((bz_phy_regs* volatile)(BZ_PHY_BASE)) \ No newline at end of file +#define BZ_PHY ((volatile bz_phy_regs*)(BZ_PHY_BASE)) \ No newline at end of file diff --git a/src/include/phy/bz_phy_agc.h b/src/include/phy/bz_phy_agc.h index ee4702f..6a41883 100644 --- a/src/include/phy/bz_phy_agc.h +++ b/src/include/phy/bz_phy_agc.h @@ -583,4 +583,4 @@ typedef union { }; } bz_phy_agc_regs; #define BZ_PHY_AGC_BASE 0x40002c00 -#define BZ_PHY_AGC ((bz_phy_agc_regs* volatile)(BZ_PHY_AGC_BASE)) \ No newline at end of file +#define BZ_PHY_AGC ((volatile bz_phy_agc_regs*)(BZ_PHY_AGC_BASE)) \ No newline at end of file diff --git a/src/include/phy/dma.h b/src/include/phy/dma.h index 9c4e2fd..0cd255b 100644 --- a/src/include/phy/dma.h +++ b/src/include/phy/dma.h @@ -88,4 +88,4 @@ typedef union { }; } dma_regs; #define DMA_BASE 0x44a00000 -#define DMA ((dma_regs* volatile)(DMA_BASE)) \ No newline at end of file +#define DMA ((volatile dma_regs*)(DMA_BASE)) \ No newline at end of file diff --git a/src/include/phy/ipc.h b/src/include/phy/ipc.h index c20a865..176b7bd 100644 --- a/src/include/phy/ipc.h +++ b/src/include/phy/ipc.h @@ -49,4 +49,4 @@ typedef union { }; } ipc_regs; #define IPC_BASE 0x44800000 -#define IPC ((ipc_regs* volatile)(IPC_BASE)) \ No newline at end of file +#define IPC ((volatile ipc_regs*)(IPC_BASE)) \ No newline at end of file diff --git a/src/include/phy/mac_core.h b/src/include/phy/mac_core.h index f869d75..50ed2e6 100644 --- a/src/include/phy/mac_core.h +++ b/src/include/phy/mac_core.h @@ -825,4 +825,4 @@ typedef union { }; } mac_core_regs; #define MAC_CORE_BASE 0x44b00000 -#define MAC_CORE ((mac_core_regs* volatile)(MAC_CORE_BASE)) \ No newline at end of file +#define MAC_CORE ((volatile mac_core_regs*)(MAC_CORE_BASE)) \ No newline at end of file diff --git a/src/include/phy/mac_pl.h b/src/include/phy/mac_pl.h index 918266a..742907f 100644 --- a/src/include/phy/mac_pl.h +++ b/src/include/phy/mac_pl.h @@ -867,4 +867,4 @@ typedef union { }; } mac_pl_regs; #define MAC_PL_BASE 0x44b08000 -#define MAC_PL ((mac_pl_regs* volatile)(MAC_PL_BASE)) \ No newline at end of file +#define MAC_PL ((volatile mac_pl_regs*)(MAC_PL_BASE)) \ No newline at end of file diff --git a/src/include/phy/mdm.h b/src/include/phy/mdm.h index 1ab9362..ee0f605 100644 --- a/src/include/phy/mdm.h +++ b/src/include/phy/mdm.h @@ -162,4 +162,4 @@ typedef union { }; } mdm_regs; #define MDM_BASE 0x44c00000 -#define MDM ((mdm_regs* volatile)(MDM_BASE)) \ No newline at end of file +#define MDM ((volatile mdm_regs*)(MDM_BASE)) \ No newline at end of file diff --git a/src/include/phy/sysctrl.h b/src/include/phy/sysctrl.h index 8f186ab..63db1a6 100644 --- a/src/include/phy/sysctrl.h +++ b/src/include/phy/sysctrl.h @@ -32,4 +32,4 @@ typedef union { }; } sysctrl_regs; #define SYSCTRL_BASE 0x44900000 -#define SYSCTRL ((sysctrl_regs* volatile)(SYSCTRL_BASE)) \ No newline at end of file +#define SYSCTRL ((volatile sysctrl_regs*)(SYSCTRL_BASE)) \ No newline at end of file diff --git a/src/include/phy/sysctrl92.h b/src/include/phy/sysctrl92.h index a137b6b..00c7961 100644 --- a/src/include/phy/sysctrl92.h +++ b/src/include/phy/sysctrl92.h @@ -7,4 +7,4 @@ typedef union { }; } sysctrl92_regs; #define SYSCTRL92_BASE 0x44920000 -#define SYSCTRL92 ((sysctrl92_regs* volatile)(SYSCTRL92_BASE)) \ No newline at end of file +#define SYSCTRL92 ((volatile sysctrl92_regs*)(SYSCTRL92_BASE)) \ No newline at end of file diff --git a/src/include/soc/AON.h b/src/include/soc/AON.h index 4089f3b..f3d842a 100644 --- a/src/include/soc/AON.h +++ b/src/include/soc/AON.h @@ -394,4 +394,4 @@ typedef union { }; } AON_regs; #define AON_BASE 0x4000f000 -#define AON ((AON_regs* volatile)(AON_BASE)) \ No newline at end of file +#define AON ((volatile AON_regs*)(AON_BASE)) \ No newline at end of file diff --git a/src/include/soc/HBN.h b/src/include/soc/HBN.h index 819f0e5..5b0fa88 100644 --- a/src/include/soc/HBN.h +++ b/src/include/soc/HBN.h @@ -206,4 +206,4 @@ typedef union { }; } HBN_regs; #define HBN_BASE 0x4000f000 -#define HBN ((HBN_regs* volatile)(HBN_BASE)) \ No newline at end of file +#define HBN ((volatile HBN_regs*)(HBN_BASE)) \ No newline at end of file diff --git a/src/include/soc/cci.h b/src/include/soc/cci.h index d9d4def..05448b0 100644 --- a/src/include/soc/cci.h +++ b/src/include/soc/cci.h @@ -47,4 +47,4 @@ typedef union { }; } cci_regs; #define CCI_BASE 0x40008000 -#define CCI ((cci_regs* volatile)(CCI_BASE)) \ No newline at end of file +#define CCI ((volatile cci_regs*)(CCI_BASE)) \ No newline at end of file diff --git a/src/include/soc/cks.h b/src/include/soc/cks.h index 474e844..8f58ea1 100644 --- a/src/include/soc/cks.h +++ b/src/include/soc/cks.h @@ -27,4 +27,4 @@ typedef union { }; } cks_regs; #define CKS_BASE 0x4000a000 -#define CKS ((cks_regs* volatile)(CKS_BASE)) \ No newline at end of file +#define CKS ((volatile cks_regs*)(CKS_BASE)) \ No newline at end of file diff --git a/src/include/soc/dma.h b/src/include/soc/dma.h index 8b88f88..d5cd609 100644 --- a/src/include/soc/dma.h +++ b/src/include/soc/dma.h @@ -301,4 +301,4 @@ typedef union { }; } dma_regs; #define DMA_BASE 0x4000c000 -#define DMA ((dma_regs* volatile)(DMA_BASE)) \ No newline at end of file +#define DMA ((volatile dma_regs*)(DMA_BASE)) \ No newline at end of file diff --git a/src/include/soc/ef_ctrl.h b/src/include/soc/ef_ctrl.h index b2ef074..c316c96 100644 --- a/src/include/soc/ef_ctrl.h +++ b/src/include/soc/ef_ctrl.h @@ -187,4 +187,4 @@ typedef union { }; } ef_ctrl_regs; #define EF_CTRL_BASE 0x40007000 -#define EF_CTRL ((ef_ctrl_regs* volatile)(EF_CTRL_BASE)) \ No newline at end of file +#define EF_CTRL ((volatile ef_ctrl_regs*)(EF_CTRL_BASE)) \ No newline at end of file diff --git a/src/include/soc/ef_data_0.h b/src/include/soc/ef_data_0.h index 612e008..6e4c15f 100644 --- a/src/include/soc/ef_data_0.h +++ b/src/include/soc/ef_data_0.h @@ -235,4 +235,4 @@ typedef union { }; } ef_data_0_regs; #define EF_DATA_0_BASE 0x40007000 -#define EF_DATA_0 ((ef_data_0_regs* volatile)(EF_DATA_0_BASE)) \ No newline at end of file +#define EF_DATA_0 ((volatile ef_data_0_regs*)(EF_DATA_0_BASE)) \ No newline at end of file diff --git a/src/include/soc/ef_data_1.h b/src/include/soc/ef_data_1.h index 3667e6a..41c0a6b 100644 --- a/src/include/soc/ef_data_1.h +++ b/src/include/soc/ef_data_1.h @@ -127,4 +127,4 @@ typedef union { }; } ef_data_1_regs; #define EF_DATA_1_BASE 0x40007000 -#define EF_DATA_1 ((ef_data_1_regs* volatile)(EF_DATA_1_BASE)) \ No newline at end of file +#define EF_DATA_1 ((volatile ef_data_1_regs*)(EF_DATA_1_BASE)) \ No newline at end of file diff --git a/src/include/soc/glb.h b/src/include/soc/glb.h index 6fb5e34..7a2a5f0 100644 --- a/src/include/soc/glb.h +++ b/src/include/soc/glb.h @@ -965,4 +965,4 @@ typedef union { }; } glb_regs; #define GLB_BASE 0x40000000 -#define GLB ((glb_regs* volatile)(GLB_BASE)) \ No newline at end of file +#define GLB ((volatile glb_regs*)(GLB_BASE)) \ No newline at end of file diff --git a/src/include/soc/gpip.h b/src/include/soc/gpip.h index ae4f5a4..8e173bd 100644 --- a/src/include/soc/gpip.h +++ b/src/include/soc/gpip.h @@ -79,4 +79,4 @@ typedef union { }; } gpip_regs; #define GPIP_BASE 0x40002000 -#define GPIP ((gpip_regs* volatile)(GPIP_BASE)) \ No newline at end of file +#define GPIP ((volatile gpip_regs*)(GPIP_BASE)) \ No newline at end of file diff --git a/src/include/soc/i2c.h b/src/include/soc/i2c.h index 805c66b..241f783 100644 --- a/src/include/soc/i2c.h +++ b/src/include/soc/i2c.h @@ -139,4 +139,4 @@ typedef union { }; } i2c_regs; #define I2C_BASE 0x4000a300 -#define I2C ((i2c_regs* volatile)(I2C_BASE)) \ No newline at end of file +#define I2C ((volatile i2c_regs*)(I2C_BASE)) \ No newline at end of file diff --git a/src/include/soc/ir.h b/src/include/soc/ir.h index c1b3a7f..283c73f 100644 --- a/src/include/soc/ir.h +++ b/src/include/soc/ir.h @@ -192,4 +192,4 @@ typedef union { }; } ir_regs; #define IR_BASE 0x4000a600 -#define IR ((ir_regs* volatile)(IR_BASE)) \ No newline at end of file +#define IR ((volatile ir_regs*)(IR_BASE)) \ No newline at end of file diff --git a/src/include/soc/l1c.h b/src/include/soc/l1c.h index ce77cad..694143d 100644 --- a/src/include/soc/l1c.h +++ b/src/include/soc/l1c.h @@ -81,4 +81,4 @@ typedef union { }; } l1c_regs; #define L1C_BASE 0x40009000 -#define L1C ((l1c_regs* volatile)(L1C_BASE)) \ No newline at end of file +#define L1C ((volatile l1c_regs*)(L1C_BASE)) \ No newline at end of file diff --git a/src/include/soc/pds.h b/src/include/soc/pds.h index c0e6079..8b726ce 100644 --- a/src/include/soc/pds.h +++ b/src/include/soc/pds.h @@ -281,4 +281,4 @@ typedef union { }; } pds_regs; #define PDS_BASE 0x4000e000 -#define PDS ((pds_regs* volatile)(PDS_BASE)) \ No newline at end of file +#define PDS ((volatile pds_regs*)(PDS_BASE)) \ No newline at end of file diff --git a/src/include/soc/pwm.h b/src/include/soc/pwm.h index 14c358d..a2f94b8 100644 --- a/src/include/soc/pwm.h +++ b/src/include/soc/pwm.h @@ -264,4 +264,4 @@ typedef union { }; } pwm_regs; #define PWM_BASE 0x4000a400 -#define PWM ((pwm_regs* volatile)(PWM_BASE)) \ No newline at end of file +#define PWM ((volatile pwm_regs*)(PWM_BASE)) \ No newline at end of file diff --git a/src/include/soc/rf.h b/src/include/soc/rf.h index ee0c812..ac308cb 100644 --- a/src/include/soc/rf.h +++ b/src/include/soc/rf.h @@ -1931,4 +1931,4 @@ typedef union { }; } rf_regs; #define RF_BASE 0x40001000 -#define RF ((rf_regs* volatile)(RF_BASE)) \ No newline at end of file +#define RF ((volatile rf_regs*)(RF_BASE)) \ No newline at end of file diff --git a/src/include/soc/sec_dbg.h b/src/include/soc/sec_dbg.h index 8687274..b87c44c 100644 --- a/src/include/soc/sec_dbg.h +++ b/src/include/soc/sec_dbg.h @@ -59,4 +59,4 @@ typedef union { }; } sec_dbg_regs; #define SEC_DBG_BASE 0x40003000 -#define SEC_DBG ((sec_dbg_regs* volatile)(SEC_DBG_BASE)) \ No newline at end of file +#define SEC_DBG ((volatile sec_dbg_regs*)(SEC_DBG_BASE)) \ No newline at end of file diff --git a/src/include/soc/sec_eng.h b/src/include/soc/sec_eng.h index be41930..714ceed 100644 --- a/src/include/soc/sec_eng.h +++ b/src/include/soc/sec_eng.h @@ -621,4 +621,4 @@ typedef union { }; } sec_eng_regs; #define SEC_ENG_BASE 0x40004000 -#define SEC_ENG ((sec_eng_regs* volatile)(SEC_ENG_BASE)) \ No newline at end of file +#define SEC_ENG ((volatile sec_eng_regs*)(SEC_ENG_BASE)) \ No newline at end of file diff --git a/src/include/soc/sf_ctrl.h b/src/include/soc/sf_ctrl.h index 5eaec5c..d35397c 100644 --- a/src/include/soc/sf_ctrl.h +++ b/src/include/soc/sf_ctrl.h @@ -664,4 +664,4 @@ typedef union { }; } sf_ctrl_regs; #define SF_CTRL_BASE 0x4000b000 -#define SF_CTRL ((sf_ctrl_regs* volatile)(SF_CTRL_BASE)) \ No newline at end of file +#define SF_CTRL ((volatile sf_ctrl_regs*)(SF_CTRL_BASE)) \ No newline at end of file diff --git a/src/include/soc/spi.h b/src/include/soc/spi.h index 77d6650..af70f94 100644 --- a/src/include/soc/spi.h +++ b/src/include/soc/spi.h @@ -136,4 +136,4 @@ typedef union { }; } spi_regs; #define SPI_BASE 0x4000a200 -#define SPI ((spi_regs* volatile)(SPI_BASE)) \ No newline at end of file +#define SPI ((volatile spi_regs*)(SPI_BASE)) \ No newline at end of file diff --git a/src/include/soc/timer.h b/src/include/soc/timer.h index bf6d225..88f74d9 100644 --- a/src/include/soc/timer.h +++ b/src/include/soc/timer.h @@ -281,4 +281,4 @@ typedef union { }; } timer_regs; #define TIMER_BASE 0x4000a500 -#define TIMER ((timer_regs* volatile)(TIMER_BASE)) \ No newline at end of file +#define TIMER ((volatile timer_regs*)(TIMER_BASE)) \ No newline at end of file diff --git a/src/include/soc/tzc_nsec.h b/src/include/soc/tzc_nsec.h index c82efc8..a7bd73c 100644 --- a/src/include/soc/tzc_nsec.h +++ b/src/include/soc/tzc_nsec.h @@ -59,4 +59,4 @@ typedef union { }; } tzc_nsec_regs; #define TZC_NSEC_BASE 0x40006000 -#define TZC_NSEC ((tzc_nsec_regs* volatile)(TZC_NSEC_BASE)) \ No newline at end of file +#define TZC_NSEC ((volatile tzc_nsec_regs*)(TZC_NSEC_BASE)) \ No newline at end of file diff --git a/src/include/soc/tzc_sec.h b/src/include/soc/tzc_sec.h index 90582e2..07e3e79 100644 --- a/src/include/soc/tzc_sec.h +++ b/src/include/soc/tzc_sec.h @@ -59,4 +59,4 @@ typedef union { }; } tzc_sec_regs; #define TZC_SEC_BASE 0x40005000 -#define TZC_SEC ((tzc_sec_regs* volatile)(TZC_SEC_BASE)) \ No newline at end of file +#define TZC_SEC ((volatile tzc_sec_regs*)(TZC_SEC_BASE)) \ No newline at end of file diff --git a/src/include/soc/uart.h b/src/include/soc/uart.h index c8d2e76..47c0ef9 100644 --- a/src/include/soc/uart.h +++ b/src/include/soc/uart.h @@ -189,4 +189,4 @@ typedef union { }; } uart_regs; #define UART_BASE 0x4000a000 -#define UART ((uart_regs* volatile)(UART_BASE)) \ No newline at end of file +#define UART ((volatile uart_regs*)(UART_BASE)) \ No newline at end of file From 9803c2081adfb640eda10cd18d8f937a4f6d286f Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Wed, 22 Dec 2021 19:11:03 -0600 Subject: [PATCH 073/148] add some ignores --- .gitignore | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 5e4a051..66dc929 100644 --- a/.gitignore +++ b/.gitignore @@ -305,4 +305,6 @@ tags [._]*.un~ # End of https://www.toptal.com/developers/gitignore/api/emacs,vim,pycharm+all,python -/build +/build* +.vscode/ +*.cache \ No newline at end of file From d65e629086ff1c7f0697a9e53a49281d0746f859 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:20:19 -0600 Subject: [PATCH 074/148] move macro to global --- src/{bl602_wifi/driver/phy/phy_rf => include}/macro.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename src/{bl602_wifi/driver/phy/phy_rf => include}/macro.h (94%) diff --git a/src/bl602_wifi/driver/phy/phy_rf/macro.h b/src/include/macro.h similarity index 94% rename from src/bl602_wifi/driver/phy/phy_rf/macro.h rename to src/include/macro.h index 2b706f6..6857eff 100644 --- a/src/bl602_wifi/driver/phy/phy_rf/macro.h +++ b/src/include/macro.h @@ -43,5 +43,5 @@ #define _APPLY_NEXT() APPLY_NEXT #define PACK(var, name) for (int tip = 1; tip;) for (__typeof__ (var) name = var; tip; tip = 0, var = name) - +#define STATIC_ASSERT(COND,MSG) typedef char static_assertion_##MSG[(COND)?1:-1] #endif \ No newline at end of file From 05d666f2c93fed3381465523725d7fd23c77dcb3 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:20:30 -0600 Subject: [PATCH 075/148] adding sysctrl and ipc --- src/bl602_wifi/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/bl602_wifi/CMakeLists.txt b/src/bl602_wifi/CMakeLists.txt index 2dbb21e..941d82f 100644 --- a/src/bl602_wifi/CMakeLists.txt +++ b/src/bl602_wifi/CMakeLists.txt @@ -1,4 +1,6 @@ init_bl602module("bl602_wifi") add_bl602module("driver/phy/phy_rf") add_bl602module("driver/phyif") +add_bl602module("driver/sysctrl") +add_bl602module("driver/ipc") end_bl602module() \ No newline at end of file From becea0d54ab821453438864f4c255b83e476cb98 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:20:50 -0600 Subject: [PATCH 076/148] update IPC regs --- script/manualext.py | 21 +++- src/include/phy/ipc.h | 89 ++++++++------ src/svd/ipc.svd | 272 ++++++++++++++++++++++++++++++++++-------- 3 files changed, 294 insertions(+), 88 deletions(-) diff --git a/script/manualext.py b/script/manualext.py index 601467a..56cff04 100755 --- a/script/manualext.py +++ b/script/manualext.py @@ -432,7 +432,26 @@ def getregs(fname, pattern='name'): peris['ipc'] = Peripheral(peripheral('ipc', 0x44800000, 0x1000)) for code, offset in getregs("../components/bl602/bl602_wifidrv/bl60x_wifi_driver/reg_ipc_app.h", pattern='brief'): - RegFromComment(offset + 0x44800000, code) + RegFromComment(offset + 0x44800000, code.lower()) +Reg('emb2app_line_sel_low', 0x44800000 + 0x14) +for i in range(0,16): + FieldBit(f'emb2app{i}_sel', i*2, 2) +Reg('emb2app_line_sel_high', 0x44800000 + 0x18) +ipc_names = [] +def flipname(name): + name = name.replace('app', 'XXXXX') + name = name.replace('emb', 'YYYYY') + name = name.replace('XXXXX', 'emb') + name = name.replace('YYYYY', 'app') + return name +for reg in peris['ipc'].regs: + if (len(reg.fields) == 1): + reg.fields = [] + ipc_names.append((flipname(reg.name), reg.offset + 0x100, reg.fields)) +for name, offset, f in ipc_names: + Reg(name, offset + 0x44800000) + for i in f: + FieldBit(flipname(i.name), i.lsb, i.len) #open('../src/include/phy/ipc.h', 'w').write('\n'.join(GenHeader())) #print('\n'.join(GenHeader())) diff --git a/src/include/phy/ipc.h b/src/include/phy/ipc.h index 176b7bd..46b20d1 100644 --- a/src/include/phy/ipc.h +++ b/src/include/phy/ipc.h @@ -2,50 +2,67 @@ typedef union { uint32_t regs[0x400]; uint8_t pad[0x1000]; struct { + uint32_t app2emb_trigger; // @ 0x0 + uint32_t emb2app_rawstatus; // @ 0x4 + uint32_t emb2app_ack; // @ 0x8 + uint32_t emb2app_unmask_set; // @ 0xc + uint32_t emb2app_unmask_clear; // @ 0x10 union { uint32_t value; struct { - uint32_t APP2EMB_TRIGGER : 32; // @ 31 -- 0 # 0x0 + uint32_t emb2app0_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t emb2app1_sel : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t emb2app2_sel : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t emb2app3_sel : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t emb2app4_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t emb2app5_sel : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t emb2app6_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t emb2app7_sel : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t emb2app8_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t emb2app9_sel : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t emb2app10_sel : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t emb2app11_sel : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t emb2app12_sel : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t emb2app13_sel : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t emb2app14_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t emb2app15_sel : 2; // @ 31 -- 30 # 0x3fffffff }; - } APP2EMB_TRIGGER; // @ 0x0 + } emb2app_line_sel_low; // @ 0x14 + uint32_t emb2app_line_sel_high; // @ 0x18 + uint32_t emb2app_status; // @ 0x1c + uint8_t pad0[0x20]; + uint32_t app_signature; // @ 0x40 + uint8_t pad1[0xbc]; + uint32_t emb2app_trigger; // @ 0x100 + uint32_t app2emb_rawstatus; // @ 0x104 + uint32_t app2emb_ack; // @ 0x108 + uint32_t app2emb_unmask_set; // @ 0x10c + uint32_t app2emb_unmask_clear; // @ 0x110 union { uint32_t value; struct { - uint32_t EMB2APP_RAWSTATUS : 32; // @ 31 -- 0 # 0x0 + uint32_t app2emb0_sel : 2; // @ 1 -- 0 # 0xfffffffc + uint32_t app2emb1_sel : 2; // @ 3 -- 2 # 0xfffffff3 + uint32_t app2emb2_sel : 2; // @ 5 -- 4 # 0xffffffcf + uint32_t app2emb3_sel : 2; // @ 7 -- 6 # 0xffffff3f + uint32_t app2emb4_sel : 2; // @ 9 -- 8 # 0xfffffcff + uint32_t app2emb5_sel : 2; // @ 11 -- 10 # 0xfffff3ff + uint32_t app2emb6_sel : 2; // @ 13 -- 12 # 0xffffcfff + uint32_t app2emb7_sel : 2; // @ 15 -- 14 # 0xffff3fff + uint32_t app2emb8_sel : 2; // @ 17 -- 16 # 0xfffcffff + uint32_t app2emb9_sel : 2; // @ 19 -- 18 # 0xfff3ffff + uint32_t app2emb10_sel : 2; // @ 21 -- 20 # 0xffcfffff + uint32_t app2emb11_sel : 2; // @ 23 -- 22 # 0xff3fffff + uint32_t app2emb12_sel : 2; // @ 25 -- 24 # 0xfcffffff + uint32_t app2emb13_sel : 2; // @ 27 -- 26 # 0xf3ffffff + uint32_t app2emb14_sel : 2; // @ 29 -- 28 # 0xcfffffff + uint32_t app2emb15_sel : 2; // @ 31 -- 30 # 0x3fffffff }; - } EMB2APP_RAWSTATUS; // @ 0x4 - union { - uint32_t value; - struct { - uint32_t EMB2APP_ACK : 32; // @ 31 -- 0 # 0x0 - }; - } EMB2APP_ACK; // @ 0x8 - union { - uint32_t value; - struct { - uint32_t EMB2APP_UNMASK : 32; // @ 31 -- 0 # 0x0 - }; - } EMB2APP_UNMASK_SET; // @ 0xc - union { - uint32_t value; - struct { - uint32_t EMB2APP_UNMASK : 32; // @ 31 -- 0 # 0x0 - }; - } EMB2APP_UNMASK_CLEAR; // @ 0x10 - uint8_t pad0[0x8]; - union { - uint32_t value; - struct { - uint32_t EMB2APP_STATUS : 32; // @ 31 -- 0 # 0x0 - }; - } EMB2APP_STATUS; // @ 0x1c - uint8_t pad1[0x20]; - union { - uint32_t value; - struct { - uint32_t APP_SIGNATURE : 32; // @ 31 -- 0 # 0x0 - }; - } APP_SIGNATURE; // @ 0x40 + } app2emb_line_sel_low; // @ 0x114 + uint32_t app2emb_line_sel_high; // @ 0x118 + uint32_t app2emb_status; // @ 0x11c + uint8_t pad2[0x20]; + uint32_t emb_signature; // @ 0x140 }; } ipc_regs; #define IPC_BASE 0x44800000 diff --git a/src/svd/ipc.svd b/src/svd/ipc.svd index 011f109..75bc770 100644 --- a/src/svd/ipc.svd +++ b/src/svd/ipc.svd @@ -12,88 +12,258 @@ - APP2EMB_TRIGGER - APP2EMB_TRIGGER. + app2emb_trigger + app2emb_trigger. 0x0 - - - APP2EMB_TRIGGER - 31 - 0 - - - EMB2APP_RAWSTATUS - EMB2APP_RAWSTATUS. + emb2app_rawstatus + emb2app_rawstatus. 0x4 - - - EMB2APP_RAWSTATUS - 31 - 0 - - - EMB2APP_ACK - EMB2APP_ACK. + emb2app_ack + emb2app_ack. 0x8 - - - EMB2APP_ACK - 31 - 0 - - - EMB2APP_UNMASK_SET - EMB2APP_UNMASK_SET. + emb2app_unmask_set + emb2app_unmask_set. 0xc - - - EMB2APP_UNMASK - 31 - 0 - - - EMB2APP_UNMASK_CLEAR - EMB2APP_UNMASK_CLEAR. + emb2app_unmask_clear + emb2app_unmask_clear. 0x10 + + + emb2app_line_sel_low + emb2app_line_sel_low. + 0x14 - EMB2APP_UNMASK + emb2app15_sel 31 + 30 + + + emb2app14_sel + 29 + 28 + + + emb2app13_sel + 27 + 26 + + + emb2app12_sel + 25 + 24 + + + emb2app11_sel + 23 + 22 + + + emb2app10_sel + 21 + 20 + + + emb2app9_sel + 19 + 18 + + + emb2app8_sel + 17 + 16 + + + emb2app7_sel + 15 + 14 + + + emb2app6_sel + 13 + 12 + + + emb2app5_sel + 11 + 10 + + + emb2app4_sel + 9 + 8 + + + emb2app3_sel + 7 + 6 + + + emb2app2_sel + 5 + 4 + + + emb2app1_sel + 3 + 2 + + + emb2app0_sel + 1 0 - EMB2APP_STATUS - EMB2APP_STATUS. + emb2app_line_sel_high + emb2app_line_sel_high. + 0x18 + + + emb2app_status + emb2app_status. 0x1c - - - EMB2APP_STATUS - 31 - 0 - - - APP_SIGNATURE - APP_SIGNATURE. + app_signature + app_signature. 0x40 + + + emb2app_trigger + emb2app_trigger. + 0x100 + + + app2emb_rawstatus + app2emb_rawstatus. + 0x104 + + + app2emb_ack + app2emb_ack. + 0x108 + + + app2emb_unmask_set + app2emb_unmask_set. + 0x10c + + + app2emb_unmask_clear + app2emb_unmask_clear. + 0x110 + + + app2emb_line_sel_low + app2emb_line_sel_low. + 0x114 - APP_SIGNATURE + app2emb15_sel 31 + 30 + + + app2emb14_sel + 29 + 28 + + + app2emb13_sel + 27 + 26 + + + app2emb12_sel + 25 + 24 + + + app2emb11_sel + 23 + 22 + + + app2emb10_sel + 21 + 20 + + + app2emb9_sel + 19 + 18 + + + app2emb8_sel + 17 + 16 + + + app2emb7_sel + 15 + 14 + + + app2emb6_sel + 13 + 12 + + + app2emb5_sel + 11 + 10 + + + app2emb4_sel + 9 + 8 + + + app2emb3_sel + 7 + 6 + + + app2emb2_sel + 5 + 4 + + + app2emb1_sel + 3 + 2 + + + app2emb0_sel + 1 0 + + app2emb_line_sel_high + app2emb_line_sel_high. + 0x118 + + + app2emb_status + app2emb_status. + 0x11c + + + emb_signature + emb_signature. + 0x140 + \ No newline at end of file From 1845f40d036456f2c14b4fc521f0fa991c74934c Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:21:09 -0600 Subject: [PATCH 077/148] use new macro --- src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c | 2 +- src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c index eb71747..381def7 100644 --- a/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c +++ b/src/bl602_wifi/driver/phy/phy_rf/bl602_rf_private.c @@ -80,7 +80,7 @@ static void rf_pri_restore_state_for_cal() { #include "rf_private_save.h" } -#include "macro.h" +#include #define mapper0(x) new_pucr1.x = 0; #define mapper1(x) new_pucr1.x = 1; #define P_CLR(...) APPLY(mapper0, __VA_ARGS__) diff --git a/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c b/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c index 6a2b927..fc4b638 100644 --- a/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c +++ b/src/bl602_wifi/driver/phy/phy_rf/phy_bl602.c @@ -13,7 +13,7 @@ #include #include #include -#include "macro.h" +#include static int8_t rxgain_offset_vs_temperature; // :79:15 static int8_t poweroffset[14]; // :80:15 From 6537668c32049edf173a218e742b43f7d4e6b37b Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:21:28 -0600 Subject: [PATCH 078/148] reduce warning --- src/include/utils.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/utils.h b/src/include/utils.h index 3cbf09b..1b3c62d 100644 --- a/src/include/utils.h +++ b/src/include/utils.h @@ -3,8 +3,8 @@ #define MIN(x,y) (((x) > (y)) ? (y) : (x)) #define MAX(x,y) (((x) < (y)) ? (y) : (x)) int puts(char *s); -int printf(char *fmt,...); -void* memset(void *, int, long unsigned int); +int printf(const char *fmt,...); +void* memset(void *, int, unsigned int); void* memcpy(void*, const void*, unsigned int); void BL602_Delay_US(uint32_t cnt); void BL602_Delay_MS(uint32_t cnt); From db03980dd85106d5db098b126864fcfc1139c5a2 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:21:39 -0600 Subject: [PATCH 079/148] sysctrl_init() --- src/bl602_wifi/driver/sysctrl/sysctrl.c | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 src/bl602_wifi/driver/sysctrl/sysctrl.c diff --git a/src/bl602_wifi/driver/sysctrl/sysctrl.c b/src/bl602_wifi/driver/sysctrl/sysctrl.c new file mode 100644 index 0000000..9df88cd --- /dev/null +++ b/src/bl602_wifi/driver/sysctrl/sysctrl.c @@ -0,0 +1,6 @@ +#include +#include +void sysctrl_init() { + SYSCTRL->diag_conf.value = 0x8000000c; + SYSCTRL->misc_cntl.set1 = 0x1ff; +} From 0231b45681d00deb067fc9edcb0a19fc72795d79 Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:22:24 -0600 Subject: [PATCH 080/148] ipc and related headers --- src/bl602_wifi/driver/ipc/ipc_emb.c | 204 ++++++++++++++++++ src/bl602_wifi/driver/ipc/ipc_shared.c | 3 + src/include/bl602_wifi/ipc/ipc_emb.h | 33 +++ src/include/bl602_wifi/ipc/ipc_shared.h | 19 ++ src/include/bl602_wifi/la/la_mem.h | 8 + src/include/bl602_wifi/lmac/tx/tx_swdesc.h | 71 ++++++ .../bl602_wifi/modules/common/co_list.h | 12 ++ src/include/bl602_wifi/modules/ke/ke_env.h | 21 ++ src/include/bl602_wifi/modules/ke/ke_event.h | 12 ++ src/include/bl602_wifi/modules/ke/ke_mem.h | 11 + src/include/bl602_wifi/modules/ke/ke_msg.h | 41 ++++ src/include/bl602_wifi/modules/ke/ke_task.h | 74 +++++++ src/include/bl602_wifi/modules/mac/mac.h | 99 +++++++++ src/include/bl602_wifi/umac/txu/txu_cntrl.h | 16 ++ 14 files changed, 624 insertions(+) create mode 100644 src/bl602_wifi/driver/ipc/ipc_emb.c create mode 100644 src/bl602_wifi/driver/ipc/ipc_shared.c create mode 100644 src/include/bl602_wifi/ipc/ipc_emb.h create mode 100644 src/include/bl602_wifi/ipc/ipc_shared.h create mode 100644 src/include/bl602_wifi/la/la_mem.h create mode 100644 src/include/bl602_wifi/lmac/tx/tx_swdesc.h create mode 100644 src/include/bl602_wifi/modules/common/co_list.h create mode 100644 src/include/bl602_wifi/modules/ke/ke_env.h create mode 100644 src/include/bl602_wifi/modules/ke/ke_event.h create mode 100644 src/include/bl602_wifi/modules/ke/ke_mem.h create mode 100644 src/include/bl602_wifi/modules/ke/ke_msg.h create mode 100644 src/include/bl602_wifi/modules/ke/ke_task.h create mode 100644 src/include/bl602_wifi/modules/mac/mac.h create mode 100644 src/include/bl602_wifi/umac/txu/txu_cntrl.h diff --git a/src/bl602_wifi/driver/ipc/ipc_emb.c b/src/bl602_wifi/driver/ipc/ipc_emb.c new file mode 100644 index 0000000..52a1288 --- /dev/null +++ b/src/bl602_wifi/driver/ipc/ipc_emb.c @@ -0,0 +1,204 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPC_EMB_SIGNATURE_RESET 0x49504332 + +int internel_cal_size_tx_desc; // :59:5 +static TaskHandle_t xTaskToNotify; // :91:21 +uint32_t ipc_emb_counter; // :92:10 +const uint32_t ipc_emb_evt_bit[5] = {0x80, 0x100, 0x200, 0x400, 0x800}; +struct ipc_emb_env_tag ipc_emb_env; // :110:24 +const int nx_txdesc_cnt_msk[1] = {3}; // :113:11 + +void ipc_emb_msg_dma_int_handler(void) { + // empty function + return ; +} + +void ipc_emb_dbg_dma_int_handler(void) { + DMA->int_ack.b7 = 1; + IPC->emb2app_trigger = 1; +} + +void ipc_emb_dump(void) { + // empty function + return ; +} + +bool ipc_emb_tx_q_has_data(int queue_idx) { + // guessed, not sure if it's !=0 or == 0 + // rationally, it should be != 0 + return (ipc_emb_env.txdesc + (ipc_emb_env.txdesc_idx & 3))->ready != 0; +} + +uint32_t ipc_emb_tx_evt_field(uint32_t stat) { + // can't find impl + return 0; +} + +void ipc_emb_txcfm_ind(uint32_t queue_bits) { + IPC->emb2app_trigger = queue_bits << 7; +} + +void ipc_emb_init(void) { + xTaskToNotify = xTaskGetCurrentTaskHandle(); + memset(&ipc_emb_env, 0, 0x20); + ipc_emb_env.txdesc = ipc_shared_env.txdesc0; + ASSERT_ERR(IPC->emb_signature == IPC_EMB_SIGNATURE_RESET); + IPC->app2emb_line_sel_low.value = 0; + IPC->app2emb_line_sel_high = 0; + IPC->app2emb_line_sel_low.app2emb0_sel = 0; + IPC->app2emb_line_sel_low.app2emb1_sel = 1; + IPC->app2emb_line_sel_low.app2emb4_sel = 2; + IPC->app2emb_line_sel_low.app2emb5_sel = 2; + IPC->app2emb_line_sel_low.app2emb6_sel = 2; + IPC->app2emb_line_sel_low.app2emb8_sel = 3; + IPC->app2emb_line_sel_low.app2emb9_sel = 3; + IPC->app2emb_line_sel_low.app2emb10_sel = 3; + IPC->app2emb_line_sel_low.app2emb11_sel = 3; + IPC->app2emb_line_sel_low.app2emb12_sel = 3; + IPC->app2emb_unmask_set = 0x1f03; +} + +void ipc_emb_notify(void) { + ASSERT_ERR(xTaskToNotify != NULL); + if (TrapNetCounter == 0) { + xTaskGenericNotify(xTaskToNotify,0,eIncrement,(uint32_t *)0x0); + } else { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + vTaskNotifyGiveFromISR(xTaskToNotify, &xHigherPriorityTaskWoken); + if (xHigherPriorityTaskWoken != 0) { + vTaskSwitchContext(); + } + } +} + +void ipc_emb_wait(void) { + ulTaskNotifyTake(1, portMAX_DELAY); +} + +void ipc_emb_tx_flow_off(void) { + IPC->app2emb_unmask_clear = 0x1f00; + ke_evt_clear(0xf80); +} + +void ipc_emb_tx_flow_on(void) { + IPC->app2emb_unmask_set = 0x1f00; +} + +void ipc_emb_tx_irq(void) { + uint32_t status = IPC->app2emb_status; + if (status & 0x1f00) { + ke_evt_set(status >> 1); + IPC->app2emb_unmask_clear = status; + IPC->app2emb_ack = status; + } +} + +void ipc_emb_txdesc_copy(struct txdesc *dst_local, volatile struct txdesc_host *src_shared) { + for (int i = 0; i < sizeof(struct hostdesc); i++) { + *(uint32_t*)&dst_local->host = *(uint32_t*)&src_shared->host; + } +} + +void ipc_emb_tx_evt(int queue_idx) { + uint32_t event = ipc_emb_evt_bit[queue_idx]; + ke_evt_clear(event); + while (true) { + volatile struct txdesc_host* txdesc_hx = ipc_emb_env.txdesc + (ipc_emb_env.txdesc_idx & 3); + if (txdesc_hx->ready != 0xffffffff) { + IPC->app2emb_unmask_set = 0x100; + return ; + } + if (((event & 0x800) == 0) && ((ke_env.evt_field & 0x440800) != 0)) break; + IPC->app2emb_ack = 0x100; + struct txdesc* txdesc = (struct txdesc*)txdesc_hx->pad_txdesc; + memset(txdesc, 0, sizeof(struct txdesc)); + txdesc->hw_desc.cfm_ptr = &txdesc->hw_cfm; + txdesc->lmac.hw_desc = &txdesc->hw_desc; + ipc_emb_txdesc_copy(txdesc, txdesc_hx); + txdesc->lmac.agg_desc = 0; + txdesc->hw_desc.thd.nextmpdudesc_ptr = 0; + txdesc->hw_desc.thd.optlen[0] = 0; + txdesc->hw_desc.thd.optlen[1] = 0; + txdesc->hw_desc.thd.optlen[2] = 0; + txdesc->umac.buf_control = 0; + txu_cntrl_push(txdesc, 0); + txdesc_hx->ready = 1; + ipc_emb_env.txdesc_idx = ipc_emb_env.txdesc_idx + 1; + } + ke_evt_set(event); +} + +void ipc_emb_cfmback_irq(void) { + if (IPC->app2emb_status & 0x20) { + IPC->app2emb_unmask_clear = 0x20; + IPC->app2emb_ack = 0x20; + ke_evt_set(0x40000); + } + if (IPC->app2emb_status & 0x10) { + IPC->app2emb_unmask_clear = 0x10; + IPC->app2emb_ack = 0x10; + ke_evt_set(0x80000); + } +} + +bool ipc_emb_hostrxdesc_check(void) { + return 1; +} + +void ipc_emb_radar_event_ind(void) { + IPC->emb2app_trigger = 0x40; +} + +void ipc_emb_prim_tbtt_ind(void) { + IPC->emb2app_trigger = 0x10; +} + +void ipc_emb_sec_tbtt_ind(void) { + IPC->emb2app_trigger = 0x20; +} + +void ipc_emb_kmsg_hdlr(struct ke_msg *kmsg_ipc) { + struct ke_msg* kmsg_dst = ke_malloc(kmsg_ipc->param_len + sizeof(struct ke_msg)); + ASSERT_ERR(kmsg_dst != NULL); + kmsg_dst->hdr.next = NULL; + kmsg_dst->id = kmsg_ipc->id; + kmsg_dst->dest_id = kmsg_ipc->dest_id; + kmsg_dst->src_id = 13; + kmsg_dst->param_len = kmsg_ipc->param_len; + memcpy(kmsg_dst->param, kmsg_ipc->param, kmsg_dst->param_len); + kmsg_ipc->src_id = ipc_emb_env.ipc_msgacke2a_cnt++; + ipc_emb_env.ipc_msgacke2a_cnt = ipc_emb_env.ipc_msgacke2a_cnt; + ASSERT_ERR(ke_task_local(kmsg_dst->dest_id)); + IPC->emb2app_trigger = 4; + ke_msg_send(kmsg_dst + 1); +} + +void ipc_emb_msg_irq(void) { + if (IPC->app2emb_status & 2) { + ke_evt_set(0x2000000); + IPC->app2emb_unmask_clear = 2; + } +} + +void ipc_emb_msg_evt(int dummy) { + for (uint32_t rawstatus = IPC->app2emb_rawstatus; rawstatus & 2; rawstatus = IPC->app2emb_rawstatus) { + IPC->app2emb_ack = 2; + ipc_emb_kmsg_hdlr((struct ke_msg *)&ipc_shared_env.msg_a2e_buf); + } + ke_evt_clear(0x2000000); + IPC->app2emb_unmask_set = 2; +} diff --git a/src/bl602_wifi/driver/ipc/ipc_shared.c b/src/bl602_wifi/driver/ipc/ipc_shared.c new file mode 100644 index 0000000..5949185 --- /dev/null +++ b/src/bl602_wifi/driver/ipc/ipc_shared.c @@ -0,0 +1,3 @@ +#include + +struct ipc_shared_env_tag ipc_shared_env; // :24:27 \ No newline at end of file diff --git a/src/include/bl602_wifi/ipc/ipc_emb.h b/src/include/bl602_wifi/ipc/ipc_emb.h new file mode 100644 index 0000000..9d643e7 --- /dev/null +++ b/src/include/bl602_wifi/ipc/ipc_emb.h @@ -0,0 +1,33 @@ +#ifndef _IPC_EMB_H_ +#define _IPC_EMB_H_ + +#include +#include +#include + +struct ipc_emb_env_tag { + struct co_list rx_queue; // +0 + struct co_list cfm_queue; // +8 + uint8_t ipc_rxdesc_idx; // +16 + uint8_t ipc_rxbuf_idx; // +17 + uint8_t ipc_radar_buf_idx; // +18 + uint8_t ipc_msge2a_buf_idx; // +19 + uint8_t ipc_dbg_buf_idx; // +20 + uint8_t ipc_msgacke2a_cnt; // +21 + uint32_t txdesc_idx; // +24 + volatile struct txdesc_host *txdesc; // +28 +}; + + +extern struct ipc_emb_env_tag ipc_emb_env; +extern const int nx_txdesc_cnt_msk[]; + + +bool ipc_emb_tx_q_has_data(int queue_idx); +uint32_t ipc_emb_tx_evt_field(uint32_t stat); +void ipc_emb_txcfm_ind(uint32_t queue_bits); +void ipc_emb_init(void); +void ipc_emb_notify(void); +void ipc_emb_wait(void); + +#endif \ No newline at end of file diff --git a/src/include/bl602_wifi/ipc/ipc_shared.h b/src/include/bl602_wifi/ipc/ipc_shared.h new file mode 100644 index 0000000..94bf067 --- /dev/null +++ b/src/include/bl602_wifi/ipc/ipc_shared.h @@ -0,0 +1,19 @@ +#ifndef _IPC_SHARED_H_ +#define _IPC_SHARED_H_ +#include +#include +struct ipc_a2e_msg { + uint32_t dummy_word; // +0 + uint32_t msg[127]; // +4 +}; // :213:8 +#ifndef CFG_TXDESC +#define CFG_TXDESC 4 +#endif +#define NX_TXDESC_CNT0 CFG_TXDESC +struct ipc_shared_env_tag { + volatile struct ipc_a2e_msg msg_a2e_buf; // +0 + volatile uint32_t pattern_addr; // +512 + volatile struct txdesc_host txdesc0[4]; // +516 +}; // :244:8 +extern struct ipc_shared_env_tag ipc_shared_env; // :257:34 +#endif // _IPC_SHARED_H_ \ No newline at end of file diff --git a/src/include/bl602_wifi/la/la_mem.h b/src/include/bl602_wifi/la/la_mem.h new file mode 100644 index 0000000..5a9f460 --- /dev/null +++ b/src/include/bl602_wifi/la/la_mem.h @@ -0,0 +1,8 @@ +#ifndef _LA_MEM_H_ +#define _LA_MEM_H_ + +struct la_mem_format { + uint32_t word[4]; // +0 +}; // :37:8 + +#endif // _LA_MEM_H_ diff --git a/src/include/bl602_wifi/lmac/tx/tx_swdesc.h b/src/include/bl602_wifi/lmac/tx/tx_swdesc.h new file mode 100644 index 0000000..58a7c4a --- /dev/null +++ b/src/include/bl602_wifi/lmac/tx/tx_swdesc.h @@ -0,0 +1,71 @@ +#ifndef _TX_SWDESC_H_ +#define _TX_SWDESC_H_ + +#include +#include + +#include +#include +#include + + +struct hostdesc { + uint32_t pbuf_addr; // +0 + uint32_t packet_addr; // +4 + uint16_t packet_len; // +8 + uint32_t status_addr; // +12 + struct mac_addr eth_dest_addr; // +16 + struct mac_addr eth_src_addr; // +22 + uint16_t ethertype; // +28 + uint16_t pn[4]; // +30 + uint16_t sn; // +38 + uint16_t timestamp; // +40 + uint8_t tid; // +42 + uint8_t vif_idx; // +43 + uint8_t staid; // +44 + uint16_t flags; // +46 + uint32_t pbuf_chained_ptr[4]; // +48 + uint32_t pbuf_chained_len[4]; // +64 +}; + +struct umacdesc { + struct txl_buffer_control *buf_control; // +0 + uint32_t buff_offset; // +4 + uint16_t payl_len; // +8 + uint8_t head_len; // +10 + uint8_t hdr_len_802_2; // +11 + uint8_t tail_len; // +12 +}; + +struct lmacdesc { + struct tx_agg_desc *agg_desc; // +0 + struct txl_buffer_tag *buffer; // +4 + struct tx_hw_desc *hw_desc; // +8 +}; + +struct txdesc { + struct co_list_hdr list_hdr; // +0 + struct hostdesc host; // +4 + struct umacdesc umac; // +84 + struct lmacdesc lmac; // +100 + struct tx_hw_desc hw_desc; // +112 + struct tx_cfm_tag hw_cfm; // +184 + uint32_t buf[128]; // +204 +}; + +struct txdesc_host { + uint32_t ready; // +0 + struct hostdesc host; // +4 + uint32_t pad_txdesc[55]; // +84 + uint32_t pad_buf[128]; // +304 +}; + + +extern struct txdesc *txdesc_array; +extern const int nx_txdesc_cnt[5]; + + +bool is_int_frame(struct txdesc *txdesc); +bool is_qos_data(struct txdesc *txdesc); + +#endif diff --git a/src/include/bl602_wifi/modules/common/co_list.h b/src/include/bl602_wifi/modules/common/co_list.h new file mode 100644 index 0000000..e7600e8 --- /dev/null +++ b/src/include/bl602_wifi/modules/common/co_list.h @@ -0,0 +1,12 @@ +#ifndef _CO_LIST_H_ +#define _CO_LIST_H_ +struct co_list_hdr { + struct co_list_hdr *next; // +0 +}; // :47:8 + +struct co_list { + struct co_list_hdr *first; // +0 + struct co_list_hdr *last; // +4 +}; // :54:8 + +#endif // _CO_LIST_H_ diff --git a/src/include/bl602_wifi/modules/ke/ke_env.h b/src/include/bl602_wifi/modules/ke/ke_env.h new file mode 100644 index 0000000..1516f77 --- /dev/null +++ b/src/include/bl602_wifi/modules/ke/ke_env.h @@ -0,0 +1,21 @@ +#ifndef _KE_ENV_H_ +#define _KE_ENV_H_ + +#include + +#include + + +typedef uint32_t evt_field_t; + +struct ke_env_tag { + volatile evt_field_t evt_field; // +0 + struct co_list queue_sent; // +4 + struct co_list queue_saved; // +12 + struct co_list queue_timer; // +20 + struct mblock_free *mblock_first; // +28 +}; + +extern struct ke_env_tag ke_env; + +#endif diff --git a/src/include/bl602_wifi/modules/ke/ke_event.h b/src/include/bl602_wifi/modules/ke/ke_event.h new file mode 100644 index 0000000..4298011 --- /dev/null +++ b/src/include/bl602_wifi/modules/ke/ke_event.h @@ -0,0 +1,12 @@ +#ifndef _KE_EVENT_H_ +#define _KE_EVENT_H_ + +#include + +evt_field_t ke_evt_get(void); +void ke_evt_set(const evt_field_t event); +void ke_evt_clear(const evt_field_t event); +void ke_evt_schedule(void); +void ke_init(void); + +#endif diff --git a/src/include/bl602_wifi/modules/ke/ke_mem.h b/src/include/bl602_wifi/modules/ke/ke_mem.h new file mode 100644 index 0000000..07df734 --- /dev/null +++ b/src/include/bl602_wifi/modules/ke/ke_mem.h @@ -0,0 +1,11 @@ +#ifndef _KE_MEM_H_ +#define _KE_MEM_H_ + +#include + + +struct mblock_free *ke_mem_init(void); +void *ke_malloc(uint32_t size); +void ke_free(void *mem_ptr); + +#endif // _KE_MEM_H_ diff --git a/src/include/bl602_wifi/modules/ke/ke_msg.h b/src/include/bl602_wifi/modules/ke/ke_msg.h new file mode 100644 index 0000000..30b3097 --- /dev/null +++ b/src/include/bl602_wifi/modules/ke/ke_msg.h @@ -0,0 +1,41 @@ +#ifndef _KE_MSG_H_ +#define _KE_MSG_H_ + +#include +#include +#include + +#include + + +typedef uint16_t ke_task_id_t; +typedef uint16_t ke_state_t; +typedef uint16_t ke_msg_id_t; + +struct ke_msg { + struct co_list_hdr hdr; // +0 + ke_msg_id_t id; // +4 + ke_task_id_t dest_id; // +6 + ke_task_id_t src_id; // +8 + uint16_t param_len; // +10 + uint32_t param[]; // +12 +}; + +STATIC_ASSERT(sizeof(struct ke_msg) == 12, ke_msg_must_has_sizeof_12); + +enum ke_msg_status_tag { + KE_MSG_CONSUMED = 0, + KE_MSG_NO_FREE = 1, + KE_MSG_SAVED = 2 +}; + + +struct ke_msg *ke_param2msg(const void *param_ptr); +void *ke_msg2param(const struct ke_msg *msg); +void *ke_msg_alloc(const ke_msg_id_t id, const ke_task_id_t dest_id, const ke_task_id_t src_id, const uint16_t param_len); +void ke_msg_send(const void *param_ptr); +void ke_msg_send_basic(const ke_msg_id_t id, const ke_task_id_t dest_id, const ke_task_id_t src_id); +void ke_msg_forward_and_change_id(const void *param_ptr, const ke_msg_id_t msg_id, const ke_task_id_t dest_id, const ke_task_id_t src_id); +void ke_msg_free(const struct ke_msg *msg); + +#endif // _KE_MSG_H_ diff --git a/src/include/bl602_wifi/modules/ke/ke_task.h b/src/include/bl602_wifi/modules/ke/ke_task.h new file mode 100644 index 0000000..f26497b --- /dev/null +++ b/src/include/bl602_wifi/modules/ke/ke_task.h @@ -0,0 +1,74 @@ +#ifndef _KE_TASK_H_ +#define _KE_TASK_H_ + +#include +#include + +#include +#include + +// based on TASK_DESC +enum +{ + TASK_NONE = (uint8_t) -1, + + /// MAC Management task. + TASK_MM = 0, + TASK_DBG = 1, + /// SCAN task + TASK_SCAN = 2, + /// TDLS task + TASK_TDLS = 3, // maybe, not used anyway + /// SCAN task + TASK_SCANU = 4, + /// SCAN task + TASK_ME = 5, + /// SM task + TASK_SM = 6, + /// APM task + TASK_APM = 7, + /// BAM task + TASK_BAM = 8, + /// MESH task + TASK_MESH = 9, // maybe, not used anyway + TASK_HOSTAPD = 10, + /// RXU task + TASK_RXU = 11, // maybe, not used anyway + /// CFG task + TASK_CFG = 12, + // nX API task + TASK_API = 13, // maybe, not used anyway + TASK_MAX, // max == 14 +}; + +#define DRV_TASK_ID 100 + + +typedef int (*ke_msg_func_t)(const ke_msg_id_t, const void *, const ke_task_id_t, const ke_task_id_t); + +struct ke_msg_handler { + ke_msg_id_t id; // +0 + ke_msg_func_t func; // +4 +}; + +struct ke_state_handler { + const struct ke_msg_handler *msg_table; // +0 + uint16_t msg_cnt; // +4 +}; + +struct ke_task_desc { + const struct ke_state_handler *state_handler; // +0 + const struct ke_state_handler *default_handler; // +4 + ke_state_t *state; // +8 + uint16_t state_max; // +12 + uint16_t idx_max; // +14 +}; + +static bool ke_task_local(const ke_task_id_t id) { + ASSERT_ERR(id <= TASK_MAX); + return id < TASK_API; +}; +ke_state_t ke_state_get(const ke_task_id_t id); +void ke_state_set(const ke_task_id_t id, const ke_state_t state_id); + +#endif // __KE_TASK_H__ diff --git a/src/include/bl602_wifi/modules/mac/mac.h b/src/include/bl602_wifi/modules/mac/mac.h new file mode 100644 index 0000000..9f8e489 --- /dev/null +++ b/src/include/bl602_wifi/modules/mac/mac.h @@ -0,0 +1,99 @@ +#ifndef _MAC_H_ +#define _MAC_H_ + +#include +#include + + +struct mac_addr { + uint16_t array[3]; // +0 +}; + +struct mac_ssid { + uint8_t length; // +0 + uint8_t array[32]; // +1 + uint8_t array_tail[1]; // +33 +}; + +struct mac_rateset { + uint8_t length; // +0 + uint8_t array[12]; // +1 +}; + +struct key_info_tag { + uint64_t rx_pn[9]; // +0 + uint64_t tx_pn; // +72 + union { + struct { + uint32_t tx_key[2]; // +0 + uint32_t rx_key[2]; // +8 + } mic; + struct { + uint32_t key[4]; // +0 + } mfp; + } u; // +80 + uint8_t cipher; // +96 + uint8_t key_idx; // +97 + uint8_t hw_key_idx; // +98 + bool valid; // +99 +}; + +struct mac_sec_key { + uint8_t length; // +0 + uint32_t array[8]; // +4 +}; + +struct mac_htcapability { + uint16_t ht_capa_info; // +0 + uint8_t a_mpdu_param; // +2 + uint8_t mcs_rate[16]; // +3 + uint16_t ht_extended_capa; // +20 + uint32_t tx_beamforming_capa; // +24 + uint8_t asel_capa; // +28 +}; + +struct mac_vhtcapability { + uint32_t vht_capa_info; // +0 + uint16_t rx_mcs_map; // +4 + uint16_t rx_highest; // +6 + uint16_t tx_mcs_map; // +8 + uint16_t tx_highest; // +10 +}; + +struct mac_edca_param_set { + uint8_t qos_info; // +0 + uint8_t acm; // +1 + uint32_t ac_param[4]; // +4 +}; + +struct mac_scan_result { + struct mac_addr bssid; // +0 + struct mac_ssid ssid; // +6 + uint16_t bsstype; // +40 + struct scan_chan_tag *chan; // +44 + uint16_t beacon_period; // +48 + uint16_t cap_info; // +50 + bool valid_flag; // +52 + int8_t rssi; // +53 + int8_t ppm_rel; // +54 + int8_t ppm_abs; // +55 +}; + +struct mac_sta_info { + struct mac_rateset rate_set; // +0 + struct mac_htcapability ht_cap; // +16 + struct mac_vhtcapability vht_cap; // +48 + uint32_t capa_flags; // +60 + uint8_t phy_bw_max; // +64 + uint8_t bw_cur; // +65 + uint8_t uapsd_queues; // +66 + uint8_t max_sp_len; // +67 + uint8_t stbc_nss; // +68 +}; + +extern const uint8_t mac_tid2ac[]; +extern const uint8_t mac_ac2uapsd[4]; +extern const uint8_t mac_id2rate[]; +extern const struct mac_addr mac_addr_bcst; + +#endif diff --git a/src/include/bl602_wifi/umac/txu/txu_cntrl.h b/src/include/bl602_wifi/umac/txu/txu_cntrl.h new file mode 100644 index 0000000..1d9490c --- /dev/null +++ b/src/include/bl602_wifi/umac/txu/txu_cntrl.h @@ -0,0 +1,16 @@ +#ifndef __TXU_CNTRL_H__ +#define __TXU_CNTRL_H__ + +#include +#include + +#include + + +bool txu_cntrl_push(struct txdesc *txdesc, uint8_t access_category); +void txu_cntrl_frame_build(struct txdesc *txdesc, uint32_t buf); +void txu_cntrl_tkip_mic_append(struct txdesc *txdesc, uint8_t ac); +void txu_cntrl_cfm(struct txdesc *txdesc); +void txu_cntrl_protect_mgmt_frame(struct txdesc *txdesc, uint32_t frame, uint16_t hdr_len); + +#endif // __TXU_CNTRL_H__ From c1258fa78648e65aa6e59403c0cff94cf8e1ffce Mon Sep 17 00:00:00 2001 From: Fangfei Yang Date: Thu, 23 Dec 2021 05:24:33 -0600 Subject: [PATCH 081/148] bl602_demo_wifi.elf built w/o -Wl,--gc-sections --- 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