You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Any other thing we need to know for helping you better?
In the CSI extraction process, does it have to work in the full-duplex (Self-TX) mode? Can we set it as a receiver to obtain CSI?
If full-duplex mode is required, does the CSI extraction process only work for single RX sampling? The hardware platform we used is Xilinx Zed board + FMCOMMS3, which includes two Rx antennas.
If the above options are not available, can I modify the FPGA code in your project to enable the entire module to operate as a receiver for CSI extraction and sample equalizer results from 2 RX?
The text was updated successfully, but these errors were encountered:
Could you send email to [email protected] to introduce your self?
Yes, already sent.
Our image is used directly or you build your own image?
use yours directly(openwifi-1.4.0-notter.img).
What is your own modification?
no modification.
Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
Ubuntu 20.04, window11 ,Just use openwifi-1.4.0-notter.img for Quick start.
Board/hardware type
zed_fmcs2
WiFi channel number
Default 5g(36)and 5g (48)
Steps to reproduce the issue, and the related error message, screenshot, etc
none
Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"
none
Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods
none
Any other thing we need to know for helping you better?
In the CSI extraction process, does it have to work in the full-duplex (Self-TX) mode? Can we set it as a receiver to obtain CSI?
If full-duplex mode is required, does the CSI extraction process only work for single RX sampling? The hardware platform we used is Xilinx Zed board + FMCOMMS3, which includes two Rx antennas.
If the above options are not available, can I modify the FPGA code in your project to enable the entire module to operate as a receiver for CSI extraction and sample equalizer results from 2 RX?
The text was updated successfully, but these errors were encountered: