diff --git a/Kconfig.dependencies b/Kconfig.dependencies index 6557c01ce6..16ddd9fdb9 100644 --- a/Kconfig.dependencies +++ b/Kconfig.dependencies @@ -26,6 +26,11 @@ config SIDEWALK_TFM_SUPPORT select EXPERIMENTAL default SIDEWALK && BUILD_WITH_TFM +config SIDEWALK_NRF54L10_SUPPORT + bool "Sidewalk support for nRF54L10 [EXPERIMENTAL]" + select EXPERIMENTAL + default SIDEWALK && SOC_NRF54L10 + config SIDEWALK_BLE bool default SIDEWALK @@ -107,7 +112,7 @@ choice CC3XX_LOCK_VARIANT endchoice config PSA_WANT_ALG_SHA_512 - default y if SOC_NRF54L15 + default y if SOC_SERIES_NRF54LX config PSA_WANT_ALG_CHACHA20_POLY1305 default n diff --git a/samples/sid_end_device/Kconfig.sysbuild b/samples/sid_end_device/Kconfig.sysbuild index 11639dd900..3a3e22188d 100644 --- a/samples/sid_end_device/Kconfig.sysbuild +++ b/samples/sid_end_device/Kconfig.sysbuild @@ -25,7 +25,7 @@ config DFU_MULTI_IMAGE_PACKAGE_APP default y config PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY - default y if BOARD_NRF52840DK_NRF52840 || BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP + default y if !BOARD_NRF54L15DK_NRF54L15_CPUAPP || !BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS if (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP) @@ -50,7 +50,7 @@ config DFU_MULTI_IMAGE_PACKAGE_NET endif # (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP) -if (BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS) +if (BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP) # TODO: NCSDK-28931: Cannot use fprotect twice, so disable it in MCUboot to # test protecting factory data. It can be enabled while there is a support diff --git a/samples/sid_end_device/boards/nrf54l15dk_nrf54l10_cpuapp.conf b/samples/sid_end_device/boards/nrf54l15dk_nrf54l10_cpuapp.conf new file mode 100644 index 0000000000..a60ac39009 --- /dev/null +++ b/samples/sid_end_device/boards/nrf54l15dk_nrf54l10_cpuapp.conf @@ -0,0 +1,14 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +CONFIG_POWEROFF=y + +# nRF54L15DK uses SPI NOR external flash for DFU +CONFIG_SPI=y +CONFIG_SPI_NOR=y +CONFIG_MULTITHREADING=y +CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y +CONFIG_MCUMGR_GRP_IMG_ALLOW_ERASE_PENDING=y diff --git a/samples/sid_end_device/boards/nrf54l15dk_nrf54l10_cpuapp.overlay b/samples/sid_end_device/boards/nrf54l15dk_nrf54l10_cpuapp.overlay new file mode 100644 index 0000000000..193ee34073 --- /dev/null +++ b/samples/sid_end_device/boards/nrf54l15dk_nrf54l10_cpuapp.overlay @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/{ + aliases { + state-notifier-connected = &led0; + state-notifier-time-sync = &led1; + state-notifier-registered = &led2; + state-notifier-working = &led3; + }; + + semtech_sx1262_gpios{ + compatible = "gpio-keys"; + semtech_sx1262_reset_gpios: reset { + gpios = <&gpio2 8 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>; + label = "semtech_sx1262 Reset"; + }; + semtech_sx1262_busy_gpios: busy { + gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH)>; + label = "semtech_sx1262 Busy"; + }; + semtech_sx1262_antenna_enable_gpios: antena_enable { + gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH)>; + label = "semtech_sx1262 Antena Enable"; + }; + semtech_sx1262_dio1_gpios: dio1 { + gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH|GPIO_PULL_DOWN)>; + label = "semtech_sx1262 DIO1"; + }; + }; + + chosen { + nordic,pm-ext-flash = &mx25r64; + }; +}; + +sid_semtech: &spi30 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi30_default_alt>; + pinctrl-1 = <&spi30_sleep_alt>; + pinctrl-names = "default", "sleep"; + clock-frequency = ; +}; + +&cpuapp_rram { + reg = <0x0 DT_SIZE_K(1024)>; +}; + +&cpuapp_sram { + reg = <0x20000000 DT_SIZE_K(192)>; + ranges = <0x0 0x20000000 DT_SIZE_K(192)>; +}; + +&pinctrl { + spi30_default_alt: spi30_default_alt { + group1 { + psels = , + , + ; + }; + }; + + spi30_sleep_alt: spi30_sleep_alt { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; + +&adc { + status = "disabled"; +}; +&uart21 { + status = "disabled"; +}; +&pwm20 { + status = "disabled"; +}; +&i2c20 { + status = "disabled"; +}; +&spi20 { + status = "disabled"; +}; +&spi22 { + status = "disabled"; +}; +&mx25r64 { + status = "okay"; +}; + +// TODO: re-enable HWFC once it's fixed +&uart20 { + /delete-property/ hw-flow-control; +}; diff --git a/samples/sid_end_device/pm_static_nrf54l15dk_nrf54l10_cpuapp.yml b/samples/sid_end_device/pm_static_nrf54l15dk_nrf54l10_cpuapp.yml new file mode 100644 index 0000000000..ada6b15dff --- /dev/null +++ b/samples/sid_end_device/pm_static_nrf54l15dk_nrf54l10_cpuapp.yml @@ -0,0 +1,63 @@ +app: + address: 0xc800 + end_address: 0xfd000 + region: flash_primary + size: 0xf0800 +mcuboot: + address: 0x0 + end_address: 0xc000 + placement: + before: + - mcuboot_primary + region: flash_primary + size: 0xc000 +mcuboot_pad: + address: 0xc000 + end_address: 0xc800 + placement: + before: + - mcuboot_primary_app + region: flash_primary + size: 0x800 +mcuboot_primary: + address: 0xc000 + end_address: 0xfd000 + orig_span: &id001 + - mcuboot_pad + - app + region: flash_primary + size: 0xf1000 + span: *id001 +mcuboot_primary_app: + address: 0xc800 + end_address: 0xfd000 + orig_span: &id002 + - app + region: flash_primary + size: 0xf0800 + span: *id002 +settings_storage: + address: 0xfd000 + end_address: 0xff000 + placement: + align: + start: 0x1000 + before: + - end + region: flash_primary + size: 0x2000 +mfg_storage: + address: 0xff000 + end_address: 0x100000 + region: flash_primary + size: 0x1000 +mcuboot_secondary: + address: 0x0 + end_address: 0xf1000 + placement: + align: + start: 0x4 + region: external_flash + share_size: + - mcuboot_primary + size: 0xf1000 diff --git a/samples/sid_end_device/sample.yaml b/samples/sid_end_device/sample.yaml index 05845cf93e..4c44850517 100644 --- a/samples/sid_end_device/sample.yaml +++ b/samples/sid_end_device/sample.yaml @@ -9,11 +9,13 @@ common: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tests: sample.sidewalk.hello: extra_configs: diff --git a/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.conf b/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.conf new file mode 100644 index 0000000000..9f6d267f41 --- /dev/null +++ b/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.conf @@ -0,0 +1,34 @@ +# +# Copyright (c) 2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +# TODO: NCSDK-28931: Cannot use fprotect twice, so disable it in MCUboot to +# test protecting factory data. It can be enabled while there is a support +# for protection more than one region. +CONFIG_FPROTECT=n + +# TODO: Workaround, disable memory guard to avoid false faults in application after boot +CONFIG_HW_STACK_PROTECTION=n + +# Currently, without tickless kernel, the SYSCOUNTER value after the software +# reset is not set properly and due to that the first system interrupt is not called +# in the proper time - the SYSCOUNTER value is set to the value from before +# reset + 1. Hence, the reboot time increases more and more. +# To avoid it enable tickles kernel for mcuboot. +CONFIG_TICKLESS_KERNEL=y + +CONFIG_BOOT_WATCHDOG_FEED=n + +CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y + +# nRF54L15DK uses SPI NOR external flash +CONFIG_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_NOR=y +CONFIG_SPI_NOR_SFDP_DEVICETREE=y +CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096 + +# required by SPI driver +CONFIG_MULTITHREADING=y diff --git a/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.overlay b/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.overlay new file mode 100644 index 0000000000..aa7d4b0cf6 --- /dev/null +++ b/samples/sid_end_device/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.overlay @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/ { + chosen { + nordic,pm-ext-flash = &mx25r64; + }; +}; + +/* Application does not use cpuflpr core. Assign whole RRAM and RAM to cpuapp. */ +&cpuapp_rram { + reg = <0x0 DT_SIZE_K(1024)>; +}; + +&cpuapp_sram { + reg = <0x20000000 DT_SIZE_K(192)>; + ranges = <0x0 0x20000000 DT_SIZE_K(192)>; +}; + +&mx25r64 { + status = "okay"; +}; diff --git a/subsys/sal/sid_pal/src/sid_ble_advert.c b/subsys/sal/sid_pal/src/sid_ble_advert.c index 4dfc790385..4f86c180f0 100644 --- a/subsys/sal/sid_pal/src/sid_ble_advert.c +++ b/subsys/sal/sid_pal/src/sid_ble_advert.c @@ -192,7 +192,7 @@ int sid_ble_advert_deinit(void) void sid_ble_advert_notify_connection(void) { - LOG_INF("Conneciton has been made, cancel change adv"); + LOG_DBG("Conneciton has been made, cancel change adv"); k_work_cancel_delayable(&change_adv_work); } diff --git a/subsys/sal/sid_pal/src/sid_mfg_storage.c b/subsys/sal/sid_pal/src/sid_mfg_storage.c index 68aeabb888..fed9a00f99 100644 --- a/subsys/sal/sid_pal/src/sid_mfg_storage.c +++ b/subsys/sal/sid_pal/src/sid_mfg_storage.c @@ -44,7 +44,7 @@ static int sid_mfg_storage_secure_read(uint16_t *p_value, uint8_t *buffer, uint1 #elif defined(NRF_NETWORK) #define DEV_ID_REG (uint32_t)(NRF_FICR_NS->INFO.DEVICEID[0]) #endif /* NRF5340_XXAA */ -#elif defined(NRF54L15_ENGA_XXAA) || defined(NRF54L15_XXAA) +#elif defined(NRF54L10_XXAA) || defined(NRF54L15_XXAA) #define DEV_ID_REG (uint32_t)(NRF_FICR->INFO.DEVICEID[0]) #else #error "Unknow Device ID register." diff --git a/tests/functional/critical_region/testcase.yaml b/tests/functional/critical_region/testcase.yaml index 235b75c488..27ac7968aa 100644 --- a/tests/functional/critical_region/testcase.yaml +++ b/tests/functional/critical_region/testcase.yaml @@ -6,8 +6,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/functional/crypto/src/main.c b/tests/functional/crypto/src/main.c index 52aa76e29b..0926a68e9b 100644 --- a/tests/functional/crypto/src/main.c +++ b/tests/functional/crypto/src/main.c @@ -300,7 +300,7 @@ ZTEST(crypto, test_sid_pal_crypto_hash_256) zassert_equal(SID_ERROR_OUT_OF_RESOURCES, sid_pal_crypto_hash(¶ms)); } -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) ZTEST(crypto, test_sid_pal_crypto_hash_512) { @@ -375,7 +375,7 @@ ZTEST(crypto, test_sid_pal_crypto_hash_512) zassert_equal(SID_ERROR_NONE, sid_pal_crypto_hash(¶ms)); } -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ /********************************************** * HMAC @@ -516,7 +516,7 @@ ZTEST(crypto, test_sid_pal_crypto_hmac_sha256_fake_key) zassert_not_equal(0, memcmp(openssl_test_hmac_sha256_vector, digest, SHA256_LEN)); } -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) ZTEST(crypto, test_sid_pal_crypto_hmac_sha512) { sid_pal_hmac_params_t params; @@ -636,7 +636,7 @@ ZTEST(crypto, test_sid_pal_crypto_hmac_sha512_fake_key) zassert_not_equal(0, memcmp(openssl_test_hmac_sha512_vector, digest, SHA512_LEN)); } -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ /********************************************** * END HMAC @@ -2016,7 +2016,9 @@ ZTEST(crypto, test_sid_pal_crypto_ecc_dsa) params.mode = SID_PAL_CRYPTO_VERIFY; params.key = public_Ed25519; params.key_size = sizeof(public_Ed25519); - zassert_equal(SID_ERROR_NONE, sid_pal_crypto_ecc_dsa(¶ms)); + sid_error_t ret = sid_pal_crypto_ecc_dsa(¶ms); + printk("ret: %d\n", ret); + zassert_equal(SID_ERROR_NONE, ret); // Bad public key params.key = fake_public_SECP256R1; diff --git a/tests/functional/crypto/testcase.yaml b/tests/functional/crypto/testcase.yaml index 1752c8e771..9ee76969b1 100644 --- a/tests/functional/crypto/testcase.yaml +++ b/tests/functional/crypto/testcase.yaml @@ -7,8 +7,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/functional/crypto_keys/testcase.yaml b/tests/functional/crypto_keys/testcase.yaml index 472bbf19d7..69ad53855c 100644 --- a/tests/functional/crypto_keys/testcase.yaml +++ b/tests/functional/crypto_keys/testcase.yaml @@ -7,8 +7,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/functional/interrupts/testcase.yaml b/tests/functional/interrupts/testcase.yaml index f0a9c0312c..2b464b3548 100644 --- a/tests/functional/interrupts/testcase.yaml +++ b/tests/functional/interrupts/testcase.yaml @@ -7,8 +7,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/functional/mfg_storage/testcase.yaml b/tests/functional/mfg_storage/testcase.yaml index 6adc684a3e..19459cfe90 100644 --- a/tests/functional/mfg_storage/testcase.yaml +++ b/tests/functional/mfg_storage/testcase.yaml @@ -8,11 +8,13 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp sidewalk.functional.mfg_storage_deprecated: skip: true diff --git a/tests/functional/pal_delay/testcase.yaml b/tests/functional/pal_delay/testcase.yaml index 34a2016293..7036873df7 100644 --- a/tests/functional/pal_delay/testcase.yaml +++ b/tests/functional/pal_delay/testcase.yaml @@ -6,9 +6,11 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/functional/spi_bus/testcase.yaml b/tests/functional/spi_bus/testcase.yaml index 9ee99ae96e..65fac9d01c 100644 --- a/tests/functional/spi_bus/testcase.yaml +++ b/tests/functional/spi_bus/testcase.yaml @@ -6,11 +6,13 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk harness: ztest harness_config: diff --git a/tests/functional/storage/testcase.yaml b/tests/functional/storage/testcase.yaml index 5b5b49e268..b49f883356 100644 --- a/tests/functional/storage/testcase.yaml +++ b/tests/functional/storage/testcase.yaml @@ -7,8 +7,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/functional/temperature/testcase.yaml b/tests/functional/temperature/testcase.yaml index fa5216842a..a250fc537d 100644 --- a/tests/functional/temperature/testcase.yaml +++ b/tests/functional/temperature/testcase.yaml @@ -6,9 +6,11 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/functional/time/testcase.yaml b/tests/functional/time/testcase.yaml index 79ba488782..7a1eeb6a39 100644 --- a/tests/functional/time/testcase.yaml +++ b/tests/functional/time/testcase.yaml @@ -7,8 +7,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/manual/ble/sample.yaml b/tests/manual/ble/sample.yaml index 13826947ce..bc17ecb6b0 100644 --- a/tests/manual/ble/sample.yaml +++ b/tests/manual/ble/sample.yaml @@ -9,10 +9,12 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp build_only: true integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/manual/log/sample.yaml b/tests/manual/log/sample.yaml index 71031cdda8..5de3ea82d7 100644 --- a/tests/manual/log/sample.yaml +++ b/tests/manual/log/sample.yaml @@ -9,10 +9,12 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp build_only: true integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/manual/simple_bootloader/boards/nrf54l15dk_nrf54l10_cpuapp.overlay b/tests/manual/simple_bootloader/boards/nrf54l15dk_nrf54l10_cpuapp.overlay new file mode 100644 index 0000000000..a9ac0e8581 --- /dev/null +++ b/tests/manual/simple_bootloader/boards/nrf54l15dk_nrf54l10_cpuapp.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + + +/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */ +&cpuapp_rram { + reg = <0x0 DT_SIZE_K(1024)>; +}; + +&cpuapp_sram { + reg = <0x20000000 DT_SIZE_K(192)>; + ranges = <0x0 0x20000000 DT_SIZE_K(192)>; +}; diff --git a/tests/manual/simple_bootloader/pm_static_nrf54l15dk_nrf54l10_cpuapp.yml b/tests/manual/simple_bootloader/pm_static_nrf54l15dk_nrf54l10_cpuapp.yml new file mode 100644 index 0000000000..a40110ef00 --- /dev/null +++ b/tests/manual/simple_bootloader/pm_static_nrf54l15dk_nrf54l10_cpuapp.yml @@ -0,0 +1,66 @@ +app: + address: 0xc800 + end_address: 0x84800 + region: flash_primary + size: 0x78000 +mcuboot: + address: 0x0 + end_address: 0xc000 + placement: + before: + - mcuboot_primary + region: flash_primary + size: 0xc000 +mcuboot_pad: + address: 0xc000 + end_address: 0xc800 + placement: + before: + - mcuboot_primary_app + region: flash_primary + size: 0x800 +mcuboot_primary: + address: 0xc000 + end_address: 0x84800 + orig_span: &id001 + - mcuboot_pad + - app + region: flash_primary + sharers: 0x1 + size: 0x78800 + span: *id001 +mcuboot_primary_app: + address: 0xc800 + end_address: 0x84800 + orig_span: &id002 + - app + region: flash_primary + size: 0x78000 + span: *id002 +mcuboot_secondary: + address: 0x84800 + end_address: 0xfd000 + placement: + after: + - mcuboot_primary + align: + start: 0x1000 + region: flash_primary + share_size: + - mcuboot_primary + size: 0x78800 +mfg_storage: + address: 0xff000 + end_address: 0x100000 + region: flash_primary + size: 0x1000 +settings_storage: + address: 0xfd000 + end_address: 0xff000 + placement: + align: + start: 0x1000 + before: + - end + region: flash_primary + size: 0x2000 diff --git a/tests/manual/simple_bootloader/sample.yaml b/tests/manual/simple_bootloader/sample.yaml index 4e12a51a05..f6443c67de 100644 --- a/tests/manual/simple_bootloader/sample.yaml +++ b/tests/manual/simple_bootloader/sample.yaml @@ -10,9 +10,11 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/manual/simple_bootloader/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.conf b/tests/manual/simple_bootloader/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.conf new file mode 100644 index 0000000000..de78cc2fc2 --- /dev/null +++ b/tests/manual/simple_bootloader/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.conf @@ -0,0 +1,54 @@ +# +# Copyright (c) 2021 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +# TODO: NCSDK-28931: Cannot use fprotect twice, so disable it in MCUboot to +# test protecting Matter factory data. It can be enabled while there is a support +# for protection more than one region. +CONFIG_FPROTECT=n +# TODO: Workaround, disable memory guard to avoid false faults in application after boot +CONFIG_HW_STACK_PROTECTION=n + +CONFIG_BOOT_WATCHDOG_FEED=n + +# Disable all debug features +CONFIG_USE_SEGGER_RTT=n +CONFIG_SHELL=n +CONFIG_OPENTHREAD_SHELL=n +CONFIG_CONSOLE=n +CONFIG_UART_CONSOLE=n +CONFIG_SERIAL=n +CONFIG_LOG=n +CONFIG_LOG_MODE_MINIMAL=n +CONFIG_ASSERT_VERBOSE=n +CONFIG_ASSERT_NO_FILE_INFO=y +CONFIG_PRINTK=n +CONFIG_PRINTK_SYNC=n +CONFIG_THREAD_NAME=n +CONFIG_BOOT_BANNER=n + +CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y + +# Ensure that the qspi driver is disabled by default +CONFIG_GPIO=n +CONFIG_SPI=n +CONFIG_SPI_NOR=n +CONFIG_NORDIC_QSPI_NOR=n +CONFIG_MULTITHREADING=n + +CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y + + +# Workaroud: fprotect and watchdog feed +# are not supported in NCS v2.6.0 +CONFIG_FPROTECT=n +CONFIG_BOOT_WATCHDOG_FEED=n + +# Currently, without tickless kernel, the SYSCOUNTER value after the software +# reset is not set properly and due to that the first system interrupt is not called +# in the proper time - the SYSCOUNTER value is set to the value from before +# reset + 1. Hence, the reboot time increases more and more. +# To avoid it enable tickles kernel for mcuboot. +CONFIG_TICKLESS_KERNEL=y diff --git a/tests/manual/simple_bootloader/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.overlay b/tests/manual/simple_bootloader/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.overlay new file mode 100644 index 0000000000..a9ac0e8581 --- /dev/null +++ b/tests/manual/simple_bootloader/sysbuild/mcuboot/boards/nrf54l15dk_nrf54l10_cpuapp.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + + +/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */ +&cpuapp_rram { + reg = <0x0 DT_SIZE_K(1024)>; +}; + +&cpuapp_sram { + reg = <0x20000000 DT_SIZE_K(192)>; + ranges = <0x0 0x20000000 DT_SIZE_K(192)>; +}; diff --git a/tests/unit_tests/mfg_parsers/testcase.yaml b/tests/unit_tests/mfg_parsers/testcase.yaml index e5be7d1ce9..872f09e2a8 100644 --- a/tests/unit_tests/mfg_parsers/testcase.yaml +++ b/tests/unit_tests/mfg_parsers/testcase.yaml @@ -6,12 +6,14 @@ tests: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk integration_platforms: - native_posix - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp + - nrf54l15dk/nrf54l10/cpuapp sidewalk.unit_tests.mfg_parser_psa_storage: sysbuild: true diff --git a/tests/unit_tests/sid_ace_alloc/testcase.yaml b/tests/unit_tests/sid_ace_alloc/testcase.yaml index 24909a6eda..7232bc8098 100644 --- a/tests/unit_tests/sid_ace_alloc/testcase.yaml +++ b/tests/unit_tests/sid_ace_alloc/testcase.yaml @@ -6,8 +6,10 @@ tests: - nrf5340dk/nrf5340/cpuapp - native_posix - nrf54l15dk/nrf54l15/cpuapp + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk integration_platforms: - native_posix - nrf52840dk/nrf52840 - nrf54l15dk/nrf54l15/cpuapp + - nrf54l15dk/nrf54l10/cpuapp diff --git a/tests/validation/crypto/src/main.c b/tests/validation/crypto/src/main.c index 6c64889d7d..c5d181dc46 100644 --- a/tests/validation/crypto/src/main.c +++ b/tests/validation/crypto/src/main.c @@ -21,7 +21,7 @@ static const uint8_t sha256_result[SHA256_SZ] = { 0x16, 0xf6, 0x09, 0xe1, 0x5f, 0xab, 0x45, 0xf5, 0xb9, 0x90, 0x36, 0x05, 0x06, 0x8e, 0xd9, 0x8c, 0xc0, 0xdf, 0x97, 0xf6, 0x22 }; -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) static const uint8_t sha512_result[SHA512_SZ] = { 0x08, 0x89, 0x42, 0x97, 0x01, 0x29, 0x4b, 0x44, 0xa8, 0x02, 0xba, 0xf5, 0xff, @@ -31,7 +31,7 @@ static const uint8_t sha512_result[SHA512_SZ] = { 0xf9, 0xe0, 0xdc, 0xce, 0xea, 0x27, 0xd5, 0x86, 0xf1, 0x4c, 0x3b, 0x9e }; -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ static const uint8_t hmac_hash_string[] = "halo_crypto_test_run_hmac"; @@ -48,7 +48,7 @@ static const uint8_t hmac_sha256_result[SHA256_SZ] = { 0xfd, 0x71, 0x58, 0xaa, 0 0x51, 0xe9, 0x8a, 0xcd, 0xf5, 0x97, 0xd6, 0x73, 0xf1, 0xea, 0x33 }; -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) static const uint8_t hmac_sha512_result[SHA512_SZ] = { 0x64, 0x84, 0xa8, 0x5b, 0x48, 0x62, 0x41, 0xa6, 0xbf, 0x2e, 0xff, 0xe6, 0xed, @@ -58,7 +58,7 @@ static const uint8_t hmac_sha512_result[SHA512_SZ] = { 0x3a, 0x31, 0xde, 0xec, 0xc9, 0x6a, 0x81, 0xd4, 0xce, 0x0d, 0x5c, 0x5d }; -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ // Test vector // https://tools.ietf.org/html/rfc4493 @@ -1104,7 +1104,7 @@ ZTEST(crypto, test_hash_positive) zassert_equal(SID_ERROR_NONE, ret); zassert_equal(0, memcmp(out_buf, sha256_result, hash_params.digest_size)); -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) hash_params.algo = SID_PAL_HASH_SHA512; hash_params.digest_size = SHA512_SZ; @@ -1112,7 +1112,7 @@ ZTEST(crypto, test_hash_positive) zassert_equal(SID_ERROR_NONE, ret); zassert_equal(0, memcmp(out_buf, sha512_result, hash_params.digest_size)); -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ } ZTEST(crypto, test_hash_invalid_param_sha256) @@ -1143,7 +1143,7 @@ ZTEST(crypto, test_hmac_positive) zassert_equal(SID_ERROR_NONE, ret); zassert_equal(0, memcmp(out_buf, hmac_sha256_result, hmac_params.digest_size)); -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) hmac_params.algo = SID_PAL_HASH_SHA512; hmac_params.digest_size = SHA512_SZ; @@ -1151,7 +1151,7 @@ ZTEST(crypto, test_hmac_positive) zassert_equal(SID_ERROR_NONE, ret); zassert_equal(0, memcmp(out_buf, hmac_sha512_result, hmac_params.digest_size)); -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ } ZTEST(crypto, test_hmac_invalid_param_sha256) @@ -1182,7 +1182,7 @@ ZTEST(crypto, test_hmac_negative) zassert_equal(SID_ERROR_NONE, ret); zassert_not_equal(0, memcmp(out_buf, hmac_sha256_result, hmac_params.digest_size)); -#if defined(CONFIG_SOC_NRF54L15) +#if defined(CONFIG_SOC_SERIES_NRF54LX) hmac_params.algo = SID_PAL_HASH_SHA512; hmac_params.digest_size = SHA512_SZ; @@ -1190,7 +1190,7 @@ ZTEST(crypto, test_hmac_negative) zassert_equal(SID_ERROR_NONE, ret); zassert_not_equal(0, memcmp(out_buf, hmac_sha512_result, hmac_params.digest_size)); -#endif /* CONFIG_SOC_NRF54L15 */ +#endif /* CONFIG_SOC_SERIES_NRF54LX */ } ZTEST(crypto, test_cmac_positive) diff --git a/tests/validation/crypto/testcase.yaml b/tests/validation/crypto/testcase.yaml index 2378ab46a2..f761b2ca73 100644 --- a/tests/validation/crypto/testcase.yaml +++ b/tests/validation/crypto/testcase.yaml @@ -6,9 +6,11 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/validation/storage_kv/testcase.yaml b/tests/validation/storage_kv/testcase.yaml index 77311f7a30..66fecb12ca 100644 --- a/tests/validation/storage_kv/testcase.yaml +++ b/tests/validation/storage_kv/testcase.yaml @@ -6,9 +6,11 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/tests/validation/timer/testcase.yaml b/tests/validation/timer/testcase.yaml index a95cde433d..3dbf9b992e 100644 --- a/tests/validation/timer/testcase.yaml +++ b/tests/validation/timer/testcase.yaml @@ -6,9 +6,11 @@ tests: - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp integration_platforms: - nrf52840dk/nrf52840 - nrf5340dk/nrf5340/cpuapp - nrf54l15dk/nrf54l15/cpuapp - nrf54l15dk/nrf54l15/cpuapp/ns + - nrf54l15dk/nrf54l10/cpuapp tags: Sidewalk diff --git a/utils/sidewalk_dfu/Kconfig b/utils/sidewalk_dfu/Kconfig index ae392d068b..e1662ae1e7 100644 --- a/utils/sidewalk_dfu/Kconfig +++ b/utils/sidewalk_dfu/Kconfig @@ -25,7 +25,7 @@ config SIDEWALK_DFU_BOOTLOADER imply EXTRA_EXCEPTION_INFO config SIDEWALK_DFU_SERVICE_BLE - bool "DFU sericve over BLE" + bool "DFU service over BLE" default SIDEWALK_DFU imply MCUMGR imply MCUMGR_GRP_IMG diff --git a/utils/state_notifier/state_notifier_gpio_backend.c b/utils/state_notifier/state_notifier_gpio_backend.c index 7d576f57ce..c70c8ed01c 100644 --- a/utils/state_notifier/state_notifier_gpio_backend.c +++ b/utils/state_notifier/state_notifier_gpio_backend.c @@ -33,7 +33,7 @@ static void gpio_enumerate_state(enum application_state state_id, uint32_t value return; } -#if defined(NRF54L15_ENGA_XXAA) || defined(NRF54L15_XXAA) +#if defined(NRF54L15_ENGA_XXAA) || defined(NRF54L15_XXAA) || defined(NRF54L10_XXAA) gpio_pin_set_raw(gpio.port, gpio.pin, value); #else /* output activated with low state */