board2.RUL

DRC Rules Export File for PCB: D:\SVN_neu\AA_SVN_cleaned_up_projects\3_FPGA_box_V2\FPGA_Frontpanel_2_V2\board2.PcbDoc
RuleKind=Clearance|RuleName=Clearance_1|Scope=Board|Minimum=8.00
RuleKind=Clearance|RuleName=clearance_polygons|Scope=Board|Minimum=59.06
RuleKind=Width|RuleName=Width_HC_class|Scope=Board|Minimum=60.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=Width|RuleName=Width_HP_class|Scope=Board|Minimum=40.00
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width_24V class|Scope=Board|Minimum=30.00
RuleKind=Clearance|RuleName=clearance_24V class|Scope=Board|Minimum=10.00
RuleKind=Clearance|RuleName=clearance_HP_class|Scope=Board|Minimum=15.00
RuleKind=Width|RuleName=Width_1|Scope=Board|Minimum=60.00
RuleKind=Width|RuleName=WidthRoom|Scope=Board|Minimum=11.81
RuleKind=Clearance|RuleName=ClearanceRoom|Scope=Board|Minimum=5.91