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I2C design #10
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A separate data buffers for slave and master mode shall be used.
Another problem I found is not checking if I2C interface is free before sending and not validating against arbitration lost. |
The 8us (until semaphore is taken in xI2CSlaveTransfer) is most critical one. A received data is not protected against transmission started by MMC (event???) or next start from MCH (request after event response). |
Maybe a solution to lower the delays between semaphores being released/taken is to change them to Task Notifications, which, according to FreeRTOS spec, are way faster than the Semaphore API. |
Actually, that's how it is implemented in the custom I2C ISR functions, so the semaphore that's taking so long to be taken/released is the Mutex? |
Now using LPCOpen I2C driver functions, just masked as xI2C*** so other target uC can implement their own if they need. |
Timing should be tested again with the new implementation |
I guess it may miss some transfer made by MCH after master transfers because slave mode is enabled again not in interrupt routing but in user context. Tests I made in Juli confirmed this. That's why I made modifications to handleMasterXferState and added Chip_I2C_MasterTransferXfer (https://github.com/qermit/AFC-Loader/blob/master/src/chip/src/i2c_17xx_40xx.c) |
First of all I fixed badly designed mutex handling in commit: qermit/afcipm@49c5959
It was to prevent other tasks changing this shared structure.
I've also introduced a initial i2c multiplexer handling.
In this case memory copy is just waist of resources and limits usage of I2C bus function in a master mode. Just pointer to rx/tx data shall be assigned while only one task may take ownership over I2C bus.
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