SAMD51 clock system stalls in -O2 and above

[jnaulet]

This is related to issue #19
We might have to implement some variant of activate wait, like delay_us() or delay_ms() for every arch & every clock speed.

This is not that obvious withotu a massive refactoring, unless maybe arch_counter() might be used differently (as a freerunnning counter, similar to MIPS and RISC-V).

[jnaulet]

Here's a possible workaround: let the clock driver allow to wait for a certain number of cycles / ns.
This won't fix the sync between clock domains that occur on almost any sam related driver, though.