mirror of https://github.com/jkjoy/sunpeiwen.git
550 lines
11 KiB
JavaScript
550 lines
11 KiB
JavaScript
/*
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Language: Verilog
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Author: Jon Evans <jon@craftyjon.com>
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Contributors: Boone Severson <boone.severson@gmail.com>
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Description: Verilog is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. This highlighter supports Verilog and SystemVerilog through IEEE 1800-2012.
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Website: http://www.verilog.com
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*/
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function verilog(hljs) {
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const regex = hljs.regex;
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const KEYWORDS = {
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$pattern: /\$?[\w]+(\$[\w]+)*/,
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keyword: [
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"accept_on",
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"alias",
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"always",
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"always_comb",
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"always_ff",
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"always_latch",
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"and",
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"assert",
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"assign",
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"assume",
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"automatic",
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"before",
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"begin",
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"bind",
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"bins",
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"binsof",
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"bit",
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"break",
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"buf|0",
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"bufif0",
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"bufif1",
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"byte",
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"case",
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"casex",
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"casez",
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"cell",
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"chandle",
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"checker",
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"class",
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"clocking",
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"cmos",
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"config",
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"const",
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"constraint",
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"context",
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"continue",
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"cover",
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"covergroup",
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"coverpoint",
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"cross",
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"deassign",
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"default",
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"defparam",
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"design",
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"disable",
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"dist",
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"do",
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"edge",
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"else",
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"end",
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"endcase",
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"endchecker",
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"endclass",
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"endclocking",
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"endconfig",
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"endfunction",
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"endgenerate",
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"endgroup",
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"endinterface",
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"endmodule",
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"endpackage",
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"endprimitive",
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"endprogram",
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"endproperty",
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"endspecify",
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"endsequence",
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"endtable",
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"endtask",
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"enum",
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"event",
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"eventually",
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"expect",
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"export",
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"extends",
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"extern",
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"final",
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"first_match",
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"for",
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"force",
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"foreach",
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"forever",
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"fork",
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"forkjoin",
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"function",
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"generate|5",
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"genvar",
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"global",
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"highz0",
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"highz1",
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"if",
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"iff",
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"ifnone",
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"ignore_bins",
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"illegal_bins",
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"implements",
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"implies",
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"import",
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"incdir",
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"include",
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"initial",
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"inout",
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"input",
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"inside",
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"instance",
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"int",
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"integer",
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"interconnect",
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"interface",
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"intersect",
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"join",
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"join_any",
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"join_none",
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"large",
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"let",
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"liblist",
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"library",
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"local",
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"localparam",
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"logic",
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"longint",
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"macromodule",
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"matches",
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"medium",
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"modport",
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"module",
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"nand",
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"negedge",
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"nettype",
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"new",
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"nexttime",
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"nmos",
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"nor",
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"noshowcancelled",
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"not",
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"notif0",
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"notif1",
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"or",
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"output",
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"package",
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"packed",
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"parameter",
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"pmos",
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"posedge",
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"primitive",
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"priority",
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"program",
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"property",
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"protected",
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"pull0",
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"pull1",
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"pulldown",
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"pullup",
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"pulsestyle_ondetect",
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"pulsestyle_onevent",
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"pure",
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"rand",
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"randc",
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"randcase",
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"randsequence",
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"rcmos",
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"real",
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"realtime",
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"ref",
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"reg",
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"reject_on",
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"release",
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"repeat",
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"restrict",
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"return",
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"rnmos",
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"rpmos",
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"rtran",
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"rtranif0",
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"rtranif1",
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"s_always",
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"s_eventually",
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"s_nexttime",
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"s_until",
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"s_until_with",
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"scalared",
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"sequence",
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"shortint",
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"shortreal",
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"showcancelled",
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"signed",
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"small",
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"soft",
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"solve",
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"specify",
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"specparam",
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"static",
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"string",
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"strong",
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"strong0",
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"strong1",
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"struct",
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"super",
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"supply0",
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"supply1",
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"sync_accept_on",
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"sync_reject_on",
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"table",
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"tagged",
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"task",
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"this",
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"throughout",
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"time",
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"timeprecision",
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"timeunit",
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"tran",
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"tranif0",
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"tranif1",
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"tri",
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"tri0",
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"tri1",
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"triand",
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"trior",
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"trireg",
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"type",
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"typedef",
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"union",
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"unique",
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"unique0",
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"unsigned",
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"until",
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"until_with",
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"untyped",
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"use",
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"uwire",
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"var",
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"vectored",
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"virtual",
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"void",
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"wait",
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"wait_order",
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"wand",
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"weak",
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"weak0",
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"weak1",
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"while",
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"wildcard",
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"wire",
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"with",
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"within",
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"wor",
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"xnor",
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"xor"
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],
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literal: [ 'null' ],
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built_in: [
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"$finish",
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"$stop",
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"$exit",
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"$fatal",
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"$error",
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"$warning",
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"$info",
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"$realtime",
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"$time",
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"$printtimescale",
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"$bitstoreal",
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"$bitstoshortreal",
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"$itor",
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"$signed",
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"$cast",
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"$bits",
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"$stime",
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"$timeformat",
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"$realtobits",
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"$shortrealtobits",
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"$rtoi",
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"$unsigned",
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"$asserton",
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"$assertkill",
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"$assertpasson",
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"$assertfailon",
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"$assertnonvacuouson",
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"$assertoff",
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"$assertcontrol",
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"$assertpassoff",
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"$assertfailoff",
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"$assertvacuousoff",
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"$isunbounded",
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"$sampled",
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"$fell",
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"$changed",
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"$past_gclk",
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"$fell_gclk",
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"$changed_gclk",
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"$rising_gclk",
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"$steady_gclk",
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"$coverage_control",
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"$coverage_get",
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"$coverage_save",
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"$set_coverage_db_name",
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"$rose",
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"$stable",
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"$past",
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"$rose_gclk",
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"$stable_gclk",
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"$future_gclk",
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"$falling_gclk",
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"$changing_gclk",
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"$display",
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"$coverage_get_max",
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"$coverage_merge",
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"$get_coverage",
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"$load_coverage_db",
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"$typename",
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"$unpacked_dimensions",
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"$left",
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"$low",
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"$increment",
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"$clog2",
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"$ln",
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"$log10",
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"$exp",
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"$sqrt",
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"$pow",
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"$floor",
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"$ceil",
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"$sin",
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"$cos",
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"$tan",
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"$countbits",
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"$onehot",
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"$isunknown",
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"$fatal",
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"$warning",
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"$dimensions",
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"$right",
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"$high",
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"$size",
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"$asin",
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"$acos",
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"$atan",
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"$atan2",
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"$hypot",
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"$sinh",
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"$cosh",
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"$tanh",
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"$asinh",
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"$acosh",
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"$atanh",
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"$countones",
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"$onehot0",
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"$error",
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"$info",
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"$random",
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"$dist_chi_square",
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"$dist_erlang",
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"$dist_exponential",
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"$dist_normal",
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"$dist_poisson",
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"$dist_t",
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"$dist_uniform",
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"$q_initialize",
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"$q_remove",
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"$q_exam",
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"$async$and$array",
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"$async$nand$array",
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"$async$or$array",
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"$async$nor$array",
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"$sync$and$array",
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"$sync$nand$array",
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"$sync$or$array",
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"$sync$nor$array",
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"$q_add",
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"$q_full",
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"$psprintf",
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"$async$and$plane",
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"$async$nand$plane",
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"$async$or$plane",
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"$async$nor$plane",
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"$sync$and$plane",
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"$sync$nand$plane",
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"$sync$or$plane",
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"$sync$nor$plane",
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"$system",
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"$display",
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"$displayb",
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"$displayh",
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"$displayo",
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"$strobe",
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"$strobeb",
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"$strobeh",
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"$strobeo",
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"$write",
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"$readmemb",
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"$readmemh",
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"$writememh",
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"$value$plusargs",
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"$dumpvars",
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"$dumpon",
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"$dumplimit",
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"$dumpports",
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"$dumpportson",
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"$dumpportslimit",
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"$writeb",
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"$writeh",
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"$writeo",
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"$monitor",
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"$monitorb",
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"$monitorh",
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"$monitoro",
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"$writememb",
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"$dumpfile",
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"$dumpoff",
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"$dumpall",
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"$dumpflush",
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"$dumpportsoff",
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"$dumpportsall",
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"$dumpportsflush",
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"$fclose",
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"$fdisplay",
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"$fdisplayb",
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"$fdisplayh",
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"$fdisplayo",
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"$fstrobe",
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"$fstrobeb",
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"$fstrobeh",
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"$fstrobeo",
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"$swrite",
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"$swriteb",
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"$swriteh",
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"$swriteo",
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"$fscanf",
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"$fread",
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"$fseek",
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"$fflush",
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"$feof",
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"$fopen",
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"$fwrite",
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"$fwriteb",
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"$fwriteh",
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"$fwriteo",
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"$fmonitor",
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"$fmonitorb",
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"$fmonitorh",
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"$fmonitoro",
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"$sformat",
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"$sformatf",
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"$fgetc",
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"$ungetc",
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"$fgets",
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"$sscanf",
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"$rewind",
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"$ftell",
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"$ferror"
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]
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};
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const BUILT_IN_CONSTANTS = [
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"__FILE__",
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"__LINE__"
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];
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const DIRECTIVES = [
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"begin_keywords",
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"celldefine",
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"default_nettype",
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"default_decay_time",
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"default_trireg_strength",
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"define",
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"delay_mode_distributed",
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"delay_mode_path",
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"delay_mode_unit",
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"delay_mode_zero",
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"else",
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"elsif",
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"end_keywords",
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"endcelldefine",
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"endif",
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"ifdef",
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"ifndef",
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"include",
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"line",
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"nounconnected_drive",
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"pragma",
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"resetall",
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"timescale",
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"unconnected_drive",
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"undef",
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"undefineall"
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];
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return {
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name: 'Verilog',
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aliases: [
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'v',
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'sv',
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'svh'
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],
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case_insensitive: false,
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keywords: KEYWORDS,
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contains: [
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hljs.C_BLOCK_COMMENT_MODE,
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hljs.C_LINE_COMMENT_MODE,
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hljs.QUOTE_STRING_MODE,
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{
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scope: 'number',
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contains: [ hljs.BACKSLASH_ESCAPE ],
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variants: [
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{ begin: /\b((\d+'([bhodBHOD]))[0-9xzXZa-fA-F_]+)/ },
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{ begin: /\B(('([bhodBHOD]))[0-9xzXZa-fA-F_]+)/ },
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{ // decimal
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begin: /\b[0-9][0-9_]*/,
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relevance: 0
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}
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]
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},
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/* parameters to instances */
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{
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scope: 'variable',
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variants: [
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{ begin: '#\\((?!parameter).+\\)' },
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{
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begin: '\\.\\w+',
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relevance: 0
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}
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]
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},
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{
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scope: 'variable.constant',
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match: regex.concat(/`/, regex.either(...BUILT_IN_CONSTANTS)),
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},
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{
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scope: 'meta',
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begin: regex.concat(/`/, regex.either(...DIRECTIVES)),
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end: /$|\/\/|\/\*/,
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returnEnd: true,
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keywords: DIRECTIVES
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}
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]
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};
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}
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module.exports = verilog;
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