mirror of https://github.com/jkjoy/sunpeiwen.git
216 lines
4.0 KiB
JavaScript
216 lines
4.0 KiB
JavaScript
/*
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Language: VHDL
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Author: Igor Kalnitsky <igor@kalnitsky.org>
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Contributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>
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Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.
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Website: https://en.wikipedia.org/wiki/VHDL
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*/
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function vhdl(hljs) {
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// Regular expression for VHDL numeric literals.
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// Decimal literal:
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const INTEGER_RE = '\\d(_|\\d)*';
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const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;
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const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';
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// Based literal:
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const BASED_INTEGER_RE = '\\w+';
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const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';
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const NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';
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const KEYWORDS = [
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"abs",
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"access",
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"after",
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"alias",
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"all",
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"and",
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"architecture",
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"array",
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"assert",
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"assume",
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"assume_guarantee",
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"attribute",
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"begin",
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"block",
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"body",
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"buffer",
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"bus",
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"case",
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"component",
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"configuration",
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"constant",
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"context",
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"cover",
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"disconnect",
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"downto",
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"default",
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"else",
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"elsif",
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"end",
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"entity",
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"exit",
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"fairness",
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"file",
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"for",
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"force",
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"function",
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"generate",
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"generic",
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"group",
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"guarded",
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"if",
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"impure",
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"in",
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"inertial",
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"inout",
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"is",
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"label",
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"library",
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"linkage",
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"literal",
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"loop",
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"map",
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"mod",
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"nand",
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"new",
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"next",
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"nor",
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"not",
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"null",
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"of",
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"on",
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"open",
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"or",
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"others",
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"out",
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"package",
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"parameter",
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"port",
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"postponed",
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"procedure",
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"process",
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"property",
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"protected",
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"pure",
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"range",
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"record",
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"register",
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"reject",
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"release",
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"rem",
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"report",
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"restrict",
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"restrict_guarantee",
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"return",
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"rol",
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"ror",
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"select",
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"sequence",
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"severity",
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"shared",
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"signal",
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"sla",
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"sll",
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"sra",
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"srl",
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"strong",
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"subtype",
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"then",
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"to",
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"transport",
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"type",
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"unaffected",
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"units",
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"until",
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"use",
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"variable",
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"view",
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"vmode",
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"vprop",
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"vunit",
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"wait",
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"when",
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"while",
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"with",
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"xnor",
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"xor"
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];
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const BUILT_INS = [
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"boolean",
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"bit",
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"character",
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"integer",
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"time",
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"delay_length",
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"natural",
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"positive",
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"string",
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"bit_vector",
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"file_open_kind",
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"file_open_status",
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"std_logic",
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"std_logic_vector",
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"unsigned",
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"signed",
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"boolean_vector",
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"integer_vector",
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"std_ulogic",
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"std_ulogic_vector",
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"unresolved_unsigned",
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"u_unsigned",
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"unresolved_signed",
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"u_signed",
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"real_vector",
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"time_vector"
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];
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const LITERALS = [
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// severity_level
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"false",
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"true",
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"note",
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"warning",
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"error",
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"failure",
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// textio
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"line",
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"text",
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"side",
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"width"
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];
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return {
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name: 'VHDL',
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case_insensitive: true,
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keywords: {
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keyword: KEYWORDS,
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built_in: BUILT_INS,
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literal: LITERALS
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},
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illegal: /\{/,
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contains: [
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hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.
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hljs.COMMENT('--', '$'),
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hljs.QUOTE_STRING_MODE,
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{
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className: 'number',
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begin: NUMBER_RE,
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relevance: 0
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},
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{
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className: 'string',
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begin: '\'(U|X|0|1|Z|W|L|H|-)\'',
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contains: [ hljs.BACKSLASH_ESCAPE ]
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},
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{
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className: 'symbol',
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begin: '\'[A-Za-z](_?[A-Za-z0-9])*',
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contains: [ hljs.BACKSLASH_ESCAPE ]
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}
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]
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};
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}
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module.exports = vhdl;
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