From e46523412e08f1099aac3715aaa5b7526dbeeba2 Mon Sep 17 00:00:00 2001
From: Max Korbel <max.korbel@intel.com>
Date: Mon, 24 Jun 2024 08:50:46 -0700
Subject: [PATCH] Fix bug in internal array discovery (#494)

---
 lib/src/module.dart                     | 12 ++++++++
 lib/src/synthesizers/systemverilog.dart |  6 ++--
 test/module_test.dart                   | 39 +++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/lib/src/module.dart b/lib/src/module.dart
index 3a4bde96d..5eb818811 100644
--- a/lib/src/module.dart
+++ b/lib/src/module.dart
@@ -417,6 +417,12 @@ abstract class Module {
           !isInput(signal) &&
           !isInOut(signal) &&
           subModule == null) {
+        // handle expanding the search for arrays
+        if (signal.isArrayMember) {
+          await _traceInputForModuleContents(signal.parentStructure!,
+              dontAddSignal: dontAddSignal);
+        }
+
         _addInternalSignal(signal);
       }
 
@@ -514,6 +520,12 @@ abstract class Module {
           !isOutput(signal) &&
           !isInOut(signal) &&
           subModule == null) {
+        // handle expanding the search for arrays
+        if (signal.isArrayMember) {
+          await _traceOutputForModuleContents(signal.parentStructure!,
+              dontAddSignal: dontAddSignal);
+        }
+
         _addInternalSignal(signal);
         for (final dstConnection in signal.dstConnections) {
           await _traceInputForModuleContents(dstConnection);
diff --git a/lib/src/synthesizers/systemverilog.dart b/lib/src/synthesizers/systemverilog.dart
index a42a5ff61..fd50efc72 100644
--- a/lib/src/synthesizers/systemverilog.dart
+++ b/lib/src/synthesizers/systemverilog.dart
@@ -758,8 +758,10 @@ class _SynthModuleDefinition {
     for (var i = 0; i < logicsToTraverse.length; i++) {
       final receiver = logicsToTraverse[i];
 
-      assert(receiver.parentModule != null,
-          'Any signal traced by this should have been detected by build.');
+      assert(
+          receiver.parentModule != null,
+          'Any signal traced by this should have been detected by build,'
+          ' but $receiver was not.');
 
       if (receiver.parentModule != module &&
           !module.subModules.contains(receiver.parentModule)) {
diff --git a/test/module_test.dart b/test/module_test.dart
index 5f0bf497a..d39cc533f 100644
--- a/test/module_test.dart
+++ b/test/module_test.dart
@@ -7,6 +7,7 @@
 // 2023 September 11
 // Author: Max Korbel <max.korbel@intel.com>
 
+import 'package:collection/collection.dart';
 import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
@@ -61,6 +62,33 @@ class MultipleLocation extends Module {
   }
 }
 
+class ArrayConcatMod extends Module {
+  ArrayConcatMod() {
+    final a = addInput('a', Logic());
+    final en = addInput('en', Logic());
+    final b = addOutput('b');
+
+    final aBar = Logic(name: 'a_bar');
+    final orOut = Logic(name: 'or_out');
+
+    final t0 = Logic(name: 't0');
+    final t2 = Logic(name: 't2');
+    final t3 = Logic(name: 't3');
+    final aConcat = LogicArray([4], 1, name: 'a_concat');
+
+    aConcat.elements[3] <= t3;
+    aConcat.elements[2] <= t2;
+    aConcat.elements[1] <= a;
+    aConcat.elements[0] <= t0;
+
+    aBar <= ~aConcat.elements[1];
+
+    orOut <= aBar | en;
+
+    b <= aConcat.elements[1] & orOut;
+  }
+}
+
 void main() {
   test('tryInput, exists', () {
     final mod = ModuleWithMaybePorts(addIn: true);
@@ -101,4 +129,15 @@ void main() {
     final mod = MultipleLocation();
     expect(mod.build, throwsA(isA<PortRulesViolationException>()));
   });
+
+  test('array concat per element builds and finds sigs', () async {
+    final mod = ArrayConcatMod();
+    await mod.build();
+
+    expect(
+        mod.internalSignals.firstWhereOrNull((e) => e.name == 't0'), isNotNull);
+
+    final sv = mod.generateSynth();
+    expect(sv, contains('assign a_concat[0] = t0;'));
+  });
 }