From 4585deee80a24243ba2c2852a00259cd267f0402 Mon Sep 17 00:00:00 2001
From: Max Korbel
Date: Tue, 19 Sep 2023 11:20:41 -0700
Subject: [PATCH] Manually update docs
---
index.json | 2 +-
rohd/Combinational/Combinational.html | 2 +-
...tyReservedNameException-class-sidebar.html | 24 ++
rohd/EmptyReservedNameException-class.html | 251 ++++++++++++++
.../EmptyReservedNameException.html | 128 +++++++
rohd/FiniteStateMachine-class-sidebar.html | 32 ++
rohd/FiniteStateMachine-class.html | 326 ++++++++++++++++++
.../FiniteStateMachine.html | 132 +++++++
.../FiniteStateMachine.multi.html | 191 ++++++++++
rohd/FiniteStateMachine/clk.html | 142 ++++++++
rohd/FiniteStateMachine/currentState.html | 129 +++++++
rohd/FiniteStateMachine/generateDiagram.html | 145 ++++++++
rohd/FiniteStateMachine/getStateIndex.html | 139 ++++++++
rohd/FiniteStateMachine/nextState.html | 129 +++++++
rohd/FiniteStateMachine/reset.html | 127 +++++++
rohd/FiniteStateMachine/resetState.html | 127 +++++++
rohd/FiniteStateMachine/states.html | 134 +++++++
...lConfigurationException-class-sidebar.html | 24 ++
rohd/IllegalConfigurationException-class.html | 252 ++++++++++++++
.../IllegalConfigurationException.html | 128 +++++++
.../InterfaceNameException-class-sidebar.html | 24 ++
rohd/InterfaceNameException-class.html | 251 ++++++++++++++
.../InterfaceNameException.html | 128 +++++++
.../InterfaceTypeException-class-sidebar.html | 24 ++
rohd/InterfaceTypeException-class.html | 252 ++++++++++++++
.../InterfaceTypeException.html | 129 +++++++
...lidConditionalException-class-sidebar.html | 24 ++
rohd/InvalidConditionalException-class.html | 253 ++++++++++++++
.../InvalidConditionalException.html | 128 +++++++
...alidMultiplierException-class-sidebar.html | 24 ++
rohd/InvalidMultiplierException-class.html | 253 ++++++++++++++
.../InvalidMultiplierException.html | 128 +++++++
...nvalidPortNameException-class-sidebar.html | 24 ++
rohd/InvalidPortNameException-class.html | 251 ++++++++++++++
.../InvalidPortNameException.html | 128 +++++++
...idReservedNameException-class-sidebar.html | 24 ++
rohd/InvalidReservedNameException-class.html | 251 ++++++++++++++
.../InvalidReservedNameException.html | 128 +++++++
...alidTruncationException-class-sidebar.html | 24 ++
rohd/InvalidTruncationException-class.html | 253 ++++++++++++++
.../InvalidTruncationException.html | 128 +++++++
...ValueOperationException-class-sidebar.html | 24 ++
.../InvalidValueOperationException-class.html | 254 ++++++++++++++
.../InvalidValueOperationException.html | 130 +++++++
...icConstructionException-class-sidebar.html | 25 ++
rohd/LogicConstructionException-class.html | 262 ++++++++++++++
.../LogicConstructionException.html | 127 +++++++
rohd/LogicConstructionException/reason.html | 127 +++++++
...ueConstructionException-class-sidebar.html | 24 ++
...LogicValueConstructionException-class.html | 251 ++++++++++++++
.../LogicValueConstructionException.html | 127 +++++++
...lreadyAssignedException-class-sidebar.html | 24 ++
...dSignalAlreadyAssignedException-class.html | 253 ++++++++++++++
.../MappedSignalAlreadyAssignedException.html | 127 +++++++
...ModuleNotBuiltException-class-sidebar.html | 24 ++
rohd/ModuleNotBuiltException-class.html | 253 ++++++++++++++
.../ModuleNotBuiltException.html | 128 +++++++
...nSupportedTypeException-class-sidebar.html | 24 ++
rohd/NonSupportedTypeException-class.html | 253 ++++++++++++++
.../NonSupportedTypeException.html | 130 +++++++
...llReservedNameException-class-sidebar.html | 24 ++
rohd/NullReservedNameException-class.html | 251 ++++++++++++++
.../NullReservedNameException.html | 128 +++++++
rohd/Pipeline-class-sidebar.html | 3 +-
rohd/Pipeline-class.html | 13 +-
rohd/Pipeline/Pipeline.html | 4 +-
rohd/Pipeline/Pipeline.multi.html | 182 ++++++++++
rohd/Pipeline/clk.html | 36 +-
...tWidthMismatchException-class-sidebar.html | 25 ++
rohd/PortWidthMismatchException-class.html | 258 ++++++++++++++
...PortWidthMismatchException.equalWidth.html | 131 +++++++
.../PortWidthMismatchException.html | 129 +++++++
rohd/PutException-class-sidebar.html | 24 ++
rohd/PutException-class.html | 252 ++++++++++++++
rohd/PutException/PutException.html | 129 +++++++
rohd/ReadyValidPipeline-class-sidebar.html | 3 +-
rohd/ReadyValidPipeline-class.html | 13 +-
.../ReadyValidPipeline.html | 4 +-
.../ReadyValidPipeline.multi.html | 163 +++++++++
rohd/RohdException-class-sidebar.html | 24 ++
rohd/RohdException-class.html | 278 +++++++++++++++
rohd/RohdException/RohdException.html | 127 +++++++
rohd/RohdException/message.html | 127 +++++++
rohd/RohdException/toString.html | 145 ++++++++
...onnectingLogicException-class-sidebar.html | 24 ++
rohd/SelfConnectingLogicException-class.html | 251 ++++++++++++++
.../SelfConnectingLogicException.html | 128 +++++++
rohd/Sequential/Sequential.multi.html | 4 +
...SignalRedrivenException-class-sidebar.html | 24 ++
rohd/SignalRedrivenException-class.html | 253 ++++++++++++++
.../SignalRedrivenException.html | 130 +++++++
...lWidthMismatchException-class-sidebar.html | 26 ++
rohd/SignalWidthMismatchException-class.html | 264 ++++++++++++++
...gnalWidthMismatchException.forDynamic.html | 135 ++++++++
.../SignalWidthMismatchException.forNull.html | 130 +++++++
.../SignalWidthMismatchException.html | 129 +++++++
rohd/State-class-sidebar.html | 2 +
rohd/State-class.html | 24 +-
rohd/State/State.html | 6 +-
rohd/State/conditionalType.html | 131 +++++++
rohd/State/defaultNextState.html | 127 +++++++
rohd/State/events.html | 3 +
rohd/StateMachine.html | 133 +++++++
...tializedSignalException-class-sidebar.html | 24 ++
rohd/UninitializedSignalException-class.html | 252 ++++++++++++++
.../UninitializedSignalException.html | 127 +++++++
...nsupportedTypeException-class-sidebar.html | 24 ++
rohd/UnsupportedTypeException-class.html | 251 ++++++++++++++
.../UnsupportedTypeException.html | 128 +++++++
...eWidthMismatchException-class-sidebar.html | 24 ++
rohd/ValueWidthMismatchException-class.html | 252 ++++++++++++++
.../ValueWidthMismatchException.html | 129 +++++++
...WriteAfterReadException-class-sidebar.html | 24 ++
rohd/WriteAfterReadException-class.html | 252 ++++++++++++++
.../WriteAfterReadException.html | 126 +++++++
rohd/rohd-library-sidebar.html | 30 +-
rohd/rohd-library.html | 255 +++++++++++++-
117 files changed, 14219 insertions(+), 36 deletions(-)
create mode 100644 rohd/EmptyReservedNameException-class-sidebar.html
create mode 100644 rohd/EmptyReservedNameException-class.html
create mode 100644 rohd/EmptyReservedNameException/EmptyReservedNameException.html
create mode 100644 rohd/FiniteStateMachine-class-sidebar.html
create mode 100644 rohd/FiniteStateMachine-class.html
create mode 100644 rohd/FiniteStateMachine/FiniteStateMachine.html
create mode 100644 rohd/FiniteStateMachine/FiniteStateMachine.multi.html
create mode 100644 rohd/FiniteStateMachine/clk.html
create mode 100644 rohd/FiniteStateMachine/currentState.html
create mode 100644 rohd/FiniteStateMachine/generateDiagram.html
create mode 100644 rohd/FiniteStateMachine/getStateIndex.html
create mode 100644 rohd/FiniteStateMachine/nextState.html
create mode 100644 rohd/FiniteStateMachine/reset.html
create mode 100644 rohd/FiniteStateMachine/resetState.html
create mode 100644 rohd/FiniteStateMachine/states.html
create mode 100644 rohd/IllegalConfigurationException-class-sidebar.html
create mode 100644 rohd/IllegalConfigurationException-class.html
create mode 100644 rohd/IllegalConfigurationException/IllegalConfigurationException.html
create mode 100644 rohd/InterfaceNameException-class-sidebar.html
create mode 100644 rohd/InterfaceNameException-class.html
create mode 100644 rohd/InterfaceNameException/InterfaceNameException.html
create mode 100644 rohd/InterfaceTypeException-class-sidebar.html
create mode 100644 rohd/InterfaceTypeException-class.html
create mode 100644 rohd/InterfaceTypeException/InterfaceTypeException.html
create mode 100644 rohd/InvalidConditionalException-class-sidebar.html
create mode 100644 rohd/InvalidConditionalException-class.html
create mode 100644 rohd/InvalidConditionalException/InvalidConditionalException.html
create mode 100644 rohd/InvalidMultiplierException-class-sidebar.html
create mode 100644 rohd/InvalidMultiplierException-class.html
create mode 100644 rohd/InvalidMultiplierException/InvalidMultiplierException.html
create mode 100644 rohd/InvalidPortNameException-class-sidebar.html
create mode 100644 rohd/InvalidPortNameException-class.html
create mode 100644 rohd/InvalidPortNameException/InvalidPortNameException.html
create mode 100644 rohd/InvalidReservedNameException-class-sidebar.html
create mode 100644 rohd/InvalidReservedNameException-class.html
create mode 100644 rohd/InvalidReservedNameException/InvalidReservedNameException.html
create mode 100644 rohd/InvalidTruncationException-class-sidebar.html
create mode 100644 rohd/InvalidTruncationException-class.html
create mode 100644 rohd/InvalidTruncationException/InvalidTruncationException.html
create mode 100644 rohd/InvalidValueOperationException-class-sidebar.html
create mode 100644 rohd/InvalidValueOperationException-class.html
create mode 100644 rohd/InvalidValueOperationException/InvalidValueOperationException.html
create mode 100644 rohd/LogicConstructionException-class-sidebar.html
create mode 100644 rohd/LogicConstructionException-class.html
create mode 100644 rohd/LogicConstructionException/LogicConstructionException.html
create mode 100644 rohd/LogicConstructionException/reason.html
create mode 100644 rohd/LogicValueConstructionException-class-sidebar.html
create mode 100644 rohd/LogicValueConstructionException-class.html
create mode 100644 rohd/LogicValueConstructionException/LogicValueConstructionException.html
create mode 100644 rohd/MappedSignalAlreadyAssignedException-class-sidebar.html
create mode 100644 rohd/MappedSignalAlreadyAssignedException-class.html
create mode 100644 rohd/MappedSignalAlreadyAssignedException/MappedSignalAlreadyAssignedException.html
create mode 100644 rohd/ModuleNotBuiltException-class-sidebar.html
create mode 100644 rohd/ModuleNotBuiltException-class.html
create mode 100644 rohd/ModuleNotBuiltException/ModuleNotBuiltException.html
create mode 100644 rohd/NonSupportedTypeException-class-sidebar.html
create mode 100644 rohd/NonSupportedTypeException-class.html
create mode 100644 rohd/NonSupportedTypeException/NonSupportedTypeException.html
create mode 100644 rohd/NullReservedNameException-class-sidebar.html
create mode 100644 rohd/NullReservedNameException-class.html
create mode 100644 rohd/NullReservedNameException/NullReservedNameException.html
create mode 100644 rohd/Pipeline/Pipeline.multi.html
create mode 100644 rohd/PortWidthMismatchException-class-sidebar.html
create mode 100644 rohd/PortWidthMismatchException-class.html
create mode 100644 rohd/PortWidthMismatchException/PortWidthMismatchException.equalWidth.html
create mode 100644 rohd/PortWidthMismatchException/PortWidthMismatchException.html
create mode 100644 rohd/PutException-class-sidebar.html
create mode 100644 rohd/PutException-class.html
create mode 100644 rohd/PutException/PutException.html
create mode 100644 rohd/ReadyValidPipeline/ReadyValidPipeline.multi.html
create mode 100644 rohd/RohdException-class-sidebar.html
create mode 100644 rohd/RohdException-class.html
create mode 100644 rohd/RohdException/RohdException.html
create mode 100644 rohd/RohdException/message.html
create mode 100644 rohd/RohdException/toString.html
create mode 100644 rohd/SelfConnectingLogicException-class-sidebar.html
create mode 100644 rohd/SelfConnectingLogicException-class.html
create mode 100644 rohd/SelfConnectingLogicException/SelfConnectingLogicException.html
create mode 100644 rohd/SignalRedrivenException-class-sidebar.html
create mode 100644 rohd/SignalRedrivenException-class.html
create mode 100644 rohd/SignalRedrivenException/SignalRedrivenException.html
create mode 100644 rohd/SignalWidthMismatchException-class-sidebar.html
create mode 100644 rohd/SignalWidthMismatchException-class.html
create mode 100644 rohd/SignalWidthMismatchException/SignalWidthMismatchException.forDynamic.html
create mode 100644 rohd/SignalWidthMismatchException/SignalWidthMismatchException.forNull.html
create mode 100644 rohd/SignalWidthMismatchException/SignalWidthMismatchException.html
create mode 100644 rohd/State/conditionalType.html
create mode 100644 rohd/State/defaultNextState.html
create mode 100644 rohd/StateMachine.html
create mode 100644 rohd/UninitializedSignalException-class-sidebar.html
create mode 100644 rohd/UninitializedSignalException-class.html
create mode 100644 rohd/UninitializedSignalException/UninitializedSignalException.html
create mode 100644 rohd/UnsupportedTypeException-class-sidebar.html
create mode 100644 rohd/UnsupportedTypeException-class.html
create mode 100644 rohd/UnsupportedTypeException/UnsupportedTypeException.html
create mode 100644 rohd/ValueWidthMismatchException-class-sidebar.html
create mode 100644 rohd/ValueWidthMismatchException-class.html
create mode 100644 rohd/ValueWidthMismatchException/ValueWidthMismatchException.html
create mode 100644 rohd/WriteAfterReadException-class-sidebar.html
create mode 100644 rohd/WriteAfterReadException-class.html
create mode 100644 rohd/WriteAfterReadException/WriteAfterReadException.html
diff --git a/index.json b/index.json
index cce2f4c59..57c8f31de 100644
--- a/index.json
+++ b/index.json
@@ -1 +1 @@
-[{"name":"rohd","qualifiedName":"rohd","href":"rohd/rohd-library.html","kind":8,"overriddenDepth":0,"packageRank":0,"desc":""},{"name":"ARShift","qualifiedName":"rohd.ARShift","href":"rohd/ARShift-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"An arithmetic right-shift module.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"ARShift","qualifiedName":"rohd.ARShift.ARShift","href":"rohd/ARShift/ARShift.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Calculates the value of in_ shifted right (arithmetically) by\nshiftAmount.","enclosedBy":{"name":"ARShift","kind":3,"href":"rohd/ARShift-class.html"}},{"name":"inlineVerilog","qualifiedName":"rohd.ARShift.inlineVerilog","href":"rohd/ARShift/inlineVerilog.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Generates custom SystemVerilog to be injected in place of the output\nport's corresponding signal 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in1.","enclosedBy":{"name":"Add","kind":3,"href":"rohd/Add-class.html"}},{"name":"inlineVerilog","qualifiedName":"rohd.Add.inlineVerilog","href":"rohd/Add/inlineVerilog.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Generates custom SystemVerilog to be injected in place of the output\nport's corresponding signal name.","enclosedBy":{"name":"Add","kind":3,"href":"rohd/Add-class.html"}},{"name":"out","qualifiedName":"rohd.Add.out","href":"rohd/Add/out.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate.","enclosedBy":{"name":"Add","kind":3,"href":"rohd/Add-class.html"}},{"name":"y","qualifiedName":"rohd.Add.y","href":"rohd/Add/y.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate.","enclosedBy":{"name":"Add","kind":3,"href":"rohd/Add-class.html"}},{"name":"And2Gate","qualifiedName":"rohd.And2Gate","href":"rohd/And2Gate-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"A two-input AND gate.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"And2Gate","qualifiedName":"rohd.And2Gate.And2Gate","href":"rohd/And2Gate/And2Gate.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Calculates the AND of in0 and in1.","enclosedBy":{"name":"And2Gate","kind":3,"href":"rohd/And2Gate-class.html"}},{"name":"inlineVerilog","qualifiedName":"rohd.And2Gate.inlineVerilog","href":"rohd/And2Gate/inlineVerilog.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Generates custom SystemVerilog to be injected in place of the output\nport's corresponding signal name.","enclosedBy":{"name":"And2Gate","kind":3,"href":"rohd/And2Gate-class.html"}},{"name":"out","qualifiedName":"rohd.And2Gate.out","href":"rohd/And2Gate/out.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this 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declaration.","enclosedBy":{"name":"SimulatorPhase","kind":5,"href":"rohd/SimulatorPhase.html"}},{"name":"State","qualifiedName":"rohd.State","href":"rohd/State-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"Simple class to initialize each state of the FSM.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"State","qualifiedName":"rohd.State.State","href":"rohd/State/State.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Represents a state named identifier with a definition of events\nand actions associated with that state.","enclosedBy":{"name":"State","kind":3,"href":"rohd/State-class.html"}},{"name":"actions","qualifiedName":"rohd.State.actions","href":"rohd/State/actions.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"Actions to perform while the FSM is in this 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the difference between in0 and in1.","enclosedBy":{"name":"Subtract","kind":3,"href":"rohd/Subtract-class.html"}},{"name":"inlineVerilog","qualifiedName":"rohd.Subtract.inlineVerilog","href":"rohd/Subtract/inlineVerilog.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Generates custom SystemVerilog to be injected in place of the output\nport's corresponding signal name.","enclosedBy":{"name":"Subtract","kind":3,"href":"rohd/Subtract-class.html"}},{"name":"out","qualifiedName":"rohd.Subtract.out","href":"rohd/Subtract/out.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate.","enclosedBy":{"name":"Subtract","kind":3,"href":"rohd/Subtract-class.html"}},{"name":"y","qualifiedName":"rohd.Subtract.y","href":"rohd/Subtract/y.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this 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outputs.","enclosedBy":{"name":"SynthBuilder","kind":3,"href":"rohd/SynthBuilder-class.html"}},{"name":"getFileContents","qualifiedName":"rohd.SynthBuilder.getFileContents","href":"rohd/SynthBuilder/getFileContents.html","kind":9,"overriddenDepth":0,"packageRank":0,"desc":"Collects a List of Strings representing file contents generated by\nthe synthesizer.","enclosedBy":{"name":"SynthBuilder","kind":3,"href":"rohd/SynthBuilder-class.html"}},{"name":"synthesisResults","qualifiedName":"rohd.SynthBuilder.synthesisResults","href":"rohd/SynthBuilder/synthesisResults.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"All the SynthesisResults generated by this SynthBuilder.","enclosedBy":{"name":"SynthBuilder","kind":3,"href":"rohd/SynthBuilder-class.html"}},{"name":"synthesizer","qualifiedName":"rohd.SynthBuilder.synthesizer","href":"rohd/SynthBuilder/synthesizer.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The Synthesizer to use for generating an output.","enclosedBy":{"name":"SynthBuilder","kind":3,"href":"rohd/SynthBuilder-class.html"}},{"name":"top","qualifiedName":"rohd.SynthBuilder.top","href":"rohd/SynthBuilder/top.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The top-level Module to be synthesized.","enclosedBy":{"name":"SynthBuilder","kind":3,"href":"rohd/SynthBuilder-class.html"}},{"name":"SynthesisResult","qualifiedName":"rohd.SynthesisResult","href":"rohd/SynthesisResult-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"An object representing the output of a Synthesizer","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"operator ==","qualifiedName":"rohd.SynthesisResult.==","href":"rohd/SynthesisResult/operator_equals.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"The equality 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definition type for this module instance.","enclosedBy":{"name":"SynthesisResult","kind":3,"href":"rohd/SynthesisResult-class.html"}},{"name":"matchHashCode","qualifiedName":"rohd.SynthesisResult.matchHashCode","href":"rohd/SynthesisResult/matchHashCode.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"Like the hashCode for matchesImplementation as an equality check.","enclosedBy":{"name":"SynthesisResult","kind":3,"href":"rohd/SynthesisResult-class.html"}},{"name":"matchesImplementation","qualifiedName":"rohd.SynthesisResult.matchesImplementation","href":"rohd/SynthesisResult/matchesImplementation.html","kind":9,"overriddenDepth":0,"packageRank":0,"desc":"Whether two implementations are identical or not","enclosedBy":{"name":"SynthesisResult","kind":3,"href":"rohd/SynthesisResult-class.html"}},{"name":"module","qualifiedName":"rohd.SynthesisResult.module","href":"rohd/SynthesisResult/module.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The top level Module 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output format","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"Synthesizer","qualifiedName":"rohd.Synthesizer.Synthesizer","href":"rohd/Synthesizer/Synthesizer.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"","enclosedBy":{"name":"Synthesizer","kind":3,"href":"rohd/Synthesizer-class.html"}},{"name":"generatesDefinition","qualifiedName":"rohd.Synthesizer.generatesDefinition","href":"rohd/Synthesizer/generatesDefinition.html","kind":9,"overriddenDepth":0,"packageRank":0,"desc":"Determines whether module needs a separate definition or can just be\ndescribed in-line.","enclosedBy":{"name":"Synthesizer","kind":3,"href":"rohd/Synthesizer-class.html"}},{"name":"synthesize","qualifiedName":"rohd.Synthesizer.synthesize","href":"rohd/Synthesizer/synthesize.html","kind":9,"overriddenDepth":0,"packageRank":0,"desc":"Synthesizes module into a SynthesisResult, given the mapping in\nmoduleToInstanceTypeMap.","enclosedBy":{"name":"Synthesizer","kind":3,"href":"rohd/Synthesizer-class.html"}},{"name":"SystemVerilogSynthesizer","qualifiedName":"rohd.SystemVerilogSynthesizer","href":"rohd/SystemVerilogSynthesizer-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"A Synthesizer which generates equivalent SystemVerilog as the\ngiven Module.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"SystemVerilogSynthesizer","qualifiedName":"rohd.SystemVerilogSynthesizer.SystemVerilogSynthesizer","href":"rohd/SystemVerilogSynthesizer/SystemVerilogSynthesizer.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"","enclosedBy":{"name":"SystemVerilogSynthesizer","kind":3,"href":"rohd/SystemVerilogSynthesizer-class.html"}},{"name":"generatesDefinition","qualifiedName":"rohd.SystemVerilogSynthesizer.generatesDefinition","href":"rohd/SystemVerilogSynthesizer/generatesDefinition.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Determines whether module needs a separate definition or can just be\ndescribed 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in\nmoduleToInstanceTypeMap.","enclosedBy":{"name":"SystemVerilogSynthesizer","kind":3,"href":"rohd/SystemVerilogSynthesizer-class.html"}},{"name":"UninitializedSignalException","qualifiedName":"rohd.UninitializedSignalException","href":"rohd/UninitializedSignalException-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"An exception that is thrown when Combinational.ssa detects that an SSA\nsignal is being used before it was initialized.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"UninitializedSignalException","qualifiedName":"rohd.UninitializedSignalException.UninitializedSignalException","href":"rohd/UninitializedSignalException/UninitializedSignalException.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Creates a UninitializedSignalException for signalName.","enclosedBy":{"name":"UninitializedSignalException","kind":3,"href":"rohd/UninitializedSignalException-class.html"}},{"name":"UnsupportedTypeException","qualifiedName":"rohd.UnsupportedTypeException","href":"rohd/UnsupportedTypeException-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"An exception that is thrown when an unsupported type is used.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"UnsupportedTypeException","qualifiedName":"rohd.UnsupportedTypeException.UnsupportedTypeException","href":"rohd/UnsupportedTypeException/UnsupportedTypeException.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Creates an exception when an unsupported type is used.","enclosedBy":{"name":"UnsupportedTypeException","kind":3,"href":"rohd/UnsupportedTypeException-class.html"}},{"name":"ValueWidthMismatchException","qualifiedName":"rohd.ValueWidthMismatchException","href":"rohd/ValueWidthMismatchException-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"An exception that is thrown when LogicValues of different width are found.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"ValueWidthMismatchException","qualifiedName":"rohd.ValueWidthMismatchException.ValueWidthMismatchException","href":"rohd/ValueWidthMismatchException/ValueWidthMismatchException.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Creates an exception when two LogicValue considered for the operation\nare of different width.","enclosedBy":{"name":"ValueWidthMismatchException","kind":3,"href":"rohd/ValueWidthMismatchException-class.html"}},{"name":"WaveDumper","qualifiedName":"rohd.WaveDumper","href":"rohd/WaveDumper-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"A waveform dumper for simulations.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"WaveDumper","qualifiedName":"rohd.WaveDumper.WaveDumper","href":"rohd/WaveDumper/WaveDumper.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Attaches a WaveDumper to record all signal changes in a simulation of\nmodule in a VCD file at outputPath.","enclosedBy":{"name":"WaveDumper","kind":3,"href":"rohd/WaveDumper-class.html"}},{"name":"module","qualifiedName":"rohd.WaveDumper.module","href":"rohd/WaveDumper/module.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The Module being dumped.","enclosedBy":{"name":"WaveDumper","kind":3,"href":"rohd/WaveDumper-class.html"}},{"name":"outputPath","qualifiedName":"rohd.WaveDumper.outputPath","href":"rohd/WaveDumper/outputPath.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output filepath of the generated waveforms.","enclosedBy":{"name":"WaveDumper","kind":3,"href":"rohd/WaveDumper-class.html"}},{"name":"WriteAfterReadException","qualifiedName":"rohd.WriteAfterReadException","href":"rohd/WriteAfterReadException-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"An exception that is thrown when a \"write after read\" violation occurs.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"WriteAfterReadException","qualifiedName":"rohd.WriteAfterReadException.WriteAfterReadException","href":"rohd/WriteAfterReadException/WriteAfterReadException.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Creates a WriteAfterReadException.","enclosedBy":{"name":"WriteAfterReadException","kind":3,"href":"rohd/WriteAfterReadException-class.html"}},{"name":"Xor2Gate","qualifiedName":"rohd.Xor2Gate","href":"rohd/Xor2Gate-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"A two-input XOR gate.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"Xor2Gate","qualifiedName":"rohd.Xor2Gate.Xor2Gate","href":"rohd/Xor2Gate/Xor2Gate.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Calculates the XOR of in0 and in1.","enclosedBy":{"name":"Xor2Gate","kind":3,"href":"rohd/Xor2Gate-class.html"}},{"name":"inlineVerilog","qualifiedName":"rohd.Xor2Gate.inlineVerilog","href":"rohd/Xor2Gate/inlineVerilog.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Generates custom SystemVerilog to be injected in place of the output\nport's corresponding signal name.","enclosedBy":{"name":"Xor2Gate","kind":3,"href":"rohd/Xor2Gate-class.html"}},{"name":"out","qualifiedName":"rohd.Xor2Gate.out","href":"rohd/Xor2Gate/out.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate.","enclosedBy":{"name":"Xor2Gate","kind":3,"href":"rohd/Xor2Gate-class.html"}},{"name":"y","qualifiedName":"rohd.Xor2Gate.y","href":"rohd/Xor2Gate/y.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate.","enclosedBy":{"name":"Xor2Gate","kind":3,"href":"rohd/Xor2Gate-class.html"}},{"name":"XorUnary","qualifiedName":"rohd.XorUnary","href":"rohd/XorUnary-class.html","kind":3,"overriddenDepth":0,"packageRank":0,"desc":"A unary XOR gate.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"XorUnary","qualifiedName":"rohd.XorUnary.XorUnary","href":"rohd/XorUnary/XorUnary.html","kind":2,"overriddenDepth":0,"packageRank":0,"desc":"Calculates the parity of the bits of in_.","enclosedBy":{"name":"XorUnary","kind":3,"href":"rohd/XorUnary-class.html"}},{"name":"inlineVerilog","qualifiedName":"rohd.XorUnary.inlineVerilog","href":"rohd/XorUnary/inlineVerilog.html","kind":9,"overriddenDepth":1,"packageRank":0,"desc":"Generates custom SystemVerilog to be injected in place of the output\nport's corresponding signal name.","enclosedBy":{"name":"XorUnary","kind":3,"href":"rohd/XorUnary-class.html"}},{"name":"out","qualifiedName":"rohd.XorUnary.out","href":"rohd/XorUnary/out.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate (width is always 1).","enclosedBy":{"name":"XorUnary","kind":3,"href":"rohd/XorUnary-class.html"}},{"name":"y","qualifiedName":"rohd.XorUnary.y","href":"rohd/XorUnary/y.html","kind":15,"overriddenDepth":0,"packageRank":0,"desc":"The output of this gate (width is always 1).","enclosedBy":{"name":"XorUnary","kind":3,"href":"rohd/XorUnary-class.html"}},{"name":"bin","qualifiedName":"rohd.bin","href":"rohd/bin.html","kind":7,"overriddenDepth":0,"packageRank":0,"desc":"Converts a binary String representation to a binary int.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"cases","qualifiedName":"rohd.cases","href":"rohd/cases.html","kind":7,"overriddenDepth":0,"packageRank":0,"desc":"Shorthand for a Case inside a Conditional block.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"flop","qualifiedName":"rohd.flop","href":"rohd/flop.html","kind":7,"overriddenDepth":0,"packageRank":0,"desc":"Constructs a positive edge triggered flip flop on clk.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"mux","qualifiedName":"rohd.mux","href":"rohd/mux.html","kind":7,"overriddenDepth":0,"packageRank":0,"desc":"Performs a multiplexer/ternary operation.","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"rswizzle","qualifiedName":"rohd.rswizzle","href":"rohd/rswizzle.html","kind":7,"overriddenDepth":0,"packageRank":0,"desc":"Performs a concatenation operation on the list of signals, where index 0 of\nsignals is the least significant bit(s).","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}},{"name":"swizzle","qualifiedName":"rohd.swizzle","href":"rohd/swizzle.html","kind":7,"overriddenDepth":0,"packageRank":0,"desc":"Performs a concatenation operation on the list of signals, where index 0 of\nsignals is the most significant bit(s).","enclosedBy":{"name":"rohd","kind":8,"href":"rohd/rohd-library.html"}}]
diff --git a/rohd/Combinational/Combinational.html b/rohd/Combinational/Combinational.html
index f8696925f..c0c927283 100644
--- a/rohd/Combinational/Combinational.html
+++ b/rohd/Combinational/Combinational.html
@@ -71,7 +71,7 @@
If any "write after read" occurs, then a WriteAfterReadException will
+
If any "write after read" occurs, then a WriteAfterReadException will
be thrown since it could lead to a mismatch between simulation and
synthesis. See Combinational.ssa for more details.
+ Creates an finite state machine for the specified list of _states, with
+an initial state of resetState (when synchronous reset is high) and
+transitions on positive clk edges.
+
+ Creates an finite state machine for the specified list of _states, with
+an initial state of resetState (when synchronous reset is high) and
+transitions on positive edges of any of _clks.
+
+ Generate a FSM state diagram _MermaidStateDiagram.
+Check on https://mermaid.js.org/intro/ to view the diagram generated.
+If you are using vscode, you can download the mermaid extension.
+
+
+
Creates an finite state machine for the specified list of _states, with
+an initial state of resetState (when synchronous reset is high) and
+transitions on positive clk edges.
Creates an finite state machine for the specified list of _states, with
+an initial state of resetState (when synchronous reset is high) and
+transitions on positive edges of any of _clks.
Generate a FSM state diagram _MermaidStateDiagram.
+Check on https://mermaid.js.org/intro/ to view the diagram generated.
+If you are using vscode, you can download the mermaid extension.
+
Output to mermaid diagram at outputPath.
+
+
+
+
+
+
Implementation
+
void generateDiagram({String outputPath = 'diagram_fsm.md'}) {
+ final figure = _MermaidStateDiagram(outputPath: outputPath)
+ ..addStartState(resetState.toString());
+
+ for (final state in _states) {
+ for (final entry in state.events.entries) {
+ figure.addTransitions(state.identifier.toString(),
+ entry.value.toString(), entry.key.name);
+ }
+ }
+ figure.writeToFile();
+}
An exception that is thrown when Combinational.ssa is attempting to
+deduce mappings for signals but fails since a signal would be connected
+multiple times.
Pipeline constructor
objects. Each stage can be thought of as being the contents of a
Combinational block. Use the PipelineStageInfo object to grab
signals for a given pipe stage. Flops are positive edge triggered
-based on clk.
+based on clk.
Signals to be pipelined can optionally be specified in the signals
list. Any signal referenced in a stage via the PipelineStageInfo
will automatically be included in the entire pipeline.
-
If a reset signal is provided, then it will be consumed as an
+
If a reset signal is provided, then it will be consumed as an
active-high reset for every signal through the pipeline. The default
reset value is 0 for all signals, but that can be overridden by
setting resetValues to the desired value. The values specified
diff --git a/rohd/Pipeline/Pipeline.multi.html b/rohd/Pipeline/Pipeline.multi.html
new file mode 100644
index 000000000..ca1eac8c3
--- /dev/null
+++ b/rohd/Pipeline/Pipeline.multi.html
@@ -0,0 +1,182 @@
+
+
+
Constructs a Pipeline with multiple triggers on any of _clks.
+
+
+
+
+
+
Implementation
+
Pipeline.multi(this._clks,
+ {List<List<Conditional> Function(PipelineStageInfo p)> stages = const [],
+ List<Logic?>? stalls,
+ List<Logic> signals = const [],
+ Map<Logic, Const> resetValues = const {},
+ this.reset}) {
+ _stages = stages.map(_PipeStage.new).toList();
+ _stages.add(_PipeStage((p) => [])); // output stage
+
+ if (_numStages == 0) {
+ return;
+ }
+
+ _resetValues = Map.from(resetValues);
+
+ _setStalls(stalls);
+
+ signals.forEach(_add);
+
+ for (var stageIndex = 0; stageIndex < _numStages; stageIndex++) {
+ Combinational.ssa((ssa) {
+ // keep track of the previously registered logics:
+ final prevRegisteredLogics = _registeredLogics.toSet();
+
+ // build the conditionals first so that we populate _registeredLogics
+ final stageConditionals = _stages[stageIndex]
+ .operation(PipelineStageInfo._(this, stageIndex, ssa));
+
+ // if any new logics were registered, add some extra assignments
+ // to make up the gap since it didn't get included in prior generations
+ for (final l in _registeredLogics) {
+ if (!prevRegisteredLogics.contains(l)) {
+ for (var i = 0; i < stageIndex; i++) {
+ _o(l, i) <= _i(l, i);
+ }
+ }
+ }
+
+ return [
+ for (final l in _registeredLogics)
+ ssa(get(l, stageIndex)) < _i(l, stageIndex),
+ ...stageConditionals,
+ ];
+ }, name: 'comb_stage$stageIndex');
+
+ // do output connections as assignments so they can be collapsed
+ for (final l in _registeredLogics) {
+ _o(l, stageIndex) <= get(l, stageIndex);
+ }
+ }
+}