chapter7.tex

% Free range VHDL
% Authors: Bryan Mealy, Fabrizio Tappero
% Date: January, 2023
% URL: https://github.com/fabriziotappero/Free-Range-VHDL-book
% (C) 2018-2023 B. Mealy, F. Tappero
%
% !TEX root = master.tex
%
\chapter{Using VHDL for Sequential Circuits}
All the circuits we have examined up until now have been combinatorial logic circuits. In other words, none of the circuits we have examined so far are actually able to store information. This section shows some of the various methods used to describe sequential circuits. We limit our discussion to VHDL behavioral models for several different flavors of D~flip-flops. It is possible and in some cases desirable to use data-flow models to describe storage elements in VHDL, but it is much easier to use behavior models.

The few approaches for designing flip-flops shown in the next section cover just about all the possible functionality you could imagine when you make use of a D~flip-flop. Once you understand these basics, you will be on your way to understand how to use VHDL to design Finite State Machines (FSMs). This book will examine FSMs in a later chapter.

\section{Simple Storage Elements Using VHDL}
The general approach for learning how to implement storage elements in digital design is to study the properties of a basic cross-coupled cell. The cross coupled cell forms what is referred to as \textbf{a latch}. The concept of a clocking signal is added to the device in order to enhance its controllability. Finally, some type of pulse narrowing circuitry is added to the clocking signal to get to the flip-flop. The flip-flop is nothing more than an edge-sensitive bit-storage device.

The study of a VHDL implementation of storage elements starts with the edge-triggered D~flip-flop. The VHDL examples presented are the basic edge-triggered D~flip-flop with an assortment of added functionality.
\begin{leftbar}
\begin{minipage}{0.5\linewidth}
\noindent
\textbf{EXAMPLE 14.}
Write the VHDL code that describes a D~flip-flop shown on the right. Use a behavioral model in your description.
\end{minipage}
\begin{minipage}{0.47\linewidth}
\begin{flushright}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.9,framed]
%\draw[help lines] (0,0) grid (50,50);
% BOX
\draw (20,5) rectangle (35,20) node[midway]{$d\_ff$};
% INPUTS
\small
\node (b) at (0,-2) {}; % this is to extend the pink area
\node (b) at (20,22.5) {}; % this is to extend the pink area
\node (a) at (20,2.5) {}; % this is the reference point
\draw [latex-] ($(a)+(0,15)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw [-latex] ($(a)+(15,10)$) -- ++(10,0) node[above]{Q};
\end{tikzpicture}
\end{flushright}
\end{minipage}
\end{leftbar}
\noindent
\textbf{SOLUTION.} The solution to Example~14 is shown in Listing~\ref{exe_14}. Listed below are a few interesting things to note about the solution.
\begin{my_list}
\item The given architecture body describes the \texttt{my\_d\_ff} version of the \texttt{d\_ff} entity.
\item Because this example requires the use of a behavioral model, the architecture body includes primarily a process statement. The statements within the process are executed sequentially. The process is executed each time a change is detected in any of the signals in the process' sensitivity list.  In this case, the statements within the process are executed each time there is a change in logic level of the \texttt{CLK} signal.
\item The \texttt{rising\_edge()} construct is used in the \texttt{if} statement to indicate that changes in the circuit output happen only on the rising edge of the \texttt{CLK} input. The \texttt{rising\_edge()} construct is actually an example of a VHDL function which has been defined in one of the included libraries. The way the VHDL code has been written makes the whole circuit synchronous; in fact, changes in the circuit's output are synchronized with the rising edge of the clock signal. In this case, the action is a transfer of the logic level on the \texttt{D} input to the \texttt{Q} output.
\item The functionality of \texttt{rising\_edge(CLK)} can be achieved using the quite popular VHDL ``\texttt{event}'' attribute via the construct:\\
\texttt{CLK'event and CLK='1'}.\\
Please keep this in mind.
\item The process has the label \texttt{dff}. This is not required by the VHDL language but the addition of process labels promotes a self-describing nature of the code and increases its readability and understandability.
\end{my_list}

\noindent
\begin{minipage}{0.99\linewidth}
\begin{lstlisting}[label=exe_14, caption=Solution to Example~14.]
-----------------------------------
-- Model of a simple D Flip-Flop --
-----------------------------------
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity d_ff is
	port ( D, CLK : in  std_logic;
		   Q :      out std_logic);
end d_ff;
-- architecture
architecture my_d_ff of d_ff is
begin
	dff:  process(CLK)
	begin
		if (rising_edge(CLK))      then
--or    if (CLK'event and CLK='1') then
			Q <= D;
		end if;
	end process dff;
end my_d_ff;
\end{lstlisting}
\end{minipage}

The D~flip-flop is best known and loved for its ability to store (save, remember) a single bit. The way that the VHDL code in Listing~\ref{exe_14} is able to store a bit is not however obvious. The bit-storage capability in VHDL is implied by the way the VHDL code is interpreted. The implied storage capability comes about as a result of not providing a condition that indicates what should happen if the listed \texttt{if} condition is not met. In other words, if the \texttt{if} condition is not met, the device does not change the value of \texttt{Q} and therefore it must remember the current value. The memory feature of the current value, or state, constitutes the famous bit storage quality of a flip-flop. If you have not specified what the output should be for every possible set of input conditions, the option taken by VHDL is to not change the current output. By definition, if the input changes to an unspecified state, the output remains unchanged. In this case, the output associated with the previous set of input can be thought of as being remembered. It is this mechanism, as strange and interesting as it is, that is used to induce memory in the VHDL code.

In terms of the D flip-flop shown in Example~14, the only time the output is specified is for that delta time associated with the rising edge of the clock. The typical method used to provide a catch-all condition in case the if condition is not met is with an \texttt{else} clause. Generally speaking, a quick way to tell if you have induced a memory element is to look for the presence of an \texttt{else} clause associated with the \texttt{if} statement.

The previous two paragraphs are vastly important for understanding VHDL; the concept of inducing memory in VHDL is very important to digital circuit design. The design of sequential circuits is dependent on this concept. This somewhat cryptic method used by VHDL to induce memory elements is a byproduct of behavioral modeling based solely on the interpretation of the VHDL source code. Even if you are only using VHDL to design combinatorial circuits, you will most likely be faced with the comprehension of these concepts. One of the classic warnings generated by the VHDL synthesizer is the notification that your VHDL code has generated a \texttt{latch}. Despite the fact that this is only a warning, if you did not intend to generate a latch, you should strive to modify your VHDL code in such a way as to remove this warning. Assuming you did not intend to generate a latch, the cause of your problem is that you have not explicitly provided an output state for all the possible input conditions. Because of this, your circuit will need to remember the previous output state so that it can provide an output in the case where you have not explicitly listed the current input condition.

\begin{leftbar}
\begin{minipage}{0.5\linewidth}
\noindent
\textbf{EXAMPLE 15.}
Write the VHDL code that describes a D~flip-flop shown on the right. Use a behavioral model in your description. Consider the \texttt{S} input to be an active-low, synchronous input that sets the \texttt{D}~flip-flop outputs when asserted.
\end{minipage}
\begin{minipage}{0.47\linewidth}
\begin{flushright}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.9,framed]
%\draw[help lines] (0,0) grid (50,50);
% BOX
\draw (20,5) rectangle (35,20) node[midway]{$d\_ff\_ns$};
% INPUTS
\small
\node (b) at (0,-2) {}; % this is to extend the pink area
\node (b) at (20,22.5) {}; % this is to extend the pink area
\node (a) at (20,2.5) {}; % this is the reference point
\draw [latex-] ($(a)+(0,15)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw [latex-] ($(a)+(8.5,1.5)$) |- ++(-19,-5) node[above]{S};
\draw ($(a)+(8.5,1.8)$) circle (2pt);
% OUTPUTS
\draw [-latex] ($(a)+(15,10)$) -- ++(10,0) node[above]{Q};
\end{tikzpicture}
\end{flushright}
\end{minipage}
\end{leftbar}
\noindent
\textbf{SOLUTION.} The solution to Example~15 is shown in Listing~\ref{exe_15}. There are a few things of interest regarding this solution.
\begin{my_list}
\item The \texttt{S} input to the flip-flop is made synchronous by only allowing it to affect the operation of the flip-flop on the rising edge of the system clock.
\item On the rising edge of the clock, the \texttt{S} input takes precedence over the \texttt{D} input because the state of the \texttt{S} input is checked prior to examining the state of the \texttt{D} input. In an \texttt{if-else} statement, once one condition evaluates as true, none of the other conditions is checked. In other words, the \texttt{D} input is transferred to the output only on the rising edge of the clock and only if the \texttt{S} input is not asserted.
\end{my_list}

\noindent
\begin{minipage}{0.99\linewidth}
\begin{lstlisting}[label=exe_15, caption=Solution to Example~15.]
------------------------------------------------------------------
-- RET D Flip-flop model with active-low synchronous set input. --
------------------------------------------------------------------
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity d_ff_ns is
    port (  D,S :  in  std_logic;
            CLK :  in  std_logic;
              Q :  out std_logic);
end d_ff_ns;
-- architecture
architecture my_d_ff_ns of d_ff_ns is
begin
   dff:  process (CLK)
   begin
      if (rising_edge(CLK)) then
         if (S = '0') then
            Q <= '1';
         else
            Q <= D;
         end if;
      end if;
   end process dff;
end my_d_ff_ns;
\end{lstlisting}
\end{minipage}

\begin{leftbar}
\begin{minipage}{0.5\linewidth}
\noindent
\textbf{EXAMPLE 16.}
Write the VHDL code that describes a D~flip-flop shown on the right. Use a behavioral model in your description. Consider the \texttt{R} input to be an active-high, asynchronous input that resets the \texttt{D}~flip-flop outputs when asserted.
\end{minipage}
\begin{minipage}{0.47\linewidth}
\begin{flushright}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.9,framed]
%\draw[help lines] (0,0) grid (50,50);
% BOX
\draw (20,5) rectangle (35,20) node[midway]{$d\_ff\_r$};
% INPUTS
\small
\node (b) at (0,-2) {}; % this is to extend the pink area
\node (b) at (20,22.5) {}; % this is to extend the pink area
\node (a) at (20,2.5) {}; % this is the reference point
\draw [latex-] ($(a)+(0,15)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{$\overline{CLK}$};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw [latex-] ($(a)+(8.5,2.5)$) |- ++(-19,-5) node[above]{R};
% OUTPUTS
\draw [-latex] ($(a)+(15,10)$) -- ++(10,0) node[above]{Q};
\end{tikzpicture}
\end{flushright}
\end{minipage}
\end{leftbar}
\noindent
\textbf{SOLUTION.} The solution to Example~16 is shown in Listing~\ref{exe_16}. You can probably glean the most information about asynchronous input and synchronous inputs by comparing the solutions to Example~15 and Example~16. A couple of interesting points are listed below.
\begin{my_list}
\item The reset input is independent of the clock and takes priority over the clock. This prioritization is done by making the reset condition the first condition in the \texttt{if} statement. Evaluation of the other conditions continues if the \texttt{R} input does not evaluate to a '1'.
\item The \texttt{falling\_edge()} function is used to make the D~flip-flop falling-edge-triggered. Once again, this function is defined in one of the included libraries.
\end{my_list}

\noindent
\begin{minipage}{0.99\linewidth}
\begin{lstlisting}[label=exe_16, caption=Solution to Example~16.]
----------------------------------------------------------------------
-- FET D Flip-flop model with active-high asynchronous reset input. --
----------------------------------------------------------------------
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity d_ff_r is
    port (   D,R :  in  std_logic;
             CLK :  in  std_logic;
               Q :  out std_logic);
end d_ff_r;
-- architecture
architecture my_d_ff_r of d_ff_r is
begin
   dff:  process (R,CLK)
   begin
      if (R = '1') then
         Q <= '0';
      elsif (falling_edge(CLK)) then
         Q <= D;
      end if;
   end process dff;
end my_d_ff_r;
\end{lstlisting}
\end{minipage}

The solutions of Example~15 and Example~16 represent what can be considered the standard VHDL approaches to handling synchronous and asynchronous inputs, respectively. The general forms of these solutions are actually considered templates for synchronous and asynchronous inputs by several VHDL references. As you will see later, these solutions form the foundation to finite state machine design using VHDL.

\begin{leftbar}
\begin{minipage}{0.5\linewidth}
\noindent
\textbf{EXAMPLE 17.}
Write the VHDL code that describes a T~flip-flop shown on the right. Use a behavioral model in your description. Consider the \texttt{S} input to be an active-low, asynchronous input that sets the T~flip-flop outputs when asserted.
\end{minipage}
\begin{minipage}{0.47\linewidth}
\begin{flushright}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.9,framed]
% BOX
\draw (20,5) rectangle (35,20) node[midway]{$t\_ff\_s$};
% INPUTS
\small
\node (b) at (0,-2) {}; % this is to extend the pink area
\node (b) at (20,22.5) {}; % this is to extend the pink area
\node (a) at (20,2.5) {}; % this is the reference point
\draw [latex-] ($(a)+(0,15)$) -- ++(-10,0) node[above]{T};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw [latex-] ($(a)+(8.5,1.0)$) |- ++(-19,-5) node[above]{S};
\draw ($(a)+(8.5,1.8)$) circle (2pt);
% OUTPUTS
\draw [-latex] ($(a)+(15,10)$) -- ++(10,0) node[above]{Q};
\end{tikzpicture}
\end{flushright}
\end{minipage}
\end{leftbar}
\noindent
\textbf{SOLUTION.} The solution to Example~17 is shown in Listing~\ref{exe_17}. This example has some very important techniques associated with it that are well worth mentioning below.
\begin{my_list}
\item A unique quality of the D~flip-flop is demonstrated in this implementation of a T~flip-flop. The output of a D~flip-flop is only dependent upon the \texttt{D} input and is not a function of the present output of the flip-flop. The output of a T~flip-flop is dependent upon both the \texttt{T} input and the current output of the flip-flop. This adds a certain amount of extra complexity to the T~flip-flop model as compared to the D~flip-flop as is shown in Listing~\ref{exe_17}. The T~flip-flop model in Listing~\ref{exe_17} uses a temporary signal in order to use the current state of the flip-flop as an input. In other words, since \texttt{Q} appears as a port to the entity it must be assigned a mode specifier and in this case, it has been assigned a mode specifier of ``out''. \textbf{Signals that are declared as outputs can therefore not appear on the right-hand side of a signal assignment operator}. The standard approach to bypassing this apparent limitation in VHDL is to \textbf{use intermediate signals} which, as opposed to port signals, do not have mode specifications and can thus be used as either inputs or outputs (can appear on both sides of the signal assignment operator) in the body of the architecture. The approach is to manipulate the intermediate signal in the body of the architecture but to also use a concurrent signal assignment statement to assign the intermediate signal to the appropriate output. Note that in the key statement in the solution shown in \ref{exe_17} that the intermediate signal appears on both sides of the signal assignment operator. This is a widely used approach in VHDL: please take time to understand and absorb it. And lastly on this note, there are other mode specifications that would allow you a different approach to bypassing this problem (namely, the use of the ``buffer'' mode specification), but you should never use these in VHDL. The approach presented here is considered a good use of VHDL.

\item This code uses the characteristic equation of a T~flip-flop in its implementation. We technically used a characteristic equation when we implemented the D~flip-flop but since the characteristic equation of a D~flip-flop is relatively trivial, you may not have been aware of it.
\item There are certain advantages to using T~flip-flops in some conditions, D~flip-flops are generally the storage element of choice using VHDL. If you do not have a specific reason for using some type of flip-flop other than a D~flip-flop, you probably should not.
\end{my_list}

\noindent
\begin{minipage}{0.99\linewidth}
\begin{lstlisting}[label=exe_17, caption=Solution to Example~17.]
-------------------------------------------------------------------
-- RET T Flip-flop model with active-low asynchronous set input. --
-------------------------------------------------------------------
-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity t_ff_s is
    port ( T,S,CLK :  in  std_logic;
                 Q :  out std_logic);
end t_ff_s;
-- entity
architecture my_t_ff_s of t_ff_s is
   signal t_tmp : std_logic; -- intermediate signal declaration
begin
   tff:  process (S,CLK)
   begin
      if (S = '0') then
         t_tmp <= '1';
      elsif (rising_edge(CLK)) then
         t_tmp <= T XOR t_tmp; -- temp output assignment
      end if;
   end process tff;

   Q <= t_tmp; -- final output assignment
end my_t_ff_s;
\end{lstlisting}
\end{minipage}

\section{Inducing Memory: Data-flow vs. Behavioral Modeling}
A major portion of digital design deals with sequential circuits. Generally speaking, most sequential circuit design is about synchronizing events to a clock edge. In other words, output changes only occur on a clock edge. The introduction to memory elements in VHDL presented in this section may lead the reader to think that memory in VHDL is only associated with behavioral modeling, but this is not the case. The same concept of inducing memory holds for data-flow modeling as well: not explicitly specifying an output for every possible input condition generates a latch (a storage element). And on this note, checking for unintended memory element generation is one of the duties of the digital designer. As you would imagine, memory elements add an element of needless complexity to the synthesized circuit.

One common approach for learning the syntax and mechanics of new computer languages is to implement the same task in as many different ways as possible. This approach utilizes the flexibility of the language and is arguably a valid approach to learning a new language. This is also the case in VHDL. But, probably more so in VHDL than other languages, there are specific ways of doing things and these things should always be done in these specific ways. Although it would be possible to generate flip-flops using data-flow models, most knowledgeable people examining your VHDL code would not initially be clear as to what exactly you are doing. As far as generating synchronous memory elements go, the methods outlined in this section are simply the optimal method of choice. This is one area not to be clever with.

\section{Important Points}
\begin{my_list}
\item Storage elements in VHDL are induced by not specifying output conditions for every possible input condition.

\item Unintended generation of storage elements is generally listed by the synthesizer as latch generation. Once again, latches are generated when there is an existing input condition to a circuit that does not have a corresponding output specification.

\item Memory elements can be induced by both data-flow and behavioral models.

\item If a signal declared in the entity declaration has a mode specifier of out, that signal cannot appear on the right-hand side of a signal assignment operator. This limitation is bypassed by using intermediate signals for any functional assignments and later assigning the intermediate signal to the output signal using a concurrent signal assignment statement.

\item The mode specification of \texttt{buffer} should be avoided in favor of intermediate signals.
\end{my_list}

\section{Exercises: Basic Memory Elements}

\vspace{15pt}
\noindent
%%%%%% EXERCISE 1 %%%%%%
\begin{minipage}{0.6\linewidth}
\textbf{EXERCISE 1.}
Provide a VHDL behavioral model of the D~flip-flop shown on the right. The \texttt{S} and \texttt{R} inputs are an active low asynchronous preset and clear. Assume both the \texttt{S} and \texttt{R} inputs will never be asserted simultaneously.
\end{minipage}
\begin{minipage}{0.39\linewidth}
\begin{flushleft}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.8,framed]
% GRID
% \draw[help lines] (0,0) grid (50,30);
% BOX
\draw (15,5) rectangle (30,25);
% INPUTS
\small
\node (a) at (15,2.5) {} circle (40pt); % this is the reference point
%\draw[red] ($(a)) circle (1pt);
\draw ($(a)+(8.5,24)$) |- ++(-19,3) node[above]{S};
\draw ($(a)+(8.5,23.2)$) circle (2pt);
\draw ($(a)+(0,20)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw ($(a)+(8.5,1.1)$) |- ++(-19,-3) node[above]{R};
\draw ($(a)+(8.5,1.6)$) circle (2pt);
% OUTPUTS
\draw ($(a)+(15,20)$) -- ++(10,0) node[above]{Q};
\draw ($(a)+(16.5,5)$) -- ++(8.5,0) node[above]{Q};
\draw ($(a)+(16,5)$) circle (2pt);
\end{tikzpicture}
\end{flushleft}
\end{minipage}

\vspace{15pt}
\noindent
%%%%%% EXERCISE 2 %%%%%%
\begin{minipage}{0.6\linewidth}
\textbf{EXERCISE 2.}
Provide a VHDL behavioral model of the D~flip-flop shown on the right. The \texttt{S} and \texttt{R} inputs are an active low asynchronous preset and clear. Assume the \texttt{S} input takes precedence over the \texttt{R} input in the case where both are asserted simultaneously.
\end{minipage}
\begin{minipage}{0.39\linewidth}
\begin{flushleft}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.8,framed]
% GRID
%\draw[help lines] (0,0) grid (50,30);
% BOX
\draw (15,5) rectangle (30,25);
% INPUTS
\small
\node (a) at (15,2.5) {} circle (40pt); % this is the reference point
%\draw[red] ($(a)) circle (1pt);
\draw ($(a)+(8.5,24)$) |- ++(-19,3) node[above]{S};
\draw ($(a)+(8.5,23.2)$) circle (2pt);
\draw ($(a)+(0,20)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw ($(a)+(8.5,1.1)$) |- ++(-19,-3) node[above]{R};
\draw ($(a)+(8.5,1.6)$) circle (2pt);
% OUTPUTS
\draw ($(a)+(15,20)$) -- ++(10,0) node[above]{Q};
\draw ($(a)+(16.5,5)$) -- ++(8.5,0) node[above]{Q};
\draw ($(a)+(16,5)$) circle (2pt);
\end{tikzpicture}
\end{flushleft}
\end{minipage}

\vspace{15pt}
\noindent
%%%%%% EXERCISE 3 %%%%%%
\begin{minipage}{0.6\linewidth}
\textbf{EXERCISE 3.}
Provide a VHDL behavioral model of the D~flip-flop shown on the right. The \texttt{S} and \texttt{R} inputs are synchronous preset and clear. Assume both the \texttt{S} and \texttt{R} inputs will never be asserted simultaneously.
\end{minipage}
\begin{minipage}{0.39\linewidth}
\begin{flushleft}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.8,framed]
% GRID
%\draw[help lines] (0,0) grid (50,30);
% BOX
\draw (15,5) rectangle (30,25);
% INPUTS
\small
\node (a) at (15,2.5) {} circle (40pt); % this is the reference point
%\draw[red] ($(a)) circle (1pt);
\draw ($(a)+(8.5,24)$) |- ++(-19,3) node[above]{S};
\draw ($(a)+(8.5,23.2)$) circle (2pt);
\draw ($(a)+(0,20)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw ($(a)+(8.5,1.1)$) |- ++(-19,-3) node[above]{R};
\draw ($(a)+(8.5,1.6)$) circle (2pt);
% OUTPUTS
\draw ($(a)+(15,20)$) -- ++(10,0) node[above]{Q};
\draw ($(a)+(16.5,5)$) -- ++(8.5,0) node[above]{Q};
\draw ($(a)+(16,5)$) circle (2pt);
\end{tikzpicture}
\end{flushleft}
\end{minipage}

\vspace{15pt}
\noindent
%%%%%% EXERCISE 4 %%%%%%
\begin{minipage}{0.6\linewidth}
\textbf{EXERCISE 4.}
Provide a VHDL behavioral model of the D~flip-flop shown on the right. The \texttt{S} and \texttt{R} inputs are an active low asynchronous preset and clear. If both the \texttt{S} and \texttt{R} inputs are asserted simultaneously, the output of the flip-flop will toggle.
\end{minipage}
\begin{minipage}{0.39\linewidth}
\begin{flushleft}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.8,framed]
% GRID
%\draw[help lines] (0,0) grid (50,30);
% BOX
\draw (15,5) rectangle (30,25);
% INPUTS
\small
\node (a) at (15,2.5) {} circle (40pt); % this is the reference point
%\draw[red] ($(a)) circle (1pt);
\draw ($(a)+(8.5,24)$) |- ++(-19,3) node[above]{S};
\draw ($(a)+(8.5,23.2)$) circle (2pt);
\draw ($(a)+(0,20)$) -- ++(-10,0) node[above]{D};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw ($(a)+(8.5,1.1)$) |- ++(-19,-3) node[above]{R};
\draw ($(a)+(8.5,1.6)$) circle (2pt);
% OUTPUTS
\draw ($(a)+(15,20)$) -- ++(10,0) node[above]{Q};
\draw ($(a)+(16.5,5)$) -- ++(8.5,0) node[above]{Q};
\draw ($(a)+(16,5)$) circle (2pt);
\end{tikzpicture}
\end{flushleft}
\end{minipage}

\vspace{15pt}
\noindent
%%%%%% EXERCISE 5 %%%%%%
\begin{minipage}{0.6\linewidth}
\textbf{EXERCISE 5.}
Provide a VHDL behavioral model of the T~flip-flop shown on the right. The \texttt{S} and \texttt{R} inputs are an active low asynchronous preset and clear. Assume both the \texttt{S} and \texttt{R} inputs will never be asserted simultaneously. Implement this flip-flop first using an equation description of the outputs and then using a behavioral description of the outputs.
\end{minipage}
\begin{minipage}{0.39\linewidth}
\begin{flushleft}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.8,framed]
% GRID
%\draw[help lines] (0,0) grid (50,30);
% BOX
\draw (15,5) rectangle (30,25);
% INPUTS
\small
\node (a) at (15,2.5) {} circle (40pt); % this is the reference point
%\draw[red] ($(a)) circle (1pt);
\draw ($(a)+(8.5,24)$) |- ++(-19,3) node[above]{S};
\draw ($(a)+(8.5,23.2)$) circle (2pt);
\draw ($(a)+(0,20)$) -- ++(-10,0) node[above]{T};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw ($(a)+(8.5,1.1)$) |- ++(-19,-3) node[above]{R};
\draw ($(a)+(8.5,1.6)$) circle (2pt);
% OUTPUTS
\draw ($(a)+(15,20)$) -- ++(10,0) node[above]{Q};
\draw ($(a)+(16.5,5)$) -- ++(8.5,0) node[above]{Q};
\draw ($(a)+(16,5)$) circle (2pt);
\end{tikzpicture}
\end{flushleft}
\end{minipage}

\vspace{15pt}
\noindent
%%%%%% EXERCISE 6 %%%%%%
\begin{minipage}{0.6\linewidth}
\textbf{EXERCISE 6.}
Provide a VHDL behavioral model of the T~flip-flop shown on the right. The \texttt{S} and \texttt{R} inputs are an active low asynchronous preset and clear. Assume both the \texttt{S} and \texttt{R} inputs will never be asserted simultaneously.
\end{minipage}
\begin{minipage}{0.39\linewidth}
\begin{flushleft}
\begin{tikzpicture}[x=1mm,y=1mm,line width=0.8pt,scale=0.8,framed]
% GRID
%\draw[help lines] (0,0) grid (50,30);
% BOX
\draw (15,5) rectangle (30,25);
% INPUTS
\small
\node (a) at (15,2.5) {} circle (40pt); % this is the reference point
%\draw[red] ($(a)) circle (1pt);
\draw ($(a)+(8.5,24)$) |- ++(-19,3) node[above]{S};
\draw ($(a)+(8.5,23.2)$) circle (2pt);
\draw ($(a)+(0,20)$) -- ++(-10,0) node[above]{T};
\draw ($(a)+(0,5)$) -- ++(-10,0) node[above]{CLK};
\draw ($(a)+(0,6)$) -- ++(1.5,-1) -- ++(-1.5,-1); % CLK triangle
\draw ($(a)+(8.5,1.1)$) |- ++(-19,-3) node[above]{R};
\draw ($(a)+(8.5,1.6)$) circle (2pt);
% OUTPUTS
\draw ($(a)+(15,20)$) -- ++(10,0) node[above]{Q};
\draw ($(a)+(16.5,5)$) -- ++(8.5,0) node[above]{Q};
\draw ($(a)+(16,5)$) circle (2pt);
\end{tikzpicture}
\end{flushleft}
\end{minipage}