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[Litex] "make setup" generates the signal list twice #34

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suppamax opened this issue Apr 4, 2022 · 0 comments
Open

[Litex] "make setup" generates the signal list twice #34

suppamax opened this issue Apr 4, 2022 · 0 comments
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@jeffdi
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error Something isn't working RTL Changes to verilog source

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suppamax commented Apr 4, 2022

When I run make setup from litex, the generated mgmt_core.v has signals declared twice.
The reason is that verilog._print_signals is not overwritten in caravel_platform.py and signals are declared also via _new_print_module
@suppamax suppamax mentioned this issue Apr 4, 2022
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@jeffdi jeffdi self-assigned this Sep 26, 2022
@jeffdi jeffdi moved this to Todo in Caravel Redesign Sep 27, 2022
@RTimothyEdwards RTimothyEdwards mentioned this issue Sep 30, 2022
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@RTimothyEdwards RTimothyEdwards added error Something isn't working RTL Changes to verilog source labels Oct 4, 2022
@jeffdi jeffdi removed this from Caravel Redesign Oct 6, 2022
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error Something isn't working RTL Changes to verilog source
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@RTimothyEdwards @suppamax @jeffdi