From ec53a414139ea277e669fa6dca0f6f44261c8059 Mon Sep 17 00:00:00 2001 From: Marwan Abbas Date: Tue, 22 Feb 2022 09:14:43 -0800 Subject: [PATCH] includes file from user_project --- verilog/dv/make/sim.makefile | 39 ++++++++-- verilog/includes/includes.gl+sdf.caravel | 2 +- verilog/includes/includes.gl.caravel | 2 +- verilog/includes/includes.rtl.caravel | 2 +- .../includes.rtl.caravel_user_project | 75 ------------------- 5 files changed, 34 insertions(+), 86 deletions(-) delete mode 100644 verilog/includes/includes.rtl.caravel_user_project diff --git a/verilog/dv/make/sim.makefile b/verilog/dv/make/sim.makefile index 182effd7..744f8adf 100644 --- a/verilog/dv/make/sim.makefile +++ b/verilog/dv/make/sim.makefile @@ -63,22 +63,45 @@ hex: ${BLOCKS:=.hex} ## RTL ifeq ($(SIM),RTL) - iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ - -f$(VERILOG_PATH)/includes/includes.rtl.$(CONFIG) -o $@ $< + ifeq ($(CONFIG),caravel_user_project) + iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< + else + iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.rtl.$(CONFIG) \ + -f$(CARAVEL_PATH)/rtl/__user_project_wrapper.v -o $@ $< + endif endif ## GL ifeq ($(SIM),GL) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ - -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) -o $@ $< + ifeq ($(CONFIG),caravel_user_project) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< + else + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ + -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + endif endif ## GL+SDF ifeq ($(SIM),GL_SDF) - cvc64 +interp \ - +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ - +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ - -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) $< + ifeq ($(CONFIG),caravel_user_project) + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \ + -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $< + else + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \ + -f $CARAVEL_PATH/gl/__user_project_wrapper.v $< + endif endif %.vcd: %.vvp diff --git a/verilog/includes/includes.gl+sdf.caravel b/verilog/includes/includes.gl+sdf.caravel index b984ae8b..eb10381d 100644 --- a/verilog/includes/includes.gl+sdf.caravel +++ b/verilog/includes/includes.gl+sdf.caravel @@ -38,7 +38,7 @@ $CARAVEL_PATH/gl/spare_logic_block.v $CARAVEL_PATH/gl/housekeeping.v $CARAVEL_PATH/gl/caravel_clocking.v $CARAVEL_PATH/gl/digital_pll.v -$CARAVEL_PATH/gl/__user_project_wrapper.v +// $CARAVEL_PATH/gl/__user_project_wrapper.v $CARAVEL_PATH/gl/user_id_programming.v $CARAVEL_PATH/gl/caravel.v diff --git a/verilog/includes/includes.gl.caravel b/verilog/includes/includes.gl.caravel index 133bdf54..e41565b0 100644 --- a/verilog/includes/includes.gl.caravel +++ b/verilog/includes/includes.gl.caravel @@ -56,7 +56,7 @@ -v $(CARAVEL_PATH)/gl/housekeeping.v -v $(CARAVEL_PATH)/gl/caravel_clocking.v -v $(CARAVEL_PATH)/gl/digital_pll.v --v $(CARAVEL_PATH)/gl/__user_project_wrapper.v +#-v $(CARAVEL_PATH)/gl/__user_project_wrapper.v -v $(CARAVEL_PATH)/gl/user_id_programming.v -v $(CARAVEL_PATH)/gl/caravel.v diff --git a/verilog/includes/includes.rtl.caravel b/verilog/includes/includes.rtl.caravel index 2cf52f7f..351ca686 100644 --- a/verilog/includes/includes.rtl.caravel +++ b/verilog/includes/includes.rtl.caravel @@ -44,7 +44,7 @@ -v $(CARAVEL_PATH)/rtl/housekeeping.v -v $(CARAVEL_PATH)/rtl/caravel_clocking.v -v $(CARAVEL_PATH)/rtl/digital_pll.v --v $(CARAVEL_PATH)/rtl/__user_project_wrapper.v +#-v $(CARAVEL_PATH)/rtl/__user_project_wrapper.v -v $(CARAVEL_PATH)/rtl/user_id_programming.v -v $(CARAVEL_PATH)/rtl/caravel.v diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project deleted file mode 100644 index f808be18..00000000 --- a/verilog/includes/includes.rtl.caravel_user_project +++ /dev/null @@ -1,75 +0,0 @@ -## VIP --v $(VERILOG_PATH)/dv/vip/tbuart.v --v $(VERILOG_PATH)/dv/vip/spiflash.v --v $(VERILOG_PATH)/dv/vip/wb_rw_test.v - -## DFFRAM Behavioral Model --v $(VERILOG_PATH)/dv/vip/DFFRAM.v - -## DFFRAM Full RTL -#-v $(VERILOG_PATH)/rtl/DFFRAM.v -#-v $(VERILOG_PATH)/rtl/DFFRAMBB.v - -# Mgmt Core Wrapper --v $(VERILOG_PATH)/rtl/defines.v --v $(VERILOG_PATH)/rtl/mgmt_core.v --v $(VERILOG_PATH)/rtl/mgmt_core_wrapper.v --v $(VERILOG_PATH)/rtl/VexRiscv_MinDebugCache.v - -# Caravel - -## These blocks need to stay in RTL --v $(CARAVEL_PATH)/rtl/pads.v --v $(CARAVEL_PATH)/rtl/defines.v --v $(CARAVEL_PATH)/rtl/user_defines.v --v $(CARAVEL_PATH)/rtl/mprj_io.v --v $(CARAVEL_PATH)/rtl/simple_por.v - -## These blocks only needed for RTL sims --v $(CARAVEL_PATH)/rtl/digital_pll_controller.v --v $(CARAVEL_PATH)/rtl/ring_osc2x13.v --v $(CARAVEL_PATH)/rtl/clock_div.v --v $(CARAVEL_PATH)/rtl/housekeeping_spi.v - --v $(CARAVEL_PATH)/rtl/chip_io.v --v $(CARAVEL_PATH)/rtl/mprj_logic_high.v --v $(CARAVEL_PATH)/rtl/mprj2_logic_high.v --v $(CARAVEL_PATH)/rtl/mgmt_protect.v --v $(CARAVEL_PATH)/rtl/mgmt_protect_hv.v --v $(CARAVEL_PATH)/rtl/gpio_control_block.v --v $(CARAVEL_PATH)/rtl/gpio_defaults_block.v --v $(CARAVEL_PATH)/rtl/gpio_logic_high.v --v $(CARAVEL_PATH)/rtl/xres_buf.v --v $(CARAVEL_PATH)/rtl/spare_logic_block.v --v $(CARAVEL_PATH)/rtl/housekeeping.v --v $(CARAVEL_PATH)/rtl/caravel_clocking.v --v $(CARAVEL_PATH)/rtl/digital_pll.v --v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v --v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v --v $(CARAVEL_PATH)/rtl/user_id_programming.v --v $(CARAVEL_PATH)/rtl/caravel.v - -## These blocks are manually designed --v $(CARAVEL_PATH)/gl/gpio_defaults_block_0403.v --v $(CARAVEL_PATH)/gl/gpio_defaults_block_1803.v - - -# STD CELLS - they need to be below the defines.v files - -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v - -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v - -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v - -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v - -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v - -v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v -#-v $(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v - - -## STD CELLS - they need to be below the defines.v files -#-v $(VERILOG_PATH)/cvc-pdk/sky130_ef_io.v -#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_io.v -#-v $(VERILOG_PATH)/cvc-pdk/primitives_hd.v -#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_sc_hd.v -#-v $(VERILOG_PATH)/cvc-pdk/primitives_hvl.v -#-v $(VERILOG_PATH)/cvc-pdk/sky130_fd_sc_hvl.v - -v $(VERILOG_PATH)/cvc-pdk/sky130_sram_2kbyte_1rw1r_32x512_8.v - \ No newline at end of file