diff --git a/.gitignore b/.gitignore index b4162c3e..f15f4b11 100644 --- a/.gitignore +++ b/.gitignore @@ -195,3 +195,4 @@ waves.shm/ ivl_vhdl_work/ RUN_* +*.raw diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst index 380db6d3..94f1f933 100644 --- a/CONTRIBUTING.rst +++ b/CONTRIBUTING.rst @@ -68,7 +68,7 @@ Ready to contribute? Here's how to set up `piel` for local development. $ mkvirtualenv piel $ cd piel/ - $ python setup.py develop + $ pip install -e . 4. Create a branch for local development:: diff --git a/README.md b/README.md index 38fe4efd..8c302985 100644 --- a/README.md +++ b/README.md @@ -1,15 +1,14 @@ # **P**hotonic **I**ntegrated **EL**ectronics - [![PyPI -Name](https://img.shields.io/badge/pypi-piel-blue)](https://pypi.python.org/pypi/piel) +Name](https://img.shields.io/badge/pypi-piel-blue?style=for-the-badge)](https://pypi.python.org/pypi/piel) [![PyPI -Version](https://img.shields.io/pypi/v/piel.svg)](https://pypi.python.org/pypi/piel) +Version](https://img.shields.io/pypi/v/piel.svg?style=for-the-badge)](https://pypi.python.org/pypi/piel) [![Build -Status](https://img.shields.io/travis/daquintero/piel.svg)](https://travis-ci.com/daquintero/piel) +Status](https://img.shields.io/travis/daquintero/piel.svg?style=for-the-badge)](https://travis-ci.com/daquintero/piel) [![Documentation -Status](https://readthedocs.org/projects/piel/badge/?version=latest)](https://piel.readthedocs.io/en/latest/?version=latest) -[![MIT](https://img.shields.io/github/license/gdsfactory/gdsfactory)](https://choosealicense.com/licenses/mit/) -[![Black](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black) +Status](https://readthedocs.org/projects/piel/badge/?style=for-the-badge)](https://piel.readthedocs.io/en/latest/?version=latest) +[![MIT](https://img.shields.io/github/license/gdsfactory/gdsfactory?style=for-the-badge)](https://choosealicense.com/licenses/mit/) +[![Black](https://img.shields.io/badge/code%20style-black-000000.svg?style=for-the-badge)](https://github.com/psf/black) Microservices to codesign photonics, electronics, communications, quantum, and more. diff --git a/docs/_static/img/examples/04_multi_domain_interconnect/our_short_resistive_heater.PNG b/docs/_static/img/examples/04_spice_cosimulation/our_short_resistive_heater.PNG similarity index 100% rename from docs/_static/img/examples/04_multi_domain_interconnect/our_short_resistive_heater.PNG rename to docs/_static/img/examples/04_spice_cosimulation/our_short_resistive_heater.PNG diff --git a/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.png b/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.png new file mode 100644 index 00000000..e5ee063e Binary files /dev/null and b/docs/_static/img/examples/04_spice_cosimulation/simple_transient_plot.png differ diff --git a/docs/autoapi/piel/index.rst b/docs/autoapi/piel/index.rst index 48d66006..dd68e289 100644 --- a/docs/autoapi/piel/index.rst +++ b/docs/autoapi/piel/index.rst @@ -111,6 +111,10 @@ Functions piel.get_file_line_by_keyword piel.read_file_lines piel.run_openlane_flow + piel.configure_ngspice_simulation + piel.configure_operating_point_simulation + piel.configure_transient_simulation + piel.run_simulation piel.convert_numeric_to_prefix piel.get_sdense_ports_index piel.sax_to_s_parameters_standard_matrix @@ -1146,6 +1150,62 @@ Attributes :returns: None +.. py:function:: configure_ngspice_simulation(run_directory: piel.config.piel_path_types = '.') + + This function configures the NGSPICE simulation for the circuit and returns a simulation class. + + :param run_directory: Directory where the simulation will be run + :type run_directory: piel_path_types + + :returns: Configured NGSPICE simulation options + :rtype: simulation_options + + +.. py:function:: configure_operating_point_simulation(testbench: hdl21.Module, **kwargs) + + This function configures the DC operating point simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param \*\*kwargs: Additional arguments to be passed to the operating point simulation such as name. + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: configure_transient_simulation(testbench: hdl21.Module, stop_time_s: float, step_time_s: float, **kwargs) + + This function configures the transient simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param stop_time_s: Stop time of the simulation in seconds + :type stop_time_s: float + :param step_time_s: Step time of the simulation in seconds + :type step_time_s: float + :param \*\*kwargs: Additional arguments to be passed to the transient simulation + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: run_simulation(simulation: hdl21.sim.Sim, simulator_name: Literal[ngspice] = 'ngspice', simulation_options: Optional[vlsirtools.spice.SimOptions] = None, to_csv: bool = True) + + This function runs the transient simulation for the circuit and returns the results. + + :param simulation: HDL21 simulation class + :type simulation: h.sim.Sim + :param simulator_name: Name of the simulator + :type simulator_name: Literal["ngspice"] + :param simulation_options: Simulation options + :type simulation_options: Optional[vsp.SimOptions] + :param to_csv: Whether to save the results to a csv file + :type to_csv: bool + + :returns: Simulation results + :rtype: results + + .. py:function:: convert_numeric_to_prefix(value: float) This function converts a numeric value to a number under a SPICE unit closest to the base prefix. This allows us to connect a particular number real output, into a term that can be used in a SPICE netlist. diff --git a/docs/autoapi/piel/tools/hdl21/index.rst b/docs/autoapi/piel/tools/hdl21/index.rst index 880a9c0e..1a5f946d 100644 --- a/docs/autoapi/piel/tools/hdl21/index.rst +++ b/docs/autoapi/piel/tools/hdl21/index.rst @@ -24,10 +24,70 @@ Functions .. autoapisummary:: + piel.tools.hdl21.configure_ngspice_simulation + piel.tools.hdl21.configure_operating_point_simulation + piel.tools.hdl21.configure_transient_simulation + piel.tools.hdl21.run_simulation piel.tools.hdl21.convert_numeric_to_prefix +.. py:function:: configure_ngspice_simulation(run_directory: piel.config.piel_path_types = '.') + + This function configures the NGSPICE simulation for the circuit and returns a simulation class. + + :param run_directory: Directory where the simulation will be run + :type run_directory: piel_path_types + + :returns: Configured NGSPICE simulation options + :rtype: simulation_options + + +.. py:function:: configure_operating_point_simulation(testbench: hdl21.Module, **kwargs) + + This function configures the DC operating point simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param \*\*kwargs: Additional arguments to be passed to the operating point simulation such as name. + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: configure_transient_simulation(testbench: hdl21.Module, stop_time_s: float, step_time_s: float, **kwargs) + + This function configures the transient simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param stop_time_s: Stop time of the simulation in seconds + :type stop_time_s: float + :param step_time_s: Step time of the simulation in seconds + :type step_time_s: float + :param \*\*kwargs: Additional arguments to be passed to the transient simulation + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: run_simulation(simulation: hdl21.sim.Sim, simulator_name: Literal[ngspice] = 'ngspice', simulation_options: Optional[vlsirtools.spice.SimOptions] = None, to_csv: bool = True) + + This function runs the transient simulation for the circuit and returns the results. + + :param simulation: HDL21 simulation class + :type simulation: h.sim.Sim + :param simulator_name: Name of the simulator + :type simulator_name: Literal["ngspice"] + :param simulation_options: Simulation options + :type simulation_options: Optional[vsp.SimOptions] + :param to_csv: Whether to save the results to a csv file + :type to_csv: bool + + :returns: Simulation results + :rtype: results + + .. py:function:: convert_numeric_to_prefix(value: float) This function converts a numeric value to a number under a SPICE unit closest to the base prefix. This allows us to connect a particular number real output, into a term that can be used in a SPICE netlist. diff --git a/docs/autoapi/piel/tools/hdl21/simulator/index.rst b/docs/autoapi/piel/tools/hdl21/simulator/index.rst index 1f44d9e7..aac7f865 100644 --- a/docs/autoapi/piel/tools/hdl21/simulator/index.rst +++ b/docs/autoapi/piel/tools/hdl21/simulator/index.rst @@ -13,10 +13,64 @@ Functions .. autoapisummary:: + piel.tools.hdl21.simulator.configure_ngspice_simulation + piel.tools.hdl21.simulator.configure_operating_point_simulation piel.tools.hdl21.simulator.configure_transient_simulation + piel.tools.hdl21.simulator.run_simulation -.. py:function:: configure_transient_simulation(circuit: hdl21.Module, stop_time_s: float, step_time_s: float) +.. py:function:: configure_ngspice_simulation(run_directory: piel.config.piel_path_types = '.') - This function configures the transient simulation for the circuit. + This function configures the NGSPICE simulation for the circuit and returns a simulation class. + + :param run_directory: Directory where the simulation will be run + :type run_directory: piel_path_types + + :returns: Configured NGSPICE simulation options + :rtype: simulation_options + + +.. py:function:: configure_operating_point_simulation(testbench: hdl21.Module, **kwargs) + + This function configures the DC operating point simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param \*\*kwargs: Additional arguments to be passed to the operating point simulation such as name. + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: configure_transient_simulation(testbench: hdl21.Module, stop_time_s: float, step_time_s: float, **kwargs) + + This function configures the transient simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param stop_time_s: Stop time of the simulation in seconds + :type stop_time_s: float + :param step_time_s: Step time of the simulation in seconds + :type step_time_s: float + :param \*\*kwargs: Additional arguments to be passed to the transient simulation + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: run_simulation(simulation: hdl21.sim.Sim, simulator_name: Literal[ngspice] = 'ngspice', simulation_options: Optional[vlsirtools.spice.SimOptions] = None, to_csv: bool = True) + + This function runs the transient simulation for the circuit and returns the results. + + :param simulation: HDL21 simulation class + :type simulation: h.sim.Sim + :param simulator_name: Name of the simulator + :type simulator_name: Literal["ngspice"] + :param simulation_options: Simulation options + :type simulation_options: Optional[vsp.SimOptions] + :param to_csv: Whether to save the results to a csv file + :type to_csv: bool + + :returns: Simulation results + :rtype: results diff --git a/docs/autoapi/piel/tools/index.rst b/docs/autoapi/piel/tools/index.rst index 0e745194..7716c2fc 100644 --- a/docs/autoapi/piel/tools/index.rst +++ b/docs/autoapi/piel/tools/index.rst @@ -68,6 +68,10 @@ Functions piel.tools.get_file_line_by_keyword piel.tools.read_file_lines piel.tools.run_openlane_flow + piel.tools.configure_ngspice_simulation + piel.tools.configure_operating_point_simulation + piel.tools.configure_transient_simulation + piel.tools.run_simulation piel.tools.convert_numeric_to_prefix piel.tools.get_sdense_ports_index piel.tools.sax_to_s_parameters_standard_matrix @@ -669,6 +673,62 @@ Attributes :returns: None +.. py:function:: configure_ngspice_simulation(run_directory: piel.config.piel_path_types = '.') + + This function configures the NGSPICE simulation for the circuit and returns a simulation class. + + :param run_directory: Directory where the simulation will be run + :type run_directory: piel_path_types + + :returns: Configured NGSPICE simulation options + :rtype: simulation_options + + +.. py:function:: configure_operating_point_simulation(testbench: hdl21.Module, **kwargs) + + This function configures the DC operating point simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param \*\*kwargs: Additional arguments to be passed to the operating point simulation such as name. + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: configure_transient_simulation(testbench: hdl21.Module, stop_time_s: float, step_time_s: float, **kwargs) + + This function configures the transient simulation for the circuit and returns a simulation class. + + :param testbench: HDL21 testbench + :type testbench: Module + :param stop_time_s: Stop time of the simulation in seconds + :type stop_time_s: float + :param step_time_s: Step time of the simulation in seconds + :type step_time_s: float + :param \*\*kwargs: Additional arguments to be passed to the transient simulation + + :returns: HDL21 simulation class + :rtype: Simulation + + +.. py:function:: run_simulation(simulation: hdl21.sim.Sim, simulator_name: Literal[ngspice] = 'ngspice', simulation_options: Optional[vlsirtools.spice.SimOptions] = None, to_csv: bool = True) + + This function runs the transient simulation for the circuit and returns the results. + + :param simulation: HDL21 simulation class + :type simulation: h.sim.Sim + :param simulator_name: Name of the simulator + :type simulator_name: Literal["ngspice"] + :param simulation_options: Simulation options + :type simulation_options: Optional[vsp.SimOptions] + :param to_csv: Whether to save the results to a csv file + :type to_csv: bool + + :returns: Simulation results + :rtype: results + + .. py:function:: convert_numeric_to_prefix(value: float) This function converts a numeric value to a number under a SPICE unit closest to the base prefix. This allows us to connect a particular number real output, into a term that can be used in a SPICE netlist. diff --git a/docs/examples.rst b/docs/examples.rst index 45ee215f..0255fcb5 100644 --- a/docs/examples.rst +++ b/docs/examples.rst @@ -13,5 +13,6 @@ Examples examples/02_cocotb_simulation examples/03_sax_basics examples/03a_sax_cocotb_cosimulation - examples/04_spice_cosimulation + examples//04_spice_cosimulation/04_spice_cosimulation + examples/04a_power_consumption_estimation examples/05_quantum_integration_basics diff --git a/docs/examples/04_spice_cosimulation.py b/docs/examples/04_spice_cosimulation/04_spice_cosimulation.py similarity index 68% rename from docs/examples/04_spice_cosimulation.py rename to docs/examples/04_spice_cosimulation/04_spice_cosimulation.py index a65aecdc..9f416bba 100644 --- a/docs/examples/04_spice_cosimulation.py +++ b/docs/examples/04_spice_cosimulation/04_spice_cosimulation.py @@ -2,10 +2,11 @@ # This example demonstrates the modelling of multi-physical component interconnection and system design. -import sys from gdsfactory.components import mzi2x2_2x2_phase_shifter import hdl21 as h +import pandas as pd import piel +import sys # ## Start from `gdsfactory` @@ -56,7 +57,7 @@ our_resistive_mzi_2x2_2x2_phase_shifter # - -# ![mzi2x2_2x2_phase_shifter](../_static/img/examples/03a_sax_active_cosimulation/mzi2x2_phase_shifter.PNG) +# ![mzi2x2_2x2_phase_shifter](../../_static/img/examples/03a_sax_active_cosimulation/mzi2x2_phase_shifter.PNG) our_resistive_mzi_2x2_2x2_phase_shifter_netlist = ( our_resistive_mzi_2x2_2x2_phase_shifter.get_netlist(exclude_port_types="optical") @@ -83,7 +84,7 @@ our_short_resistive_mzi_2x2_2x2_phase_shifter.show() our_short_resistive_mzi_2x2_2x2_phase_shifter.plot_widget() -# ![our_short_resistive_heater](../_static/img/examples/04_multi_domain_interconnect/our_short_resistive_heater.PNG) +# ![our_short_resistive_heater](../../_static/img/examples/04_spice_cosimulation/our_short_resistive_heater.PNG) # You can also find out more information of this component through: @@ -116,7 +117,7 @@ # # `piel` does this for you already: -our_resistive_heater_spice_netlist = piel.gdsfactory_netlist_with_hdl21_models( +our_resistive_heater_spice_netlist = piel.gdsfactory_netlist_with_hdl21_generators( our_resistive_heater_netlist ) our_resistive_heater_spice_netlist @@ -327,6 +328,7 @@ example_straight_resistor = piel_hdl21_models["straight"]() h.netlist(example_straight_resistor, sys.stdout, fmt="spice") + # ``` # * Anonymous `circuit.Package` # * Generated by `vlsirtools.SpiceNetlister` @@ -347,6 +349,140 @@ # ### Creating our Stimulus -# Let's first look into how to map a numpy data into a SPICE waveform. We will create a testbench using the `hdl21` interface. So the first thing is that we need to add our *stimulus* sources, or otherwise where would our pulses come from. We need to construct this into our testbench module. +# Let's first look into how to map a numpy data into a SPICE waveform. We will create a testbench using the `hdl21` interface. So the first thing is that we need to add our *stimulus* sources, or otherwise where would our pulses come from. We need to construct this into our testbench module. This means we need to generate the connectivity of our signal sources in relation to the ports of our circuit. We create a custom testbench module that we will use to perform this simulation. This needs to contain also our voltage sources for whatever test that we would be performing. + + +@h.module +class OperatingPointTb: + """# Basic Extracted Device DC Operating Point Testbench""" + + VSS = h.Port() # The testbench interface: sole port VSS - GROUND + VDC = h.Vdc(dc=1)(n=VSS) # A DC voltage source + + # Our component under test + dut = example_straight_resistor() + dut.e1 = VDC.p + dut.e2 = VSS + + +# In this basic test, we can analyse the DC operating point relationship for this circuit. Now, in order to make these type of simulations more automated to run at scale, `piel` provides some wrapper functions that can be parameterised with most common simulation parameters: + +# #### A Simple DC Operating Point Simulation + +simple_operating_point_simulation = piel.configure_operating_point_simulation( + testbench=OperatingPointTb, name="simple_operating_point_simulation" +) +simple_operating_point_simulation + +# ```python +# Sim(tb=Module(name=OperatingPointTb), attrs=[Op(name='operating_point_tb'), Save(targ=)], name='Simulation') +# ``` + +# We can now run the simulation using `ngpsice`. Make sure you have it installed, although this will be automatic in the *IIC-OSIC-TOOLS* environment: + +results = piel.run_simulation(simulation=simple_operating_point_simulation) +results + +# ```python +# SimResult(an=[OpResult(analysis_name='operating_point_tb', data={'v(xtop.vdc_p)': 1.0, 'i(v.xtop.vvdc)': -0.001})]) +# ``` + +# We can access the data as a dictionary too: + +results.an[0].data + +# ```python +# {'v(xtop.vdc_p)': 1.0, 'i(v.xtop.vvdc)': -0.001} +# ``` + +# #### A Simple Transient Simulation +# + +# Let's assume we want to simulate in time how a pulse propagates through our circuit. A resistor on its own will have a linear relationship with the pulse, which means we should see how the current changes from the input pulse in time accordingly. For clarity, we will make a new testbench, even if there are ways to combine them. + + +@h.module +class TransientTb: + """# Basic Extracted Device DC Operating Point Testbench""" + + VSS = h.Port() # The testbench interface: sole port VSS - GROUND + VPULSE = h.Vpulse( + delay=1 * h.prefix.m, + v1=-1000 * h.prefix.m, + v2=1000 * h.prefix.m, + period=100 * h.prefix.m, + rise=10 * h.prefix.m, + fall=10 * h.prefix.m, + width=75 * h.prefix.m, + )( + n=VSS + ) # A configured voltage pulse source + + # Our component under test + dut = example_straight_resistor() + dut.e1 = VPULSE.p + dut.e2 = VSS + + +# Again we use a simple `piel` wrapper: + +simple_transient_simulation = piel.configure_transient_simulation( + testbench=TransientTb, + stop_time_s=200e-3, + step_time_s=1e-4, + name="simple_transient_simulation", +) +simple_transient_simulation + +# ```python +# Sim(tb=Module(name=TransientTb), attrs=[Tran(tstop=0.1*UNIT, tstep=0.0001*UNIT, name='transient_tb')], name='Simulation') +# ``` + +piel.run_simulation(simple_transient_simulation, to_csv=True) + +# When you run the simulation using the `piel` `run_simulation` command, there is a `to_csv` flag that allows us to save the data and access it afterwards. We access the transient simulation in Pandas accordingly: + +transient_simulation_results = pd.read_csv("TransientTb.csv") +transient_simulation_results.iloc[20:40] + +# | | Unnamed: 0 | time | v(xtop.vpulse_p) | s | +# |---:|----------:|--------:|-----------------:|------------------:| +# | 20 | 20 | 0.00107 | -0.986 | 0.000986 | +# | 21 | 21 | 0.00115 | -0.97 | 0.00097 | +# | 22 | 22 | 0.00125 | -0.95 | 0.00095 | +# | 23 | 23 | 0.00135 | -0.93 | 0.00093 | +# | 24 | 24 | 0.00145 | -0.91 | 0.00091 | +# | 25 | 25 | 0.00155 | -0.89 | 0.00089 | +# | 26 | 26 | 0.00165 | -0.87 | 0.00087 | +# | 27 | 27 | 0.00175 | -0.85 | 0.00085 | +# | 28 | 28 | 0.00185 | -0.83 | 0.00083 | +# | 29 | 29 | 0.00195 | -0.81 | 0.00081 | +# | 30 | 30 | 0.00205 | -0.79 | 0.00079 | +# | 31 | 31 | 0.00215 | -0.77 | 0.00077 | +# | 32 | 32 | 0.00225 | -0.75 | 0.00075 | +# | 33 | 33 | 0.00235 | -0.73 | 0.00073 | +# | 34 | 34 | 0.00245 | -0.71 | 0.00071 | +# | 35 | 35 | 0.00255 | -0.69 | 0.00069 | +# | 36 | 36 | 0.00265 | -0.67 | 0.00067 | +# | 37 | 37 | 0.00275 | -0.65 | 0.00065 | +# | 38 | 38 | 0.00285 | -0.63 | 0.00063 | +# | 39 | 39 | 0.00295 | -0.61 | 0.00061 | +# + +# We can plot our simulation data accordingly: + +simple_transient_plot = piel.visual.plot_simple_multi_row( + data=transient_simulation_results, + x_axis_column_name="time", + row_list=[ + "v(xtop.vpulse_p)", + "i(v.xtop.vvpulse)", + ], + y_axis_title_list=["v(v.xtop.vvpulse)", "i(v.xtop.vvpulse)", "o4 Phase"], +) + +# ![simple_transient_plot](../../_static/img/examples/04_spice_cosimulation/simple_transient_plot.PNG) + +# #### Automation -# ### Mixed-Signal Electronic Photonic Simulation Methodology +# Now, these transient simulations are something you might want to very configure depending on the type of signals that you might want to verify. However, we can provide some basic parameterised simple functions such as step responses and so on. So instead of having to write everything above, you can also just run the following, for example: WIP diff --git a/docs/examples/04_spice_cosimulation/OperatingPointTb.csv b/docs/examples/04_spice_cosimulation/OperatingPointTb.csv new file mode 100644 index 00000000..8901fc1f --- /dev/null +++ b/docs/examples/04_spice_cosimulation/OperatingPointTb.csv @@ -0,0 +1,2 @@ +,v(xtop.vdc_p),i(v.xtop.vvdc) +0,1.0,-0.001 diff --git a/docs/examples/04_spice_cosimulation/TransientTb.csv b/docs/examples/04_spice_cosimulation/TransientTb.csv new file mode 100644 index 00000000..3a3fb642 --- /dev/null +++ b/docs/examples/04_spice_cosimulation/TransientTb.csv @@ -0,0 +1,2033 @@ +,time,v(xtop.vpulse_p),i(v.xtop.vvpulse) +0,0.0,-1.0,0.001 +1,1.0000000000000002e-06,-1.0,0.001 +2,2.0000000000000003e-06,-1.0,0.001 +3,4.000000000000001e-06,-1.0,0.001 +4,8.000000000000001e-06,-1.0,0.001 +5,1.6000000000000003e-05,-1.0,0.001 +6,3.2000000000000005e-05,-1.0,0.001 +7,6.400000000000001e-05,-1.0,0.001 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b/docs/examples/04_spice_cosimulation/netlist.raw differ diff --git a/docs/examples/04_spice_cosimulation/netlist.sp b/docs/examples/04_spice_cosimulation/netlist.sp new file mode 100644 index 00000000..a15e5c14 --- /dev/null +++ b/docs/examples/04_spice_cosimulation/netlist.sp @@ -0,0 +1,41 @@ +* `ngspice` Sim Input for `__main__.TransientTb` +* Generated by `vlsirtools.NgspiceNetlister` +* +* Anonymous `circuit.Package` +* Generated by `vlsirtools.NgspiceNetlister` +* + +.SUBCKT Straight__ ++ e1 e2 +* No parameters + +rr1 ++ e1 e2 ++ 1000 +* No parameters + + +.ENDS + +.SUBCKT TransientTb ++ VSS +* No parameters + +vVPULSE ++ VPULSE_p VSS ++ pulse ('-1000m' '1000m' '1m' '10m' '10m' '75m' '100m') +* No parameters + + +xdut ++ VPULSE_p VSS ++ Straight__ +* No parameters + + +.ENDS + +xtop 0 TransientTb // Top-Level DUT + + +.tran 0.0001 0.2 diff --git a/docs/examples/04a_power_consumption_estimation.py b/docs/examples/04a_power_consumption_estimation.py new file mode 100644 index 00000000..cf2dc09e --- /dev/null +++ b/docs/examples/04a_power_consumption_estimation.py @@ -0,0 +1,13 @@ +# # Mixed-Signal & Photonic Power Consumption Calculation + +# One desired output of an electrical model simulation is an extraction of the power consumption of the circuit. Fundamentally, this is dependent on the time and the operation performed. Hence, to estimate an average power consumption, it is more effective to define the power consumption of a particular operation, and extract the power consumption for the frequency at which this operation is performed. +# +# In this case, we are defining the energy of the operation at particular nodes of the circuit. For example, we know a resisitve heater will dissipate all of its current consumption as thermal power. However, we also need to evaluate the whole circuit. We can know how much energy our DC or RF power supply is providing by measuring the voltage and current supplied accordingly. In a digital circuit, depending on the frequency of the operation, we know how often there is a signal rise and fall, in both cases forcing digital transistors to operate in the linear regime and consuming more power than in saturation mode. We also need to account the range of time the signals are in saturation mode, as even in CMOS idle state there is a minimal power consumption that is important as the circuit scales into VLSI/EP. +# +# Note that through the SPICE simulations, we can extract the energy required at each operation with greater accuracy than analytically and the complexity of this is configuring the testbench appropriately in order to account for this. + +# + +# + +# diff --git a/docs/sections/codesign/electro_optic_time_domain.md b/docs/sections/codesign/electro_optic_time_domain.md deleted file mode 100644 index 9cf7bf57..00000000 --- a/docs/sections/codesign/electro_optic_time_domain.md +++ /dev/null @@ -1,15 +0,0 @@ -# Electro-Optic Time Domain - -Electronic and optical simulations need to be synchronised into a single time domain to have a continuous signal. This means that it is necessary to integrate electrical and optical solvers in some form and to some level of reasonable translation. It is not necessary to simulate a whole system at picosecond resolution to observe photonic transient effects, but to observe transient effects, picosecond resolution might be desired - whilst steady state might not. - -This leads to a complex proposition: how to integrate transient and steady state time-domain solvers to simulate both electronics and photonics systems? `piel` solves this in a particular way: transients are computed in high resolution and steady-state is computed operationally. - -However, this leads to another further complexity, how to integrate analog electronic solvers that might represent our individually connected devices and interconnect, in relation to the rest of the electronic driving system. For example, different heater phase shifters might have different resistances, and although the ports might be the same, they might also have a different interconnect. - -## Tools Integration - -The implementation mechanism followed is to create parametric SPICE components that can be closely integrated with our existing device models and have a mapping to the electronic and photonic simulation software. The way this is implemented also follows microservices architectures as to minimise the computational architecture required for these systems. - -## Photonic Time Delay Synchronisation - -Another complexity of simulating these systems is that photonic pulses might also be propagating in time alongside the electronic signals. `sax` already implements some functionality to analyse the time-delay of such photonic circuits, but a resolution mechanism is required to interconnect these circuits together and a corresponding time-delay model needs to be provided to the components. diff --git a/docs/sections/codesign/index.rst b/docs/sections/codesign/index.rst index bd042648..b9b86860 100644 --- a/docs/sections/codesign/index.rst +++ b/docs/sections/codesign/index.rst @@ -5,4 +5,5 @@ Co-Design Functionality :caption: Contents: parametric - electro_optic_time_domain + power_time_metrics + mixed_signal_electronic_photonic diff --git a/docs/sections/codesign/mixed_signal_electronic_photonic.rst b/docs/sections/codesign/mixed_signal_electronic_photonic.rst new file mode 100644 index 00000000..6cf935eb --- /dev/null +++ b/docs/sections/codesign/mixed_signal_electronic_photonic.rst @@ -0,0 +1,170 @@ +Mixed-Signal Electronic Photonic Simulation +=========================================== + +One of the main complexities of this simulation software is the mapping +of different dimensions of time. For example, the time of the laser wave +is has its electromagnetic components changing in the femtosecond +regime, whereas digital signals may be changing in the nanosecond +regime. This inherently creates a level of complexity and computational +optimisation required to simulate photonic and electronic networks that +standard electronics does not have to solve. + +Electronic and optical simulations need to be synchronised into a single +time domain to have a continuous signal. This means that it is necessary +to integrate electrical and optical solvers in some form and to some +level of reasonable translation. It is not necessary to simulate a whole +system at picosecond resolution to observe photonic transient effects, +but to observe transient effects, picosecond resolution might be desired +- whilst steady state might not. + +This leads to a complex proposition: how to integrate transient and +steady state time-domain solvers to simulate both electronics and +photonics systems? ``piel`` solves this in a particular way: transients +are computed in high resolution and steady-state is computed +operationally. + +However, this leads to another further complexity, how to integrate +analog electronic solvers that might represent our individually +connected devices and interconnect, in relation to the rest of the +electronic driving system. For example, different heater phase shifters +might have different resistances, and although the ports might be the +same, they might also have a different interconnect. + +Implementation Principle +------------------------ + +The implementation ``piel`` proposes is basic: + +- Modularise the time-domain operations +- Compute photonic and electronic transients only when they are + changing +- Append the corresponding data into a total global time with various + levels of resolution depending on the reference signal + +The goal is to enable to minimize computational cost of simulating such +a system, whilst being flexible and simple enough for any potential +system simulation configuration. This means that we are not simulating +an electronic and photonic system at a femto-second resolution, but we +still resolve the time-scales throughout signal transitions if we +desire. + +The electronic simulation implementation is what could be called +micro-SPICE in the sense that it is a minimal implementation of +transition simulation for a circuit. + +Tools Integration +----------------- + +The implementation mechanism followed is to create parametric SPICE +components that can be closely integrated with our existing device +models and have a mapping to the electronic and photonic simulation +software. The way this is implemented also follows microservices +architectures as to minimise the computational architecture required for +these systems. + +Potential Integration Schemes Discussion +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +TODO WIP + +One potential implementation of operation specific electronic transient +modelling is fundamental. Say, an electronic circuit is idle. This means +for the period of time that this circuit is idle and the environment is +constant, it can be approximated that the circuit is in a very similar +constant state with some level of variation dependent only on external +factors eg. temperature or so on. We can also say that the initial +conditions of the circuit, say some DC biasing, +voltage-controlled-current-sources or current-controlled-voltage-sources +DC, or similar are controlled by signals that may be external to the +circuit in question. Now, this is valid whenever there is no remaining +transient memory effects on the initial condition of the circuit, in +this case you need to model full transient effects as in normal SPICE. + +**Why is this analysis important?** Photonic operations and electronic +operations may not be occurring at the same rate. The optical signals +may be changing when the electronics is steady, the electronic signals +may be changing when the photonics is steady, or the electronics and the +photonics are changing both at the same time. These are the potential +scenarios that time-dependent simulations must account for. + +To try to build a monolithic simulator that can solve for all of these +domains at the same time limits the potential further multi-physical +modelling of more complex systems, such as quantum states. As such, we +want to be as open and as modular as possible in order to make this +simulation tool as useful as possible. + +Say, our electronic circuit is initially in idle state (which we control +the external parameters that affect this state), and we can control +initial conditions such as the DC biasing and other time-independent +states of our circuit. An opto-electronic signal creates a +time-dependent transient input signal, and we begin our analogue +simulation of our circuit, the pulse has an end width, and the +time-dependent input signal reduces to back to a zero or steady noisy +time-independent input. The internal time-dependent properties of the +circuit reset to their time-independent steady-state. + +Then there is the other aspect of complexity, which is how to enable the +multi-domains to access the other domain simulation data state. + +I know some experienced people who are reading this are probably +thinking: why bother even doing this, surely tools such as Cadence +already solve this through their mixed-signals AMS simulators. However, +any extension of this is strongly limited by their often incomplete +documentation and closed-source software. It is also limited by +excluding people who do not know Verilog-A (even if I do), such as many +photonics engineers who design their chips in Python. This is some +motivation behind a ``piel`` design flow. + +One way is simply not allow them to access any other domain than their +own. + +References on mixed-signal simulation: \* `Verilog-AMS +Flow `__ +\* `cocotb examples - Mixed-signal +(analog/digital) `__ + +At the digital time-step, there is a possibility that an analogue signal +contains memory or previous states from the transitions. This creates an +aspect of complexity in modelling these systems. It means that the +time-synchronisation between the digital and analogue system must be +possible. The aspect of complexity is the multi-domain interaction +between the solvers, for example, if the digital solver is triggered by +a photonic-analogue signal or related. + +However, this is possible by implementing subroutines. In ``cocotb``, +the simulations are run as asynchronous coroutines. We can follow this +exact principle in terms of implementing a multi-domain simulatior. Each +``cocotb`` simulation has a ``Timer``, and it is possible that for every +step in time that we desire, we can implement another subroutine. This +would be easy to do if the photonic and analogue simulations were +*time-independent* because then the digital signals control the +operation flow, and it can just be considered a functional-based system +dominated by the digital ``Timer``. it is not particularly complicated +either to have feedback in between digital-photonic logic as through +that subroutine, we have full control over the triggering of digital +signals and related. However, my question of complexity really returns +to the analogue interaction of the signals. If it is digitally-directed, +and there is no analogue feedback interaction onto the digital logic, +then the co-routine would not have to change and is not affected other +than driving the analogue signals. + +Part of the question becomes on having to run an analogue simulation at +the same time as the digital one in order to verify that there would not +be remnant analogue memory in between the driving pulses. This makes +sense in particular when the digital ``Timer`` clock overlaps in between +the analogue signal as this changes the initial state of the analogue +simulation. We could keep a track of the initial state, but it might be +a bit complex even when considering a standard RC network and driving +pulses accordingly. The other way to do so, is to perform the SPICE +simulation, and discretize at particular points in time as is the way +with AMS. + +Photonic Time Delay Synchronisation +----------------------------------- + +Another complexity of simulating these systems is that photonic pulses +might also be propagating in time alongside the electronic signals. +``sax`` already implements some functionality to analyse the time-delay +of such photonic circuits, but a resolution mechanism is required to +interconnect these circuits together and a corresponding time-delay +model needs to be provided to the components. diff --git a/docs/sections/codesign/power_time_metrics.rst b/docs/sections/codesign/power_time_metrics.rst new file mode 100644 index 00000000..a695ba3c --- /dev/null +++ b/docs/sections/codesign/power_time_metrics.rst @@ -0,0 +1,242 @@ +System Metrics +============== + +Power Analysis +-------------- + +Let us first begin considering the digital design metrics that are +important for us to understand the electrical operation characteristics +of mixed electronic-photonic systems. Most of these are redefined to +include photonic loads based on *Digital Integrated Circuits, A Design +Perspective* by Jan Rabaey. Page numbers are provided accordingly. + +Power Consumption Definitions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Peak Power +^^^^^^^^^^ + +A design can have a peak power :math:`P_{peak}` which basically involves +the maximum power consumption possible by the total photonic and +electronic system. If we have a single supply voltage to our system +:math:`V_{supply}`, then we can define it as: + +.. math:: + + + P_{peak} = i_{peak}V_{supply} = \text{max}\left(p(t)\right) + +If we have :math:`N` multiple supply voltages to our system, which is +more likekly the case in a mixed-signal digital and analogue supplies, +and potentially another external photonic electrical supply, then we can +define the total peak power of the system as: + +.. math:: + + + P_{peak,possible} = \sum_0^N i_{peak,N}V_{supply,N} = \sum_0^N \text{max}\left(p_N(t)\right) + +In reality, we need to think of the maximum power that can be drawn by +the maximum power consuming operation, which may not involve all +supplies operating at the maximum draw. However, if you want a +conservative estimate, you can assume that is it possible that all +supplies are operating at their maximum current draw :math:`i_{peak}`. +An generic maximum power defined as the highest consuming state of the +system, where not all supplies are operating at their maximum +:math:`i_{peak}` power can then be defined dependent on an consumption +efficiency parameter :math:`\eta_N` for the highest operation load: + +.. math:: + + + P_{peak,operation} = \sum_0^N \eta_N i_{peak,N}V_{supply,N} = \text{max} \left( \sum_0^N \left(p_N(t)\right) \right) + +Average Power +^^^^^^^^^^^^^ + +What may be more likely is that you might be operating this integrated +electronic-photonic system with a set of instructions over a long period +of time. A set of example of this would be through encoding +communication channels, or arbitrary unitary operations, sensing a +sample, etc. In this case, there is a power consumption over a period of +time. We can describe this in terms of the average power consumption of +the whole system over a period of time :math:`T`: + +.. math:: + + + P_{average} = \int_0^T p(t) dt + +If we have multiple supplies, as is likely to be the case, then we can +consider it to be: + +.. math:: + + + P_{average} = \sum_0^N \frac{V_{supply,N}}{T} \int_0^T i_{supply,N} (t) dt + +Power Consumption Sources +~~~~~~~~~~~~~~~~~~~~~~~~~ + +In terms of photonic loads +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +We can decompose this in terms of dynamic and static power. When some +transistors are switching, they are consuming dynamic power that they do +not consume when they are in an idle state. This applies similarly to a +photonic load. A resistive photonic load such as a thermo-optic heater +is consuming power in an idle state constantantly whenever any signal is +being applied. A capacitive load such as a electro-optic carrier +depletion phase shifter gets charged and discharged according to the +voltage that is applied and the total power consumption is dependent on +the total switching events. The same could be said for the thermo-optic +phase shifters in terms of a PWM-based modulation and so on. It is just +important to understand the sources of power consumption and heat +dissipation in our circuits in order for us to be able to optimise for +it. + +We know we want to minimise the static power consumption of the circuit +on the idle state, which means that resistive loads such as heaters are +no-gos in terms of VLSI-photonics without a suitable cooling solution. + +In terms of dynamic loads, we know that the more switching events we +have, and more components we have, the higher the total power +consumption. + +Let us evaluate how our circuit operates for these devices. In terms of +a carrier depletion modulator, we can consider the electrical connection +as some resistive wire and the junction load to be a capacitor. We can +describe this from first-principles as a basic RC circuit, with the +following relationship: + +.. math:: V_{out,RC}(t) = (1-e^{-t/\tau}) + +Our time constant :math:`\tau = RC`. And we know that +:math:`50\% V_{out,RC} = 0.69\tau` and :math:`90\% V_{out,RC} = 2.2\tau` +based on Eq. 1.13, page 34 on Rabaey. + +Energy input from signal source to charge a capacitor, independent of +series resistance R, although this determines rise times. + +.. math:: E_{in} = \int_{0}^{\infty} i_{in}(t) v_{in}(t) dt = V \int_{0}^{\infty} C \frac{dV_{out}}{dt} dt = (CV) \int_{0}^{V} dV_{out} = CV^2 + +During charge-up, the energy stored in resistor is: + +.. math:: E_c = \int_{0}^{\infty} i_c (t) V_{out} (t) dt = \int_{0}^{\infty} C \frac{dV_{out}}{dt} dt = C \int_{0}^{V} V_{out} dV_{out} = \frac{CV^2}{2} + +The other half of the energy gets dissipated in the resistor during +rising edge, and the rest of the capacitor energy gets dissipated on the +falling edge. This means that per transition there is about +:math:`E_{load,loss} = \frac{CV^2}{2}` of energy dissipation. This does +not account the energy dissipation per stage, but we need to account for +it for a super low power based design. There is also the +characterisation considerations, and corresponding capacitances. + +Another important relationship of the :math:`RC` time constant is also +in the driving of the device, when, in a switching event, the driving +switch can be considered as a voltage-controlled-capacitor (gate) +modulating-resistor (source-drain). This is important because we can +see, when we drive a switching event, and when we consider our signal +drivers, the effect of their fundamental components on the rest of the +circuit. + +Time Analysis +------------- + +Signal Propagation Definitions +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Our signals will change given that we have control over how we affect +our photonic circuit. Say, we define two boundary conditions of our +signals in a transition between 10% and 90%. We define the time of +change in between these transitions as the rise or fall time depending +on the direction of the change. In digital electronics, section 1.3 of +Rabay, we call this change the propagation delay of our transitions. +Now, this is very important for a range of reasons. + +Mainly this has an effect on the speed of our system, and also on the +power consumption of the system. It has an important effect on how we +design our driving electronics for our photonics loads. + +Rabay describes the importance of this definition very well: + + The rise/fall time of a signal is largely determined by the strength + of the driving gate, and the load presented by the node itself, which + sums the contributions of the connecting gates (fan-out) and the + wiring parasitics. + +We will explore this definition in the context of our drivers and loads +thoroughly. An important relationship worth remembering is that in a +simple RC series circuit, it takes :math:`2.2 \tau = 2.2 RC` to reach +the 90% signal transition point. + +This means that when digitizing the time of an RC signal in terms of +defining the time step of our SPICE simulation, we need to decide the +amount of resolution between the RC metric as a fraction of the RC time +constant. + +We go back to our basics by remembering some relationships in the *The +Art of Electronics* by Paul Horowitz and Winfield Hill. + +Low-Pass RC Filter +^^^^^^^^^^^^^^^^^^ + +TODO ADD IMAGE + +In a low-pass series RC circuit filter common in P/EIC layout, the +following transfer function relationships are also important. This is +the equivalent circuit formed in between a signal routing wire, eg. DC +wire to a heater, and the return path capacitive coupled signal. This +relationship is also significant when deriving transmission line design +parameters, but we will discuss this later. + +This *low-pass* filter passes lower frequencies and blocks higher +frequencies depending on the time constant of the circuit. Note that the +capacitor has a decreasing reactance (the complex impedance component +:math:`X_C`) with an increasing frequency. Unless it is specifically +designed for higher RF frequencies you must take care of what bandwidths +you will operate your circuit. A common scenario of this would simply be +the bandwidth of the wiring of the chip. + +The transfer function of the output voltage node :math:`V_{out,RC}` in +between the :math:`RC` elements in the frequency :math:`\omega` domain: + +.. math:: + + + \frac{V_{out,RC}}{V_{in}} = \frac{X_C}{R + X_C} = \frac{1}{1 + \omega \tau} + +RC Time-Constant Derivation +''''''''''''''''''''''''''' + +The time constant relationship :math:`\tau` is derived from this +relationship. Note that at lower frequencies the capacitors reactance +:math:`X_C` is very high, which means that the output node is like a +voltage divider with a small resistance on top of a very high one. +However, at higher frequencies, this becomes less valid as +:math:`X_C \approx \frac{1}{\omega C}`. This means that there will be a +frequency :math:`\omega_0 = \frac{1}{RC}` + +High-Pass RC Filter +^^^^^^^^^^^^^^^^^^^ + +TODO ADD IMAGE + +In this case, the capacitor is connected directly to the input voltage +:math:`V_{in}` which provides an inverse relationship to the low-pass +filter. The transfer function can be defined as: + +.. math:: + + + \frac{V_{out,RC}}{V_{in}} = \frac{R}{R + X_C} = \frac{\omega \tau}{1 + \omega \tau} + +Depending on your wiring, a common case of this type of filter might +involve driving a capacitive load such as electro-optic modulator in the +frequency domain. Note, it is possible to drive them in DC. + +Driving, Propagation Delay & Fanout +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If we consider each of our modulators, as a load, we must also consider +how we are driving them. diff --git a/docs/sections/components/passives.md b/docs/sections/components/passives.md new file mode 100644 index 00000000..1a7665c9 --- /dev/null +++ b/docs/sections/components/passives.md @@ -0,0 +1,3 @@ +# Passives + +It is important to understand the relationship between electrical models of physical geometrical designs in relation to their photonic operation. diff --git a/docs/sections/environment/setup.rst b/docs/sections/environment/setup.rst index ddbbca11..feef17f6 100644 --- a/docs/sections/environment/setup.rst +++ b/docs/sections/environment/setup.rst @@ -54,6 +54,15 @@ This is a preliminary table, I mostly develop on Linux, you need to verify your In the future, we will have custom installations for different types of users so they can install minimal dependencies for their use case. +Multi-Platform Dependency Installation Commands +----------------------------------------------- + +Maybe in the future I will write a mamba recepie. + +.. code-block:: + mamba install ngspice -y # For NGPICE in any environment + + Docker Configuration -------------------- diff --git a/piel/config.py b/piel/config.py index fc7190a5..28be4e56 100644 --- a/piel/config.py +++ b/piel/config.py @@ -3,6 +3,7 @@ The numerical solver is jax and is imported throughout the module. """ +import os import pathlib import types @@ -10,4 +11,4 @@ "piel_path_types", ] -piel_path_types = str | pathlib.Path | types.ModuleType +piel_path_types = str | pathlib.Path | os.PathLike | types.ModuleType diff --git a/piel/file_system.py b/piel/file_system.py index 7bf0be6d..73281856 100644 --- a/piel/file_system.py +++ b/piel/file_system.py @@ -320,7 +320,10 @@ def return_path(input_path: piel_path_types) -> pathlib.Path: elif isinstance(input_path, pathlib.Path): output_path = input_path elif isinstance(input_path, types.ModuleType): - output_path = pathlib.Path(input_path.__file__).parent + # TODO Untested + output_path = input_path + elif isinstance(input_path, os.PathLike): + output_path = pathlib.Path(input_path) else: raise ValueError( "input_path: " + str(input_path) + " is of type: " + str(type(input_path)) diff --git a/piel/tools/hdl21/__init__.py b/piel/tools/hdl21/__init__.py index 292c2ca2..7255f844 100644 --- a/piel/tools/hdl21/__init__.py +++ b/piel/tools/hdl21/__init__.py @@ -1,2 +1,2 @@ -from .circuit import * +from .simulator import * from .units import * diff --git a/piel/tools/hdl21/simulator.py b/piel/tools/hdl21/simulator.py index bbf57494..5b1d1603 100644 --- a/piel/tools/hdl21/simulator.py +++ b/piel/tools/hdl21/simulator.py @@ -1,75 +1,154 @@ import hdl21 as h -from hdl21.sim import Save, SaveMode, Tran +import hdl21.sim as hs +import numpy as np +import pandas as pd +from typing import Literal, Optional +import vlsirtools.spice as vsp +from ...config import piel_path_types +from ...file_system import return_path + +__all__ = [ + "configure_ngspice_simulation", + "configure_operating_point_simulation", + "configure_transient_simulation", + "run_simulation", +] + + +def configure_ngspice_simulation( + run_directory: piel_path_types = ".", +): + """ + This function configures the NGSPICE simulation for the circuit and returns a simulation class. + + Args: + run_directory (piel_path_types): Directory where the simulation will be run + + Returns: + simulation_options: Configured NGSPICE simulation options + """ + run_directory = return_path(run_directory) + simulation_options = vsp.SimOptions( + simulator=vsp.SupportedSimulators.NGSPICE, + fmt=vsp.ResultFormat.SIM_DATA, + rundir=run_directory, + ) + return simulation_options + + +def configure_operating_point_simulation( + testbench: h.Module, + **kwargs, +): + """ + This function configures the DC operating point simulation for the circuit and returns a simulation class. + + Args: + testbench (Module): HDL21 testbench + **kwargs: Additional arguments to be passed to the operating point simulation such as name. + + Returns: + Simulation: HDL21 simulation class + """ + + @hs.sim + class Simulation: + tb = testbench + operating_point_tb = hs.Op(**kwargs) + + return Simulation def configure_transient_simulation( - circuit: h.Module, + testbench: h.Module, stop_time_s: float, step_time_s: float, + **kwargs, ): """ - This function configures the transient simulation for the circuit. + This function configures the transient simulation for the circuit and returns a simulation class. + + Args: + testbench (Module): HDL21 testbench + stop_time_s (float): Stop time of the simulation in seconds + step_time_s (float): Step time of the simulation in seconds + **kwargs: Additional arguments to be passed to the transient simulation + + Returns: + Simulation: HDL21 simulation class """ - @h.sim + @hs.sim class Simulation: - tb = circuit - transient_tb = Tran(stop_time_s=stop_time_s, step_time_s=step_time_s) - save_all = Save(SaveMode.ALL) + tb = testbench + transient_tb = hs.Tran( + tstop=stop_time_s * h.prefix.UNIT, + tstep=step_time_s * h.prefix.UNIT, + **kwargs, + ) return Simulation -# def configure_ngspice_simulator( -# circuit, -# ) -> Circuit: -# """ -# This function configures the NgSpice simulator to be used for the simulation. -# -# Example usage below: -# -# .. code-block:: -# -# from PySpice.Spice.Netlist import Circuit -# from PySpice.Unit import u_kOhm -# from piel.tools.hdl21.simulator import configure_ngspice_simulator -# + -# circuit = Circuit('Resistor') -# circuit.R(1, 'input', 'output', u_kOhm(10)) -# circuit = configure_ngspice_simulator(circuit) -# -# -# Args: -# circuit (Circuit): PySpice circuit -# -# Returns: -# Circuit: PySpice circuit with NgSpice simulator configured -# """ -# ngspice = NgSpiceShared.new_instance() -# circuit = circuit.simulator( -# temperature=25, -# nominal_temperature=25, -# simulator="ngspice-shared", -# ngspice_shared=ngspice, -# ) -# return circuit -# -# -# def configure_transient_simulation(circuit: Circuit) -> Circuit: -# """ -# This function configures the transient simulation to be used for the simulation. -# -# Example usage below: -# -# .. code-block:: -# -# from PySpice.Spice.Netlist import Circuit -# from PySpice.Unit import u_kOhm -# from piel.tools.hdl21.simulator import configure_transient_simulation -# + -# circuit = Circuit('Resistor') -# circuit.R(1, 'input', 'output', u_kOhm(10)) -# circuit = configure_transient_simulation(circuit) -# """ -# # circuit = circuit.transient(step_time=1 @ u_us, end_time=500 @ u_us) -# return circuit +def save_results_to_csv( + results: hs.SimResult, file_name: str, save_directory: piel_path_types = "." +): + """ + This function converts the simulation results to a pandas dataframe and saves it to a csv file. + + Args: + directory (piel_path_types): Directory where the simulation will be run + """ + + save_directory = return_path(save_directory) + # TODO check that there are more than one analysis + analysis_results = results.an[0].data + if type(next(iter(analysis_results.values()))) not in ( + list, + dict, + tuple, + np.ndarray, + ): + # Check that dict values are scalars + analysis_results = pd.DataFrame(analysis_results, index=[0]) + else: + analysis_results = pd.DataFrame(analysis_results) + + analysis_results.to_csv(save_directory / (file_name + ".csv")) + + +def run_simulation( + simulation: h.sim.Sim, + simulator_name: Literal["ngspice"] = "ngspice", + simulation_options: Optional[vsp.SimOptions] = None, + to_csv: bool = True, +): + """ + This function runs the transient simulation for the circuit and returns the results. + + Args: + simulation (h.sim.Sim): HDL21 simulation class + simulator_name (Literal["ngspice"]): Name of the simulator + simulation_options (Optional[vsp.SimOptions]): Simulation options + to_csv (bool): Whether to save the results to a csv file + + Returns: + results: Simulation results + """ + if simulator_name == "ngspice": + if simulation_options is None: + if not vsp.ngspice.available(): + print( + "NGSPICE is not available. Please install it. Check by running `ngspice` in the terminal." + ) + return + simulation_options = configure_ngspice_simulation() + results = simulation.run(simulation_options) + else: + print("Simulator not supported.") + return + + if to_csv: + save_results_to_csv(results, simulation.tb.name) + + return results