sec.3.tex

\label{sec:3}

ColdADC is highly programmable.  Many circuit blocks can be bypassed and two versions of a number of circuit blocks are included to mitigate the risk that one might fail.  Testing at Fermilab concentrated on verifying the functionality of all of the circuit blocks.  Three design errors were revealed and a number of documentation errors were corrected.  The table below summarizes the tests.
 
 \begin{table}[h]
\centering
\begin{tabular}{|c|c|}
\hline
\textbf{ Test/Circuit} & Result  \\ \hline \hline
Power on &  No shorts \\ \hline
I2C & Works as designed (registers can be written and read) \\ \hline
Reset & Works as designed (registers are set to default values) \\ \hline
UART & Works as designed \\ \hline
LVDS I/O & Works as designed (output amplitude controlled as designed) \\ \hline
Clock Generation & 16 MHz clock verified \\ \hline
Data Formatter & Works as designed \\ \hline
Band Gap Reference & Works $\sim$as designed at room temperature, but fails when cold. \\ 
 & Problem traced to a design error (inclusion of the wrong \\ 
 &  OP-Amp in the current source DAC); works as designed \\ 
 &  with elevated VDDA2P5 (needs 2.7V at 77 K) \\ \hline
 CMOS Reference & Works as designed \\ \hline
 Automatic Calibration & Fails.  Calibration can still be done by using control \\ 
  & registers to force the sequence of steps required \\ 
   & and doing arithmetic off-chip.\\ 
    & Eventually we noticed that when automatic calibration is \\ 
     & attempted, the low order bytes of W0 and W2 for every \\ 
      & ``calibrated'' stage are equal. Simulation verified that  \\ 
       & this is due to a timing error storing W0 and W2. \\ \hline
 ADC Correction Logic & Works as designed (loaded fake comparator output \\ 
  & values; resulting ADC output is as expected). \\ \hline
Pipelined ADC & Linear ramp yields close to linear output; \\ 
 & deviation from linear at extremes of ramp; \\ 
  & no significant deviation from linear when cold. \\ \hline
Input buffers (SDC,DB) & Significant non-linearity observed. \\ 
 & Problem traced to circuit naming confusion that resulted \\ 
 & in level shifters being omitted from input buffers. \\
 & Buffers operate $\sim$as designed with elevated VDDD1P2 \\ \hline
 Sample and Hold and MUX & Require elevated VDDD1P2 because \\ 
 & inputs come through input buffers. \\ \hline
\end{tabular}
\caption{Functional Testing.}
\label{tab:Functionality}
\end{table}