The F/F setup/hold violations are not checked with the correct setup/hold times.

[takanie1967]

I use OSS_CVC_7.00b-x86_64-rhel6x of 07/07/14 (Linux-elf).

When I simulate a delay simulation by CVC in which SDF is annotated,
the F/F setup/hold violations are not checked with the correct setup/hold times.

For example, I write SDF file as follows and I simulate with +maxdelays option:
(HOLD (posedge D) (COND S&R (posedge CLK) ) (0.033:0.044:0.067) )
(HOLD (negedge D) (COND S&R (posedge CLK) ) (0.028:0.038:0.057) )
(* TIMESCALE is 1 ns. *)

At this time, the following timing violation message is output.
$hold((posedge CLK &&& \S&R ):16042 ps, (posedge D):16088 ps, 57 ps)

The hold violation is checked with the hold time of 57ps,
but this hold time(57ps) is for negedge of D. (Now, D behavior is posedge.)

Next, I rewrite the SDF file as follows and simulate with +maxdelays option:
(HOLD (negedge D) (COND S&R (posedge CLK) ) (0.028:0.038:0.057) )
(HOLD (posedge D) (COND S&R (posedge CLK) ) (0.033:0.044:0.067) )

At this time, the following timing violation message is output.
$hold((posedge CLK &&& \S&R ):16042 ps, (posedge D):16088 ps, 67 ps);

This message is correct.

When the SDF file contains the setup/hold times of posedge D and negedge D,
does the CVC check the timing violation based on the setup/hold time written in the line below,
regardless of the behavior (posedge or negedge) of the signal ?