diff --git a/fpga_topwrap/elaboratable_wrapper.py b/fpga_topwrap/elaboratable_wrapper.py
index a882b5cf..8c49aa0e 100644
--- a/fpga_topwrap/elaboratable_wrapper.py
+++ b/fpga_topwrap/elaboratable_wrapper.py
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 from functools import lru_cache
-from typing import Iterable, Mapping, Union
+from typing import Iterable, List, Mapping, Union
 
 from amaranth import *
 from amaranth.build import Platform
@@ -35,7 +35,7 @@ def __init__(self, name: str, elaboratable: Elaboratable) -> None:
             port_width=1, port_flow=wiring.In, name="rst", port_name="rst", iface_name=""
         )
 
-    def get_ports(self) -> list[WrapperPort]:
+    def get_ports(self) -> List[WrapperPort]:
         """Return a list of external ports."""
         return self._flatten_hier(self.get_ports_hier())
 
@@ -136,7 +136,7 @@ def _flatten_hier(self, hier: SignalMapping) -> Iterable[Signal]:
             ports += [hier]
         return ports
 
-    def _connect_ports(self, ports: SignalMapping, iface: InterfaceLike) -> list[Assign]:
+    def _connect_ports(self, ports: SignalMapping, iface: InterfaceLike) -> List[Assign]:
         """Returns a list of amaranth assignments between the wrapped elaboratable and external ports.
 
         :param ports: nested dictionary of WrapperPorts mirroring that of iface's signature
diff --git a/tests/tests_build/test_elaboratable_wrapper.py b/tests/tests_build/test_elaboratable_wrapper.py
index f43873c4..bf3783eb 100644
--- a/tests/tests_build/test_elaboratable_wrapper.py
+++ b/tests/tests_build/test_elaboratable_wrapper.py
@@ -3,7 +3,7 @@
 # Copyright (C) 2023 Antmicro
 # SPDX-License-Identifier: Apache-2.0
 
-from typing import Callable, Union
+from typing import Callable, List, Tuple, Union
 
 import pytest
 from amaranth import *
@@ -115,7 +115,7 @@ def nested_signature_mapping() -> SignalMapping:
 
 
 @pytest.fixture
-def flattened_nested_signature_mapping() -> list[WrapperPort]:
+def flattened_nested_signature_mapping() -> List[WrapperPort]:
     return [
         WrapperPort(
             bounds=[15, 0, 15, 0],
@@ -217,7 +217,7 @@ def clock_domain_signals(elaboratable_wrapper: ElaboratableWrapper) -> SignalMap
 @pytest.fixture
 def interface_connections(
     elaboratable: Elaboratable, nested_signature_mapping: SignalMapping
-) -> list[tuple[Signal, Signal]]:
+) -> List[Tuple[Signal, Signal]]:
     m = elaboratable
     d = nested_signature_mapping
     return [
@@ -269,7 +269,7 @@ def test_flatten_hier(
         self,
         elaboratable_wrapper: ElaboratableWrapper,
         nested_signature_mapping: SignalMapping,
-        flattened_nested_signature_mapping: list[WrapperPort],
+        flattened_nested_signature_mapping: List[WrapperPort],
     ) -> None:
         def ordering(p):
             return p.name
@@ -304,7 +304,7 @@ def test_get_ports_hier(
     def test_get_ports(
         self,
         elaboratable_wrapper: ElaboratableWrapper,
-        flattened_nested_signature_mapping: list[WrapperPort],
+        flattened_nested_signature_mapping: List[WrapperPort],
         clock_domain_signals: SignalMapping,
     ) -> None:
         def ordering(p):
@@ -322,7 +322,7 @@ def test_connect_ports(
         elaboratable_wrapper: ElaboratableWrapper,
         nested_signature_mapping: SignalMapping,
         elaboratable: Elaboratable,
-        interface_connections: list[tuple[Signal, Signal]],
+        interface_connections: List[Tuple[Signal, Signal]],
     ) -> None:
         conns_test = sorted(
             elaboratable_wrapper._connect_ports(nested_signature_mapping, elaboratable),