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il.cpp
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il.cpp
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#include "lowlevelilinstruction.h"
#include <cstring>
#include <inttypes.h>
#include <stdarg.h>
#include "il.h"
#include "neon_intrinsics.h"
#include "sysregs.h"
using namespace BinaryNinja;
#include "il_macros.h"
static uint32_t GetFlagWriteTypeForEffect(FlagEffect e) {
switch (e) {
case FLAGEFFECT_SETS:
case FLAGEFFECT_SETS_NORMAL:
return IL_FLAG_WRITE_ALL;
case FLAGEFFECT_SETS_FLOAT:
return IL_FLAG_WRITE_ALL_FLOAT;
case FLAGEFFECT_NONE:
default:
return 0;
}
}
static ExprId GetCondition(LowLevelILFunction& il, Condition cond)
{
switch (cond)
{
case COND_EQ:
return il.FlagGroup(IL_FLAG_GROUP_EQ);
case COND_NE:
return il.FlagGroup(IL_FLAG_GROUP_NE);
case COND_CS:
return il.FlagGroup(IL_FLAG_GROUP_CS);
case COND_CC:
return il.FlagGroup(IL_FLAG_GROUP_CC);
case COND_MI:
return il.FlagGroup(IL_FLAG_GROUP_MI);
case COND_PL:
return il.FlagGroup(IL_FLAG_GROUP_PL);
case COND_VS:
return il.FlagGroup(IL_FLAG_GROUP_VS);
case COND_VC:
return il.FlagGroup(IL_FLAG_GROUP_VC);
case COND_HI:
return il.FlagGroup(IL_FLAG_GROUP_HI);
case COND_LS:
return il.FlagGroup(IL_FLAG_GROUP_LS);
case COND_GE:
return il.FlagGroup(IL_FLAG_GROUP_GE);
case COND_LT:
return il.FlagGroup(IL_FLAG_GROUP_LT);
case COND_GT:
return il.FlagGroup(IL_FLAG_GROUP_GT);
case COND_LE:
return il.FlagGroup(IL_FLAG_GROUP_LE);
case COND_AL:
return il.Const(0, 1); // Always branch
case COND_NV:
default:
return il.Const(0, 0); // Never branch
}
}
static void GenIfElse(LowLevelILFunction& il, ExprId clause, ExprId trueCase, ExprId falseCase)
{
if (falseCase)
{
LowLevelILLabel trueCode, falseCode, done;
il.AddInstruction(il.If(clause, trueCode, falseCode));
il.MarkLabel(trueCode);
il.AddInstruction(trueCase);
il.AddInstruction(il.Goto(done));
il.MarkLabel(falseCode);
il.AddInstruction(falseCase);
il.AddInstruction(il.Goto(done));
il.MarkLabel(done);
}
else
{
LowLevelILLabel trueCode, done;
il.AddInstruction(il.If(clause, trueCode, done));
il.MarkLabel(trueCode);
il.AddInstruction(trueCase);
il.MarkLabel(done);
}
return;
}
ExprId ExtractImmediate(LowLevelILFunction& il, InstructionOperand& operand, int sizeof_imm)
{
if (operand.operandClass != IMM32 && operand.operandClass != IMM64)
return il.Unimplemented();
uint64_t imm = operand.immediate;
if (operand.shiftValueUsed)
{
switch (operand.shiftType)
{
case ShiftType_LSL:
imm = imm << operand.shiftValue;
break;
case ShiftType_LSR:
imm = imm >> operand.shiftValue;
break;
case ShiftType_MSL:
imm = (imm << operand.shiftValue) | ONES(operand.shiftValue);
break;
case ShiftType_ASR:
case ShiftType_ROR:
case ShiftType_UXTW:
case ShiftType_SXTW:
case ShiftType_SXTX:
case ShiftType_UXTX:
case ShiftType_SXTB:
case ShiftType_SXTH:
case ShiftType_UXTH:
case ShiftType_UXTB:
case ShiftType_END:
default:
return il.Unimplemented();
}
}
return ILCONST(sizeof_imm, imm & ONES(sizeof_imm * 8));
}
// extractSize can be smaller than the register, generating an LLIL_LOWPART
// resultSize can be larger than the register, generating sign or zero extension
ExprId ExtractRegister(LowLevelILFunction& il, InstructionOperand& operand, size_t regNum,
size_t extractSize, bool signExtend, size_t resultSize)
{
size_t opsz = get_register_size(operand.reg[regNum]);
if (IS_ZERO_REG(operand.reg[regNum]))
return il.Const(resultSize, 0);
ExprId res = 0;
switch (operand.operandClass)
{
case SYS_REG:
res = il.Register(opsz, operand.sysreg);
break;
case REG:
default:
res = il.Register(opsz, operand.reg[regNum]);
break;
}
if (extractSize < opsz)
res = il.LowPart(extractSize, res);
if (extractSize < resultSize || opsz < extractSize)
{
if (signExtend)
res = il.SignExtend(resultSize, res);
else
res = il.ZeroExtend(resultSize, res);
}
return res;
}
static ExprId GetFloat(LowLevelILFunction& il, InstructionOperand& operand, int float_sz)
{
if (operand.operandClass == FIMM32)
{
switch (float_sz)
{
case 2:
return il.FloatConstRaw(2, operand.immediate);
case 4:
return il.FloatConstSingle(*(float*)&(operand.immediate));
case 8:
return il.FloatConstDouble(*(float*)&(operand.immediate));
default:
break;
}
}
else if (operand.operandClass == REG)
{
return il.FloatConvert(
float_sz, ExtractRegister(il, operand, 0, REGSZ_O(operand), false, REGSZ_O(operand)));
}
return il.Unimplemented();
}
static ExprId GetShiftedRegister(
LowLevelILFunction& il, InstructionOperand& operand, size_t regNum, size_t resultSize)
{
ExprId res;
// peel off the variants that return early
switch (operand.shiftType)
{
case ShiftType_NONE:
res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize);
return res;
case ShiftType_ASR:
res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize);
if (operand.shiftValue)
res = il.ArithShiftRight(resultSize, res, il.Const(1, operand.shiftValue));
return res;
case ShiftType_LSR:
res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize);
if (operand.shiftValue)
res = il.LogicalShiftRight(resultSize, res, il.Const(1, operand.shiftValue));
return res;
case ShiftType_ROR:
res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize);
if (operand.shiftValue)
res = il.RotateRight(resultSize, res, il.Const(1, operand.shiftValue));
return res;
default:
break;
}
// everything else falls through to maybe be left shifted
switch (operand.shiftType)
{
case ShiftType_LSL:
res = ExtractRegister(il, operand, regNum, REGSZ_O(operand), false, resultSize);
break;
case ShiftType_SXTB:
res = ExtractRegister(il, operand, regNum, 1, true, resultSize);
break;
case ShiftType_SXTH:
res = ExtractRegister(il, operand, regNum, 2, true, resultSize);
break;
case ShiftType_SXTW:
res = ExtractRegister(il, operand, regNum, 4, true, resultSize);
break;
case ShiftType_SXTX:
res = ExtractRegister(il, operand, regNum, 8, true, resultSize);
break;
case ShiftType_UXTB:
res = ExtractRegister(il, operand, regNum, 1, false, resultSize);
break;
case ShiftType_UXTH:
res = ExtractRegister(il, operand, regNum, 2, false, resultSize);
break;
case ShiftType_UXTW:
res = ExtractRegister(il, operand, regNum, 4, false, resultSize);
break;
case ShiftType_UXTX:
res = ExtractRegister(il, operand, regNum, 8, false, resultSize);
break;
default:
il.AddInstruction(il.Unimplemented());
return il.Unimplemented();
}
if (operand.shiftValue)
res = il.ShiftLeft(resultSize, res, il.Const(1, operand.shiftValue));
return res;
}
static ExprId GetILOperandPreOrPostIndex(LowLevelILFunction& il, InstructionOperand& operand)
{
if (operand.operandClass != MEM_PRE_IDX && operand.operandClass != MEM_POST_IDX)
return 0;
if (operand.reg[1] == REG_NONE)
{
// ..., [Xn], #imm
if (IMM_O(operand) == 0)
return 0;
return ILSETREG_O(operand, ILADDREG_O(operand, il.Const(REGSZ_O(operand), IMM_O(operand))));
}
else
{
// ..., [Xn], <Xm>
return ILSETREG_O(operand, ILADDREG_O(operand, il.Register(8, operand.reg[1])));
}
}
/* Returns an expression that does any pre-incrementing on an operand, if it exists */
static ExprId GetILOperandPreIndex(LowLevelILFunction& il, InstructionOperand& operand)
{
if (operand.operandClass != MEM_PRE_IDX)
return 0;
return GetILOperandPreOrPostIndex(il, operand);
}
/* Returns an expression that does any post-incrementing on an operand, if it exists */
static ExprId GetILOperandPostIndex(LowLevelILFunction& il, InstructionOperand& operand)
{
if (operand.operandClass != MEM_POST_IDX)
return 0;
return GetILOperandPreOrPostIndex(il, operand);
}
/* Returns an IL expression that reads (and only reads) from the operand.
It accounts for, but does not generate IL that executes, pre and post indexing.
The operand class can be overridden.
An additional offset can be applied, convenient for calculating sequential loads and stores. */
static ExprId GetILOperandEffectiveAddress(LowLevelILFunction& il, InstructionOperand& operand,
size_t addrSize, OperandClass oclass, size_t extra_offset)
{
ExprId addr = 0;
if (oclass == NONE)
oclass = operand.operandClass;
switch (oclass)
{
case MEM_REG: // ldr x0, [x1]
case MEM_POST_IDX: // ldr w0, [x1], #4
addr = ILREG_O(operand);
if (extra_offset)
addr = il.Add(addrSize, addr, il.Const(addrSize, extra_offset));
break;
case MEM_OFFSET: // ldr w0, [x1, #4]
case MEM_PRE_IDX: // ldr w0, [x1, #4]!
addr = il.Add(addrSize, ILREG_O(operand), il.Const(addrSize, operand.immediate + extra_offset));
break;
case MEM_EXTENDED:
if (operand.shiftType == ShiftType_NONE)
{
addr =
il.Add(addrSize, ILREG_O(operand), il.Const(addrSize, operand.immediate + extra_offset));
}
else if (operand.shiftType == ShiftType_LSL)
{
if (extra_offset)
{
addr = il.Add(addrSize, ILREG_O(operand),
il.Add(addrSize,
il.ShiftLeft(addrSize, il.Const(addrSize, operand.immediate),
il.Const(1, operand.shiftValue)),
il.Const(addrSize, extra_offset)));
}
else
{
addr = il.Add(addrSize, ILREG_O(operand),
il.ShiftLeft(
addrSize, il.Const(addrSize, operand.immediate), il.Const(1, operand.shiftValue)));
}
}
else
{
// printf("ERROR: dunno how to handle MEM_EXTENDED shiftType %d\n", operand.shiftType);
ABORT_LIFT;
}
break;
default:
// printf("ERROR: dunno how to handle operand class %d\n", oclass);
ABORT_LIFT;
}
return addr;
}
static size_t ReadILOperand(LowLevelILFunction& il, InstructionOperand& operand, size_t resultSize)
{
switch (operand.operandClass)
{
case IMM32:
case IMM64:
if (operand.shiftType != ShiftType_NONE && operand.shiftValue)
return il.Const(resultSize, operand.immediate << operand.shiftValue);
else
return il.Const(resultSize, operand.immediate);
case LABEL:
return il.ConstPointer(8, operand.immediate);
case REG:
if (IS_ZERO_REG(operand.reg[0]))
return il.Const(resultSize, 0);
return GetShiftedRegister(il, operand, 0, resultSize);
case MEM_REG:
return il.Load(resultSize, il.Register(8, operand.reg[0]));
case MEM_OFFSET:
if (operand.immediate != 0)
return il.Load(
resultSize, il.Add(8, il.Register(8, operand.reg[0]), il.Const(8, operand.immediate)));
else
return il.Load(resultSize, il.Register(8, operand.reg[0]));
case MEM_EXTENDED:
return il.Load(resultSize, GetILOperandEffectiveAddress(il, operand, resultSize, NONE, 0));
case MEM_PRE_IDX:
case MEM_POST_IDX:
case MULTI_REG:
case FIMM32:
return GetFloat(il, operand, resultSize);
case NONE:
default:
return il.Unimplemented();
}
}
unsigned v_unpack_lookup_sz[15] = {0, 1, 2, 4, 8, 16, 1, 2, 4, 8, 1, 2, 4, 1, 1};
extern "C" Register* v_unpack_lookup[15][32];
Register v_consolidate_lookup[32][15] = {
// NONE .q .2d .4s .8h .16b .d .2s .4h .8b .s .2h .4b .h .b
{REG_V0, REG_V0, REG_V0, REG_V0, REG_V0, REG_V0, REG_V0_D0, REG_V0_D0, REG_V0_D0, REG_V0_D0,
REG_V0_S0, REG_V0_S0, REG_V0_S0, REG_V0_H0, REG_V0_B0},
{REG_V1, REG_V1, REG_V1, REG_V1, REG_V1, REG_V1, REG_V1_D0, REG_V1_D0, REG_V1_D0, REG_V1_D0,
REG_V1_S0, REG_V1_S0, REG_V1_S0, REG_V1_H0, REG_V1_B0},
{REG_V2, REG_V2, REG_V2, REG_V2, REG_V2, REG_V2, REG_V2_D0, REG_V2_D0, REG_V2_D0, REG_V2_D0,
REG_V2_S0, REG_V2_S0, REG_V2_S0, REG_V2_H0, REG_V2_B0},
{REG_V3, REG_V3, REG_V3, REG_V3, REG_V3, REG_V3, REG_V3_D0, REG_V3_D0, REG_V3_D0, REG_V3_D0,
REG_V3_S0, REG_V3_S0, REG_V3_S0, REG_V3_H0, REG_V3_B0},
{REG_V4, REG_V4, REG_V4, REG_V4, REG_V4, REG_V4, REG_V4_D0, REG_V4_D0, REG_V4_D0, REG_V4_D0,
REG_V4_S0, REG_V4_S0, REG_V4_S0, REG_V4_H0, REG_V4_B0},
{REG_V5, REG_V5, REG_V5, REG_V5, REG_V5, REG_V5, REG_V5_D0, REG_V5_D0, REG_V5_D0, REG_V5_D0,
REG_V5_S0, REG_V5_S0, REG_V5_S0, REG_V5_H0, REG_V5_B0},
{REG_V6, REG_V6, REG_V6, REG_V6, REG_V6, REG_V6, REG_V6_D0, REG_V6_D0, REG_V6_D0, REG_V6_D0,
REG_V6_S0, REG_V6_S0, REG_V6_S0, REG_V6_H0, REG_V6_B0},
{REG_V7, REG_V7, REG_V7, REG_V7, REG_V7, REG_V7, REG_V7_D0, REG_V7_D0, REG_V7_D0, REG_V7_D0,
REG_V7_S0, REG_V7_S0, REG_V7_S0, REG_V7_H0, REG_V7_B0},
{REG_V8, REG_V8, REG_V8, REG_V8, REG_V8, REG_V8, REG_V8_D0, REG_V8_D0, REG_V8_D0, REG_V8_D0,
REG_V8_S0, REG_V8_S0, REG_V8_S0, REG_V8_H0, REG_V8_B0},
{REG_V9, REG_V9, REG_V9, REG_V9, REG_V9, REG_V9, REG_V9_D0, REG_V9_D0, REG_V9_D0, REG_V9_D0,
REG_V9_S0, REG_V9_S0, REG_V9_S0, REG_V9_H0, REG_V9_B0},
{REG_V10, REG_V10, REG_V10, REG_V10, REG_V10, REG_V10, REG_V10_D0, REG_V10_D0, REG_V10_D0,
REG_V10_D0, REG_V10_S0, REG_V10_S0, REG_V10_S0, REG_V10_H0, REG_V10_B0},
{REG_V11, REG_V11, REG_V11, REG_V11, REG_V11, REG_V11, REG_V11_D0, REG_V11_D0, REG_V11_D0,
REG_V11_D0, REG_V11_S0, REG_V11_S0, REG_V11_S0, REG_V11_H0, REG_V11_B0},
{REG_V12, REG_V12, REG_V12, REG_V12, REG_V12, REG_V12, REG_V12_D0, REG_V12_D0, REG_V12_D0,
REG_V12_D0, REG_V12_S0, REG_V12_S0, REG_V12_S0, REG_V12_H0, REG_V12_B0},
{REG_V13, REG_V13, REG_V13, REG_V13, REG_V13, REG_V13, REG_V13_D0, REG_V13_D0, REG_V13_D0,
REG_V13_D0, REG_V13_S0, REG_V13_S0, REG_V13_S0, REG_V13_H0, REG_V13_B0},
{REG_V14, REG_V14, REG_V14, REG_V14, REG_V14, REG_V14, REG_V14_D0, REG_V14_D0, REG_V14_D0,
REG_V14_D0, REG_V14_S0, REG_V14_S0, REG_V14_S0, REG_V14_H0, REG_V14_B0},
{REG_V15, REG_V15, REG_V15, REG_V15, REG_V15, REG_V15, REG_V15_D0, REG_V15_D0, REG_V15_D0,
REG_V15_D0, REG_V15_S0, REG_V15_S0, REG_V15_S0, REG_V15_H0, REG_V15_B0},
{REG_V16, REG_V16, REG_V16, REG_V16, REG_V16, REG_V16, REG_V16_D0, REG_V16_D0, REG_V16_D0,
REG_V16_D0, REG_V16_S0, REG_V16_S0, REG_V16_S0, REG_V16_H0, REG_V16_B0},
{REG_V17, REG_V17, REG_V17, REG_V17, REG_V17, REG_V17, REG_V17_D0, REG_V17_D0, REG_V17_D0,
REG_V17_D0, REG_V17_S0, REG_V17_S0, REG_V17_S0, REG_V17_H0, REG_V17_B0},
{REG_V18, REG_V18, REG_V18, REG_V18, REG_V18, REG_V18, REG_V18_D0, REG_V18_D0, REG_V18_D0,
REG_V18_D0, REG_V18_S0, REG_V18_S0, REG_V18_S0, REG_V18_H0, REG_V18_B0},
{REG_V19, REG_V19, REG_V19, REG_V19, REG_V19, REG_V19, REG_V19_D0, REG_V19_D0, REG_V19_D0,
REG_V19_D0, REG_V19_S0, REG_V19_S0, REG_V19_S0, REG_V19_H0, REG_V19_B0},
{REG_V20, REG_V20, REG_V20, REG_V20, REG_V20, REG_V20, REG_V20_D0, REG_V20_D0, REG_V20_D0,
REG_V20_D0, REG_V20_S0, REG_V20_S0, REG_V20_S0, REG_V20_H0, REG_V20_B0},
{REG_V21, REG_V21, REG_V21, REG_V21, REG_V21, REG_V21, REG_V21_D0, REG_V21_D0, REG_V21_D0,
REG_V21_D0, REG_V21_S0, REG_V21_S0, REG_V21_S0, REG_V21_H0, REG_V21_B0},
{REG_V22, REG_V22, REG_V22, REG_V22, REG_V22, REG_V22, REG_V22_D0, REG_V22_D0, REG_V22_D0,
REG_V22_D0, REG_V22_S0, REG_V22_S0, REG_V22_S0, REG_V22_H0, REG_V22_B0},
{REG_V23, REG_V23, REG_V23, REG_V23, REG_V23, REG_V23, REG_V23_D0, REG_V23_D0, REG_V23_D0,
REG_V23_D0, REG_V23_S0, REG_V23_S0, REG_V23_S0, REG_V23_H0, REG_V23_B0},
{REG_V24, REG_V24, REG_V24, REG_V24, REG_V24, REG_V24, REG_V24_D0, REG_V24_D0, REG_V24_D0,
REG_V24_D0, REG_V24_S0, REG_V24_S0, REG_V24_S0, REG_V24_H0, REG_V24_B0},
{REG_V25, REG_V25, REG_V25, REG_V25, REG_V25, REG_V25, REG_V25_D0, REG_V25_D0, REG_V25_D0,
REG_V25_D0, REG_V25_S0, REG_V25_S0, REG_V25_S0, REG_V25_H0, REG_V25_B0},
{REG_V26, REG_V26, REG_V26, REG_V26, REG_V26, REG_V26, REG_V26_D0, REG_V26_D0, REG_V26_D0,
REG_V26_D0, REG_V26_S0, REG_V26_S0, REG_V26_S0, REG_V26_H0, REG_V26_B0},
{REG_V27, REG_V27, REG_V27, REG_V27, REG_V27, REG_V27, REG_V27_D0, REG_V27_D0, REG_V27_D0,
REG_V27_D0, REG_V27_S0, REG_V27_S0, REG_V27_S0, REG_V27_H0, REG_V27_B0},
{REG_V28, REG_V28, REG_V28, REG_V28, REG_V28, REG_V28, REG_V28_D0, REG_V28_D0, REG_V28_D0,
REG_V28_D0, REG_V28_S0, REG_V28_S0, REG_V28_S0, REG_V28_H0, REG_V28_B0},
{REG_V29, REG_V29, REG_V29, REG_V29, REG_V29, REG_V29, REG_V29_D0, REG_V29_D0, REG_V29_D0,
REG_V29_D0, REG_V29_S0, REG_V29_S0, REG_V29_S0, REG_V29_H0, REG_V29_B0},
{REG_V30, REG_V30, REG_V30, REG_V30, REG_V30, REG_V30, REG_V30_D0, REG_V30_D0, REG_V30_D0,
REG_V30_D0, REG_V30_S0, REG_V30_S0, REG_V30_S0, REG_V30_H0, REG_V30_B0},
{REG_V31, REG_V31, REG_V31, REG_V31, REG_V31, REG_V31, REG_V31_D0, REG_V31_D0, REG_V31_D0,
REG_V31_D0, REG_V31_S0, REG_V31_S0, REG_V31_S0, REG_V31_H0, REG_V31_B0},
};
/* v28.d[1] -> REG_V0_D1 */
static Register vector_reg_minimize(InstructionOperand& oper)
{
if (!IS_ASIMD_O(oper))
return REG_NONE;
if (oper.arrSpec == ARRSPEC_NONE)
{
if (oper.laneUsed)
return REG_NONE; // cannot have lane without an arrangement spec
return oper.reg[0];
}
int vidx = oper.reg[0] - REG_V0;
if (vidx < 0 || vidx > 31)
return REG_NONE;
if (oper.laneUsed)
{
switch (oper.arrSpec)
{
case ARRSPEC_FULL:
return oper.reg[0];
case ARRSPEC_1DOUBLE:
case ARRSPEC_2DOUBLES:
if (oper.lane >= 2)
return REG_NONE;
return v_unpack_lookup[ARRSPEC_2DOUBLES][vidx][oper.lane];
case ARRSPEC_1SINGLE:
case ARRSPEC_2SINGLES:
case ARRSPEC_4SINGLES:
if (oper.lane >= 4)
return REG_NONE;
return v_unpack_lookup[ARRSPEC_4SINGLES][vidx][oper.lane];
case ARRSPEC_1HALF:
case ARRSPEC_2HALVES:
case ARRSPEC_4HALVES:
case ARRSPEC_8HALVES:
if (oper.lane >= 8)
return REG_NONE;
return v_unpack_lookup[ARRSPEC_8HALVES][vidx][oper.lane];
case ARRSPEC_1BYTE:
case ARRSPEC_4BYTES:
case ARRSPEC_8BYTES:
case ARRSPEC_16BYTES:
if (oper.lane >= 16)
return REG_NONE;
return v_unpack_lookup[ARRSPEC_16BYTES][vidx][oper.lane];
default:
break;
}
}
else
{
switch (oper.arrSpec)
{
case ARRSPEC_FULL:
case ARRSPEC_2DOUBLES:
case ARRSPEC_4SINGLES:
case ARRSPEC_8HALVES:
case ARRSPEC_16BYTES:
return oper.reg[0];
case ARRSPEC_1DOUBLE:
case ARRSPEC_2SINGLES:
case ARRSPEC_4HALVES:
case ARRSPEC_8BYTES:
return v_unpack_lookup[ARRSPEC_2DOUBLES][vidx][0];
case ARRSPEC_1SINGLE:
case ARRSPEC_2HALVES:
case ARRSPEC_4BYTES:
return v_unpack_lookup[ARRSPEC_4SINGLES][vidx][0];
case ARRSPEC_1HALF:
// case ARRSPEC_2BYTE
return v_unpack_lookup[ARRSPEC_8HALVES][vidx][0];
case ARRSPEC_1BYTE:
return v_unpack_lookup[ARRSPEC_16BYTES][vidx][0];
default:
break;
}
}
return REG_NONE;
}
/* "promote" the spec to full width so lane can select any */
static ArrangementSpec promote_spec(ArrangementSpec spec)
{
switch (spec)
{
case ARRSPEC_1DOUBLE:
return ARRSPEC_2DOUBLES;
case ARRSPEC_1SINGLE:
case ARRSPEC_2SINGLES:
return ARRSPEC_4SINGLES;
case ARRSPEC_1HALF:
case ARRSPEC_2HALVES:
case ARRSPEC_4HALVES:
return ARRSPEC_8HALVES;
case ARRSPEC_1BYTE:
case ARRSPEC_4BYTES:
case ARRSPEC_8BYTES:
return ARRSPEC_16BYTES;
default:
return spec;
}
}
static int unpack_vector(InstructionOperand& oper, Register* result)
{
if (oper.operandClass == REG)
{
/* register without an arrangement specification is just a register
examples: "d18", "d6", "v7" */
if (oper.arrSpec == ARRSPEC_NONE)
{
result[0] = oper.reg[0];
return 1;
}
/* require V register with valid arrangement spec
examples: "v17.2s", "v8.4h", "v21.8b" */
if (oper.reg[0] < REG_V0 || oper.reg[0] > REG_V31)
return 0;
if (oper.arrSpec <= ARRSPEC_NONE || oper.arrSpec > ARRSPEC_1BYTE)
return 0;
/* lookup, copy result */
if (oper.laneUsed)
{
ArrangementSpec spec = promote_spec(oper.arrSpec);
int n_lanes = v_unpack_lookup_sz[spec];
if (oper.lane >= n_lanes)
return 0;
// int n = v_unpack_lookup_sz[spec];
// for (int i = 0; i < n; ++i)
result[0] = v_unpack_lookup[spec][oper.reg[0] - REG_V0][oper.lane];
return 1;
}
int n = v_unpack_lookup_sz[oper.arrSpec];
for (int i = 0; i < n; ++i)
result[i] = v_unpack_lookup[oper.arrSpec][oper.reg[0] - REG_V0][i];
return n;
}
else if (oper.operandClass == MULTI_REG)
{
if (oper.laneUsed)
{
/* multireg with a lane
examples: "ld2 {v17.d, v18.d}[1], [x20]" */
ArrangementSpec spec = promote_spec(oper.arrSpec);
int n = 0;
for (int i = 0; i < 4 && oper.reg[i] != REG_NONE; i++)
{
int n_lanes = v_unpack_lookup_sz[spec];
if (oper.lane >= n_lanes)
return 0;
result[i] = v_unpack_lookup[spec][oper.reg[i] - REG_V0][oper.lane];
n += 1;
}
return n;
}
else
{
/* multireg without a lane
examples: "{v0.8b, v1.8b}", "{v8.2s, v9.2s}" */
if (oper.arrSpec < ARRSPEC_NONE || oper.arrSpec > ARRSPEC_1BYTE)
return 0;
int n = 0;
for (int i = 0; i < 4 && oper.reg[i] != REG_NONE; i++)
{
result[i] = v_consolidate_lookup[oper.reg[i] - REG_V0][oper.arrSpec];
n += 1;
}
return n;
}
}
return 0;
}
/* if we have two operands that have the same arrangement spec, instead of treating them as
distinct sets of registers, see if we can consolidate the set of registers into a single
larger register. This allows us to easily lift things like 'mov v0.16b, v1.16b' as
'mov v0, v1' */
static int consolidate_vector(
InstructionOperand& operand1,
InstructionOperand& operand2,
Register *result)
{
/* make sure both our operand classes are single regs */
if (operand1.operandClass != REG || operand2.operandClass != REG)
return 0;
/* make sure our arrSpec's match. We need this to deal with cases where the arrSpec might
have different sizes, e.g. 'uxtl v2.2d, v8.2s'.*/
if (operand1.arrSpec != operand2.arrSpec)
return 0;
result[0] = v_consolidate_lookup[operand1.reg[0]-REG_V0][operand1.arrSpec];
result[1] = v_consolidate_lookup[operand2.reg[0]-REG_V0][operand2.arrSpec];
return 1;
}
static void LoadStoreOperandPair(LowLevelILFunction& il, bool load, InstructionOperand& operand1,
InstructionOperand& operand2, InstructionOperand& operand3)
{
unsigned sz = REGSZ_O(operand1);
/* do pre-indexing */
ExprId tmp = GetILOperandPreIndex(il, operand3);
if (tmp)
il.AddInstruction(tmp);
/* compute addresses */
OperandClass oclass = (operand3.operandClass == MEM_PRE_IDX) ? MEM_REG : operand3.operandClass;
ExprId addr0 = GetILOperandEffectiveAddress(il, operand3, 8, oclass, 0);
ExprId addr1 = GetILOperandEffectiveAddress(il, operand3, 8, oclass, sz);
/* load/store */
if (load)
{
il.AddInstruction(ILSETREG_O(operand1, il.Load(sz, addr0)));
il.AddInstruction(ILSETREG_O(operand2, il.Load(sz, addr1)));
}
else
{
il.AddInstruction(il.Store(sz, addr0, ILREG_O(operand1)));
il.AddInstruction(il.Store(sz, addr1, ILREG_O(operand2)));
}
/* do post-indexing */
tmp = GetILOperandPostIndex(il, operand3);
if (tmp)
il.AddInstruction(tmp);
}
static void LoadStoreOperandPairSize(LowLevelILFunction& il, bool load, size_t load_size, InstructionOperand& operand1,
InstructionOperand& operand2, InstructionOperand& operand3)
{
/* do pre-indexing */
ExprId tmp = GetILOperandPreIndex(il, operand3);
if (tmp)
il.AddInstruction(tmp);
/* compute addresses */
OperandClass oclass = (operand3.operandClass == MEM_PRE_IDX) ? MEM_REG : operand3.operandClass;
ExprId addr0 = GetILOperandEffectiveAddress(il, operand3, 8, oclass, 0);
ExprId addr1 = GetILOperandEffectiveAddress(il, operand3, 8, oclass, load_size);
/* load/store */
if (load)
{
il.AddInstruction(ILSETREG_O(operand1, il.Load(load_size, addr0)));
il.AddInstruction(ILSETREG_O(operand2, il.Load(load_size, addr1)));
}
else
{
il.AddInstruction(il.Store(load_size, addr0, ILREG_O(operand1)));
il.AddInstruction(il.Store(load_size, addr1, ILREG_O(operand2)));
}
/* do post-indexing */
tmp = GetILOperandPostIndex(il, operand3);
if (tmp)
il.AddInstruction(tmp);
}
static void LoadStoreVector(
LowLevelILFunction& il, bool is_load, InstructionOperand& oper0, InstructionOperand& oper1)
{
/* do pre-indexing */
ExprId tmp = GetILOperandPreIndex(il, oper1);
if (tmp)
il.AddInstruction(tmp);
Register regs[16];
int regs_n = unpack_vector(oper0, regs);
/* if we pre-indexed, base sequential effective addresses off the base register */
OperandClass oclass = (oper1.operandClass == MEM_PRE_IDX) ? MEM_REG : oper1.operandClass;
int offset = 0;
for (int i = 0; i < regs_n; ++i)
{
int rsize = get_register_size(regs[i]);
ExprId eaddr = GetILOperandEffectiveAddress(il, oper1, 8, oclass, offset);
if (is_load)
il.AddInstruction(il.SetRegister(rsize, regs[i], il.Load(rsize, eaddr)));
else
il.AddInstruction(il.Store(rsize, eaddr, il.Register(rsize, regs[i])));
offset += rsize;
}
/* do post-indexing */
tmp = GetILOperandPostIndex(il, oper1);
if (tmp)
il.AddInstruction(tmp);
}
static void LoadStoreOperand(LowLevelILFunction& il, bool load,
InstructionOperand& operand1, /* register that gets read/written */
InstructionOperand& operand2, /* location the read/write occurs */
int load_store_sz)
{
if (!load_store_sz)
load_store_sz = REGSZ_O(operand1);
ExprId tmp;
if (load)
{
switch (operand2.operandClass)
{
case MEM_REG:
// operand1.reg = [operand2.reg]
il.AddInstruction(
ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, ILREG_O(operand2)))));
break;
case MEM_OFFSET:
if (!load_store_sz)
load_store_sz = REGSZ_O(operand1);
// operand1.reg = [operand2.reg + operand2.imm]
if (IMM_O(operand2) == 0)
tmp = ILREG_O(operand2);
else
tmp = ILADDREG_O(operand2, il.Const(REGSZ_O(operand2), IMM_O(operand2)));
il.AddInstruction(ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, tmp))));
break;
case MEM_PRE_IDX:
// operand2.reg += operand2.imm
if (IMM_O(operand2) != 0)
il.AddInstruction(ILSETREG_O(operand2, il.Add(REGSZ_O(operand2), ILREG_O(operand2),
il.Const(REGSZ_O(operand2), IMM_O(operand2)))));
// operand1.reg = [operand2.reg]
il.AddInstruction(
ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, ILREG_O(operand2)))));
break;
case MEM_POST_IDX:
// operand1.reg = [operand2.reg]
il.AddInstruction(
ILSETREG_O(operand1, il.Operand(1, il.Load(load_store_sz, ILREG_O(operand2)))));
// operand2.reg += operand2.imm
if (IMM_O(operand2) != 0)
il.AddInstruction(ILSETREG_O(operand2, il.Add(REGSZ_O(operand2), ILREG_O(operand2),
il.Const(REGSZ_O(operand2), IMM_O(operand2)))));
break;
case MEM_EXTENDED:
il.AddInstruction(ILSETREG_O(operand1,
il.Operand(1, il.Load(load_store_sz,
il.Add(REGSZ_O(operand2), ILREG_O(operand2),
GetShiftedRegister(il, operand2, 1, REGSZ_O(operand2)))))));
break;
case LABEL:
il.AddInstruction(ILSETREG_O(
operand1, il.Operand(1, il.Load(load_store_sz, il.ConstPointer(8, IMM_O(operand2))))));
break;
case IMM32:
case IMM64:
il.AddInstruction(ILSETREG_O(operand1, il.Const(REGSZ_O(operand1), IMM_O(operand2))));
break;
default:
il.AddInstruction(il.Unimplemented());
break;
}
}
else // store
{
switch (operand2.operandClass)
{
case MEM_REG:
il.AddInstruction(
il.Operand(1, il.Store(load_store_sz, ILREG_O(operand2), ILREG_O(operand1))));
break;
case MEM_OFFSET:
//[operand2.reg + operand2.immediate] = operand1.reg
if (IMM_O(operand2) == 0)
tmp = ILREG_O(operand2);
else
tmp = ILADDREG_O(operand2, il.Const(REGSZ_O(operand2), IMM_O(operand2)));
il.AddInstruction(il.Operand(1, il.Store(load_store_sz, tmp, ILREG_O(operand1))));
break;
case MEM_PRE_IDX:
// operand2.reg = operand2.reg + operand2.immediate
if (IMM_O(operand2) != 0)
il.AddInstruction(ILSETREG_O(
operand2, ILADDREG_O(operand2, il.Const(REGSZ_O(operand2), IMM_O(operand2)))));
//[operand2.reg] = operand1.reg
il.AddInstruction(
il.Operand(1, il.Store(load_store_sz, ILREG_O(operand2), ILREG_O(operand1))));
break;
case MEM_POST_IDX:
//[operand2.reg] = operand1.reg
il.AddInstruction(
il.Operand(1, il.Store(load_store_sz, ILREG_O(operand2), ILREG_O(operand1))));
// operand2.reg = operand2.reg + operand2.immediate
if (IMM_O(operand2) != 0)
il.AddInstruction(ILSETREG_O(
operand2, ILADDREG_O(operand2, il.Const(REGSZ_O(operand2), IMM_O(operand2)))));
break;
case MEM_EXTENDED:
il.AddInstruction(il.Operand(
1, il.Store(load_store_sz,
il.Add(REGSZ_O(operand2), il.Register(REGSZ_O(operand2), operand2.reg[0]),
GetShiftedRegister(il, operand2, 1, REGSZ_O(operand2))),
ILREG_O(operand1))));
break;
default:
il.AddInstruction(il.Unimplemented());
break;
}
}
}
static void LoadStoreOperandSize(LowLevelILFunction& il, bool load, bool sign_extend, size_t size,
InstructionOperand& operand1, InstructionOperand& operand2)
{
ExprId tmp;
if (load)
{
switch (operand2.operandClass)
{
case MEM_REG:
// operand1.reg = [operand2.reg]
tmp = il.Operand(1, il.Load(size, ILREG_O(operand2)));
if (sign_extend)
tmp = il.SignExtend(REGSZ_O(operand1), tmp);
else
tmp = il.ZeroExtend(REGSZ_O(operand1), tmp);
il.AddInstruction(ILSETREG_O(operand1, tmp));
break;
case MEM_OFFSET:
// operand1.reg = [operand2.reg + operand2.imm]
if (IMM_O(operand2) == 0)
tmp = ILREG_O(operand2);
else
tmp = ILADDREG_O(operand2, il.Const(REGSZ_O(operand2), IMM_O(operand2)));
tmp = il.Operand(1, il.Load(size, tmp));
if (sign_extend)
tmp = il.SignExtend(REGSZ_O(operand1), tmp);
else
tmp = il.ZeroExtend(REGSZ_O(operand1), tmp);
il.AddInstruction(ILSETREG_O(operand1, tmp));
break;
case MEM_PRE_IDX:
// operand2.reg += operand2.imm
if (IMM_O(operand2) != 0)
il.AddInstruction(ILSETREG_O(operand2, il.Add(REGSZ_O(operand2), ILREG_O(operand2),
il.Const(REGSZ_O(operand2), IMM_O(operand2)))));
// operand1.reg = [operand2.reg]
tmp = il.Operand(1, il.Load(size, ILREG_O(operand2)));
if (sign_extend)
tmp = il.SignExtend(REGSZ_O(operand1), tmp);
else
tmp = il.ZeroExtend(REGSZ_O(operand1), tmp);
il.AddInstruction(ILSETREG_O(operand1, tmp));
break;
case MEM_POST_IDX:
// operand1.reg = [operand2.reg]
tmp = il.Operand(1, il.Load(size, ILREG_O(operand2)));
if (sign_extend)
tmp = il.SignExtend(REGSZ_O(operand1), tmp);
else
tmp = il.ZeroExtend(REGSZ_O(operand1), tmp);
il.AddInstruction(ILSETREG_O(operand1, tmp));
// operand2.reg += operand2.imm
if (IMM_O(operand2) != 0)
il.AddInstruction(ILSETREG_O(operand2, il.Add(REGSZ_O(operand2), ILREG_O(operand2),
il.Const(REGSZ_O(operand2), IMM_O(operand2)))));
break;
case MEM_EXTENDED:
tmp =
il.Operand(1, il.Load(size, il.Add(REGSZ_O(operand2), ILREG_O(operand2),
GetShiftedRegister(il, operand2, 1, REGSZ_O(operand2)))));
if (sign_extend)
tmp = il.SignExtend(REGSZ_O(operand1), tmp);
else
tmp = il.ZeroExtend(REGSZ_O(operand1), tmp);
il.AddInstruction(ILSETREG_O(operand1, tmp));
break;
case LABEL:
il.AddInstruction(ILSETREG_O(
operand1, il.Operand(1, il.Load(size, il.ConstPointer(8, IMM_O(operand2))))));
break;
default:
il.AddInstruction(il.Unimplemented());
break;
}
}
else // store
{
ExprId valToStore = il.Operand(0, ILREG_O(operand1));
if (size < REGSZ_O(operand1))
valToStore = il.LowPart(size, valToStore);
switch (operand2.operandClass)
{
case MEM_REG:
il.AddInstruction(il.Operand(1, il.Store(size, ILREG_O(operand2), valToStore)));
break;
case MEM_OFFSET:
//[operand2.reg + operand2.immediate] = operand1.reg
if (IMM_O(operand2) == 0)
tmp = il.Store(size, ILREG_O(operand2), valToStore);
else
tmp = il.Store(