diff --git a/Applications/relax2/poetry.lock b/Applications/relax2/poetry.lock
index 60e7218a..798e1602 100644
--- a/Applications/relax2/poetry.lock
+++ b/Applications/relax2/poetry.lock
@@ -1,81 +1,362 @@
+# This file is automatically @generated by Poetry 1.4.2 and should not be changed by hand.
+
 [[package]]
 name = "contourpy"
-version = "1.0.7"
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 description = "Python library for calculating contours of 2D quadrilateral grids"
 category = "main"
 optional = false
 python-versions = ">=3.8"
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 [package.extras]
-bokeh = ["bokeh", "chromedriver", "selenium"]
-docs = ["furo", "sphinx-copybutton"]
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 name = "cycler"
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 description = "Composable style cycles"
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 optional = false
 python-versions = ">=3.8"
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 [package.dependencies]
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 importlib-resources = {version = ">=3.2.0", markers = "python_version < \"3.10\""}
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 packaging = ">=20.0"
 pillow = ">=6.2.0"
 pyparsing = ">=2.3.1"
 python-dateutil = ">=2.7"
-setuptools_scm = ">=7"
 
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+fpx = ["olefile"]
+mic = ["olefile"]
 tests = ["check-manifest", "coverage", "defusedxml", "markdown2", "olefile", "packaging", "pyroma", "pytest", "pytest-cov", "pytest-timeout"]
+typing = ["typing-extensions"]
+xmp = ["defusedxml"]
 
 [[package]]
 name = "pyparsing"
-version = "3.0.9"
+version = "3.1.4"
 description = "pyparsing module - Classes and methods to define and execute parsing grammars"
 category = "main"
 optional = false
 python-versions = ">=3.6.8"
+files = [
+    {file = "pyparsing-3.1.4-py3-none-any.whl", hash = "sha256:a6a7ee4235a3f944aa1fa2249307708f893fe5717dc603503c6c7969c070fb7c"},
+    {file = "pyparsing-3.1.4.tar.gz", hash = "sha256:f86ec8d1a83f11977c9a6ea7598e8c27fc5cddfa5b07ea2241edbbde1d7bc032"},
+]
 
 [package.extras]
-diagrams = ["railroad-diagrams", "jinja2"]
+diagrams = ["jinja2", "railroad-diagrams"]
 
 [[package]]
 name = "pyqt5"
-version = "5.15.9"
+version = "5.15.11"
 description = "Python bindings for the Qt cross platform application toolkit"
 category = "main"
 optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
+files = [
+    {file = "PyQt5-5.15.11-cp38-abi3-macosx_11_0_arm64.whl", hash = "sha256:c8b03dd9380bb13c804f0bdb0f4956067f281785b5e12303d529f0462f9afdc2"},
+    {file = "PyQt5-5.15.11-cp38-abi3-macosx_11_0_x86_64.whl", hash = "sha256:6cd75628f6e732b1ffcfe709ab833a0716c0445d7aec8046a48d5843352becb6"},
+    {file = "PyQt5-5.15.11-cp38-abi3-manylinux_2_17_x86_64.whl", hash = "sha256:cd672a6738d1ae33ef7d9efa8e6cb0a1525ecf53ec86da80a9e1b6ec38c8d0f1"},
+    {file = "PyQt5-5.15.11-cp38-abi3-win32.whl", hash = "sha256:76be0322ceda5deecd1708a8d628e698089a1cea80d1a49d242a6d579a40babd"},
+    {file = "PyQt5-5.15.11-cp38-abi3-win_amd64.whl", hash = "sha256:bdde598a3bb95022131a5c9ea62e0a96bd6fb28932cc1619fd7ba211531b7517"},
+    {file = "PyQt5-5.15.11.tar.gz", hash = "sha256:fda45743ebb4a27b4b1a51c6d8ef455c4c1b5d610c90d2934c7802b5c1557c52"},
+]
 
 [package.dependencies]
-PyQt5-Qt5 = ">=5.15.2"
-PyQt5-sip = ">=12.11,<13"
+PyQt5-Qt5 = ">=5.15.2,<5.16.0"
+PyQt5-sip = ">=12.15,<13"
 
 [[package]]
 name = "pyqt5-qt5"
-version = "5.15.2"
+version = "5.15.15"
 description = "The subset of a Qt installation needed by PyQt5."
 category = "main"
 optional = false
 python-versions = "*"
+files = [
+    {file = "PyQt5_Qt5-5.15.15-py3-none-macosx_10_13_x86_64.whl", hash = "sha256:eb74072935958a830887115b1de1ff26341fc2d5881b28129de39612b10a260e"},
+    {file = "PyQt5_Qt5-5.15.15-py3-none-macosx_11_0_arm64.whl", hash = "sha256:f8b174725fbe29c1a22f8acce5798933a65c8a083f1d9833ff212479ec2b3c14"},
+    {file = "PyQt5_Qt5-5.15.15-py3-none-manylinux2014_x86_64.whl", hash = "sha256:611505d04ffb06a5e5bcf98f5ff0e4e15ba7785565ccbe7bd3b2e40642ea3bdd"},
+]
 
 [[package]]
 name = "pyqt5-sip"
-version = "12.11.1"
+version = "12.15.0"
 description = "The sip module support for PyQt5"
 category = "main"
 optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
+files = [
+    {file = "PyQt5_sip-12.15.0-cp310-cp310-macosx_10_9_universal2.whl", hash = "sha256:749f7a3ffd6e3d2d5db65ed92c95cbd14490631595c61f0c0672c9238bfb17de"},
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+    {file = "PyQt5_sip-12.15.0-cp310-cp310-win32.whl", hash = "sha256:83d247cdc43ef224410b14c97413067ea26356dfa39e9ed0fe702a31e25710b0"},
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+    {file = "PyQt5_sip-12.15.0-cp311-cp311-manylinux_2_5_x86_64.manylinux1_x86_64.whl", hash = "sha256:0b718a362f4392430903bbb2a4b9bbff9841a16a52f0cfdd5b5bbd9d11457980"},
+    {file = "PyQt5_sip-12.15.0-cp311-cp311-win32.whl", hash = "sha256:2575f428de584a12009fd29d00c89df16ed101a3b38beba818dfdcbc4a10709c"},
+    {file = "PyQt5_sip-12.15.0-cp311-cp311-win_amd64.whl", hash = "sha256:c85be433fbafcb3d417581c0e1b67c8198d23858166e4f938e971c2262c13cdb"},
+    {file = "PyQt5_sip-12.15.0-cp312-cp312-macosx_10_9_universal2.whl", hash = "sha256:852b75cf208825602480e95ab63314108f872d0da251e9ad3deaaff5a183a6f5"},
+    {file = "PyQt5_sip-12.15.0-cp312-cp312-manylinux_2_5_x86_64.manylinux1_x86_64.whl", hash = "sha256:0cd21c3215e3c47fdd5fa7a2dc3dd1e07a7230b0626e905a7217925068c788b9"},
+    {file = "PyQt5_sip-12.15.0-cp312-cp312-win32.whl", hash = "sha256:b58eeedc9b2a3037b136bf96915196c391a33be470ed1c0723d7163ef0b727a2"},
+    {file = "PyQt5_sip-12.15.0-cp312-cp312-win_amd64.whl", hash = "sha256:24a1d4937332bf0a38dd95bb2ce4d89723df449f6e912b52ef0e107e11fefac1"},
+    {file = "PyQt5_sip-12.15.0-cp38-cp38-macosx_11_0_universal2.whl", hash = "sha256:91b9538458a3a23e033c213bc879ce64f3d0a33d5a49cbd03e1e584efe307a35"},
+    {file = "PyQt5_sip-12.15.0-cp38-cp38-manylinux_2_5_x86_64.manylinux1_x86_64.whl", hash = "sha256:0c1c727ede7fdc464a1fe2e46109ba836509b2d7187a46fdeae443148ce51d1c"},
+    {file = "PyQt5_sip-12.15.0-cp38-cp38-win32.whl", hash = "sha256:dd241de9c569c07bbba62bff1049996e5b52478164f61f430073a87bf6d26d33"},
+    {file = "PyQt5_sip-12.15.0-cp38-cp38-win_amd64.whl", hash = "sha256:f600ae6f03e4bff91153c0dc7ebe52f90bd2b6afda58fd580e6990b3b951adc0"},
+    {file = "PyQt5_sip-12.15.0-cp39-cp39-macosx_10_9_universal2.whl", hash = "sha256:c0c543d604116af26694a8a5ba90f510551ff9124d503ae5ee14bb73a61363a3"},
+    {file = "PyQt5_sip-12.15.0-cp39-cp39-manylinux_2_5_x86_64.manylinux1_x86_64.whl", hash = "sha256:97f2d6e8d9b7b3d3e795d576d7f56e6257f524221f6383b33ded7287763e9f06"},
+    {file = "PyQt5_sip-12.15.0-cp39-cp39-win32.whl", hash = "sha256:ed5221c6241981bd98d39504823efb9cbe36841bf8917288f8fe8fc1d5569a41"},
+    {file = "PyQt5_sip-12.15.0-cp39-cp39-win_amd64.whl", hash = "sha256:7f88c85702dce80ac2e1a162054f688ed394811d6dd03a5574b3fa8111b0a6db"},
+    {file = "PyQt5_sip-12.15.0.tar.gz", hash = "sha256:d23fdfcf363b5cedd9d39f8a9c5710e7d52804f5b08a58e91c638b36eafcb702"},
+]
 
 [[package]]
 name = "python-dateutil"
-version = "2.8.2"
+version = "2.9.0.post0"
 description = "Extensions to the standard Python datetime module"
 category = "main"
 optional = false
 python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,>=2.7"
+files = [
+    {file = "python-dateutil-2.9.0.post0.tar.gz", hash = "sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3"},
+    {file = "python_dateutil-2.9.0.post0-py2.py3-none-any.whl", hash = "sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427"},
+]
 
 [package.dependencies]
 six = ">=1.5"
 
 [[package]]
 name = "pytz"
-version = "2022.7.1"
+version = "2024.2"
 description = "World timezone definitions, modern and historical"
 category = "main"
 optional = false
 python-versions = "*"
+files = [
+    {file = "pytz-2024.2-py2.py3-none-any.whl", hash = "sha256:31c7c1817eb7fae7ca4b8c7ee50c72f93aa2dd863de768e1ef4245d426aa0725"},
+    {file = "pytz-2024.2.tar.gz", hash = "sha256:2aa355083c50a0f93fa581709deac0c9ad65cca8a9e9beac660adcbd493c798a"},
+]
 
 [[package]]
 name = "scipy"
@@ -203,31 +726,37 @@ description = "Fundamental algorithms for scientific computing in Python"
 category = "main"
 optional = false
 python-versions = "<3.12,>=3.8"
+files = [
+    {file = "scipy-1.10.1-cp310-cp310-macosx_10_9_x86_64.whl", hash = "sha256:e7354fd7527a4b0377ce55f286805b34e8c54b91be865bac273f527e1b839019"},
+    {file = "scipy-1.10.1-cp310-cp310-macosx_12_0_arm64.whl", hash = "sha256:4b3f429188c66603a1a5c549fb414e4d3bdc2a24792e061ffbd607d3d75fd84e"},
+    {file = "scipy-1.10.1-cp310-cp310-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:1553b5dcddd64ba9a0d95355e63fe6c3fc303a8fd77c7bc91e77d61363f7433f"},
+    {file = "scipy-1.10.1-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:4c0ff64b06b10e35215abce517252b375e580a6125fd5fdf6421b98efbefb2d2"},
+    {file = "scipy-1.10.1-cp310-cp310-win_amd64.whl", hash = "sha256:fae8a7b898c42dffe3f7361c40d5952b6bf32d10c4569098d276b4c547905ee1"},
+    {file = "scipy-1.10.1-cp311-cp311-macosx_10_9_x86_64.whl", hash = "sha256:0f1564ea217e82c1bbe75ddf7285ba0709ecd503f048cb1236ae9995f64217bd"},
+    {file = "scipy-1.10.1-cp311-cp311-macosx_12_0_arm64.whl", hash = "sha256:d925fa1c81b772882aa55bcc10bf88324dadb66ff85d548c71515f6689c6dac5"},
+    {file = "scipy-1.10.1-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:aaea0a6be54462ec027de54fca511540980d1e9eea68b2d5c1dbfe084797be35"},
+    {file = "scipy-1.10.1-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:15a35c4242ec5f292c3dd364a7c71a61be87a3d4ddcc693372813c0b73c9af1d"},
+    {file = "scipy-1.10.1-cp311-cp311-win_amd64.whl", hash = "sha256:43b8e0bcb877faf0abfb613d51026cd5cc78918e9530e375727bf0625c82788f"},
+    {file = "scipy-1.10.1-cp38-cp38-macosx_10_9_x86_64.whl", hash = "sha256:5678f88c68ea866ed9ebe3a989091088553ba12c6090244fdae3e467b1139c35"},
+    {file = "scipy-1.10.1-cp38-cp38-macosx_12_0_arm64.whl", hash = "sha256:39becb03541f9e58243f4197584286e339029e8908c46f7221abeea4b749fa88"},
+    {file = "scipy-1.10.1-cp38-cp38-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:bce5869c8d68cf383ce240e44c1d9ae7c06078a9396df68ce88a1230f93a30c1"},
+    {file = "scipy-1.10.1-cp38-cp38-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:07c3457ce0b3ad5124f98a86533106b643dd811dd61b548e78cf4c8786652f6f"},
+    {file = "scipy-1.10.1-cp38-cp38-win_amd64.whl", hash = "sha256:049a8bbf0ad95277ffba9b3b7d23e5369cc39e66406d60422c8cfef40ccc8415"},
+    {file = "scipy-1.10.1-cp39-cp39-macosx_10_9_x86_64.whl", hash = "sha256:cd9f1027ff30d90618914a64ca9b1a77a431159df0e2a195d8a9e8a04c78abf9"},
+    {file = "scipy-1.10.1-cp39-cp39-macosx_12_0_arm64.whl", hash = "sha256:79c8e5a6c6ffaf3a2262ef1be1e108a035cf4f05c14df56057b64acc5bebffb6"},
+    {file = "scipy-1.10.1-cp39-cp39-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:51af417a000d2dbe1ec6c372dfe688e041a7084da4fdd350aeb139bd3fb55353"},
+    {file = "scipy-1.10.1-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:1b4735d6c28aad3cdcf52117e0e91d6b39acd4272f3f5cd9907c24ee931ad601"},
+    {file = "scipy-1.10.1-cp39-cp39-win_amd64.whl", hash = "sha256:7ff7f37b1bf4417baca958d254e8e2875d0cc23aaadbe65b3d5b3077b0eb23ea"},
+    {file = "scipy-1.10.1.tar.gz", hash = "sha256:2cf9dfb80a7b4589ba4c40ce7588986d6d5cebc5457cad2c2880f6bc2d42f3a5"},
+]
 
 [package.dependencies]
 numpy = ">=1.19.5,<1.27.0"
 
 [package.extras]
-test = ["pytest", "pytest-cov", "pytest-timeout", "pytest-xdist", "asv", "mpmath", "gmpy2", "threadpoolctl", "scikit-umfpack", "pooch"]
-doc = ["sphinx (!=4.1.0)", "pydata-sphinx-theme (==0.9.0)", "sphinx-design (>=0.2.0)", "matplotlib (>2)", "numpydoc"]
-dev = ["mypy", "typing-extensions", "pycodestyle", "flake8", "rich-click", "click", "doit (>=0.36.0)", "pydevtool"]
-
-[[package]]
-name = "setuptools-scm"
-version = "7.1.0"
-description = "the blessed package to manage your versions by scm tags"
-category = "main"
-optional = false
-python-versions = ">=3.7"
-
-[package.dependencies]
-packaging = ">=20.0"
-tomli = {version = ">=1.0.0", markers = "python_version < \"3.11\""}
-typing-extensions = "*"
-
-[package.extras]
-test = ["pytest (>=6.2)", "virtualenv (>20)"]
-toml = ["setuptools (>=42)"]
+dev = ["click", "doit (>=0.36.0)", "flake8", "mypy", "pycodestyle", "pydevtool", "rich-click", "typing_extensions"]
+doc = ["matplotlib (>2)", "numpydoc", "pydata-sphinx-theme (==0.9.0)", "sphinx (!=4.1.0)", "sphinx-design (>=0.2.0)"]
+test = ["asv", "gmpy2", "mpmath", "pooch", "pytest", "pytest-cov", "pytest-timeout", "pytest-xdist", "scikit-umfpack", "threadpoolctl"]
 
 [[package]]
 name = "six"
@@ -236,63 +765,32 @@ description = "Python 2 and 3 compatibility utilities"
 category = "main"
 optional = false
 python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*"
-
-[[package]]
-name = "tomli"
-version = "2.0.1"
-description = "A lil' TOML parser"
-category = "main"
-optional = false
-python-versions = ">=3.7"
-
-[[package]]
-name = "typing-extensions"
-version = "4.5.0"
-description = "Backported and Experimental Type Hints for Python 3.7+"
-category = "main"
-optional = false
-python-versions = ">=3.7"
+files = [
+    {file = "six-1.16.0-py2.py3-none-any.whl", hash = "sha256:8abb2f1d86890a2dfb989f9a77cfcfd3e47c2a354b01111771326f8aa26e0254"},
+    {file = "six-1.16.0.tar.gz", hash = "sha256:1e61c37477a1626458e36f7b1d82aa5c9b094fa4802892072e49de9c60c4c926"},
+]
 
 [[package]]
 name = "zipp"
-version = "3.15.0"
+version = "3.20.2"
 description = "Backport of pathlib-compatible object wrapper for zip files"
 category = "main"
 optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
+files = [
+    {file = "zipp-3.20.2-py3-none-any.whl", hash = "sha256:a817ac80d6cf4b23bf7f2828b7cabf326f15a001bea8b1f9b49631780ba28350"},
+    {file = "zipp-3.20.2.tar.gz", hash = "sha256:bc9eb26f4506fda01b81bcde0ca78103b6e62f991b381fec825435c836edbc29"},
+]
 
 [package.extras]
-docs = ["sphinx (>=3.5)", "jaraco.packaging (>=9)", "rst.linker (>=1.9)", "furo", "sphinx-lint", "jaraco.tidelift (>=1.4)"]
-testing = ["pytest (>=6)", "pytest-checkdocs (>=2.4)", "flake8 (<5)", "pytest-cov", "pytest-enabler (>=1.3)", "jaraco.itertools", "jaraco.functools", "more-itertools", "big-o", "pytest-black (>=0.3.7)", "pytest-mypy (>=0.9.1)", "pytest-flake8"]
+check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)"]
+cover = ["pytest-cov"]
+doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-lint"]
+enabler = ["pytest-enabler (>=2.2)"]
+test = ["big-O", "importlib-resources", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-ignore-flaky"]
+type = ["pytest-mypy"]
 
 [metadata]
-lock-version = "1.1"
+lock-version = "2.0"
 python-versions = "<3.12,>=3.8"
 content-hash = "d91f94789b834755329a2b187c53a3c0fe903c8a52ab11c39a26eeb7ac0d9478"
-
-[metadata.files]
-contourpy = []
-cycler = []
-fonttools = [
-    {file = "fonttools-4.39.2-py3-none-any.whl", hash = "sha256:85245aa2fd4cf502a643c9a9a2b5a393703e150a6eaacc3e0e84bb448053f061"},
-    {file = "fonttools-4.39.2.zip", hash = "sha256:e2d9f10337c9e3b17f9bce17a60a16a885a7d23b59b7f45ce07ea643e5580439"},
-]
-importlib-resources = []
-kiwisolver = []
-matplotlib = []
-numpy = []
-packaging = []
-pandas = []
-pillow = []
-pyparsing = []
-pyqt5 = []
-pyqt5-qt5 = []
-pyqt5-sip = []
-python-dateutil = []
-pytz = []
-scipy = []
-setuptools-scm = []
-six = []
-tomli = []
-typing-extensions = []
-zipp = []
diff --git a/Applications/relax2/server/cross-build.sh b/Applications/relax2/server/cross-build.sh
old mode 100644
new mode 100755
diff --git a/Applications/relax2/server/relax_server_dev.c b/Applications/relax2/server/relax_server_dev.c
index f1478cca..4352e7a5 100644
--- a/Applications/relax2/server/relax_server_dev.c
+++ b/Applications/relax2/server/relax_server_dev.c
@@ -17076,6 +17076,21 @@ void update_RF_SAR_cal_pulses(volatile uint16_t *tx_size, void *tx_data,  int32_
   memcpy(tx_data, pulse, 2 * size);
 }
 
+typedef __attribute__((packed)) union mixer {
+  uint64_t x;
+  int32_t y[2];
+  float z[2];
+} mixer_t;
+
+// new function to take over the conversion to float, because it would be tough in numpy
+uint64_t cast_int32cplx_float32cplx(uint64_t x)
+{
+  mixer_t X,Y;
+  X.x = x;
+  Y.z[0] = (float)(X.y[0]);
+  Y.z[1] = (float)(X.y[1]);
+  return Y.x;
+}
 
 int main(int argc)
 {
@@ -17446,8 +17461,12 @@ int main(int argc)
           usleep(1000000); // Sleep 1s
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
-			while(*rx_cntr < 10000) usleep(500);
-			for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            while(*rx_cntr < 10000) usleep(500);
+            for(j = 0; j < 5000; ++j) {
+	      
+	      buffer[j] = cast_int32cplx_float32cplx(*rx_data);
+
+	    }
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -17501,7 +17520,8 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j)
+	      buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -17555,7 +17575,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -17611,7 +17631,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -17671,7 +17691,7 @@ int main(int argc)
             // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
             for(i = 0; i < 10; ++i) {
               while(*rx_cntr < 10000) usleep(500);
-              for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+              for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
               send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
             }
             seq_config[0] = 0x00000000;
@@ -17729,7 +17749,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -17775,8 +17795,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -17819,8 +17839,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -17863,8 +17883,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -17908,8 +17928,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -17952,8 +17972,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -17998,8 +18018,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18041,8 +18061,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18092,7 +18112,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 5000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18146,7 +18166,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18202,7 +18222,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18255,7 +18275,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18302,8 +18322,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18347,8 +18367,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18393,8 +18413,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18438,8 +18458,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18485,8 +18505,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18532,8 +18552,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18578,8 +18598,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18635,7 +18655,7 @@ int main(int argc)
             // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
             for(i = 0; i < 10; ++i) {
               while(*rx_cntr < 10000) usleep(500);
-              for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+              for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
               send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
             }
             seq_config[0] = 0x00000000;
@@ -18677,8 +18697,8 @@ int main(int argc)
         //printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
         for(i = 0; i < 10; ++i) {
           while(*rx_cntr < 10000) usleep(500);
-          for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
-          send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
+            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
         }
         seq_config[0] = 0x00000000;
         usleep(500000); // Sleep 0.5s
@@ -18730,7 +18750,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18744,7 +18764,7 @@ int main(int argc)
           usleep(1000000); // Sleep 1s
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18799,7 +18819,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
@@ -18813,7 +18833,7 @@ int main(int argc)
           // printf("Number of RX samples in FIFO: %d\n",*rx_cntr);
           for(i = 0; i < 10; ++i) {
             while(*rx_cntr < 10000) usleep(500);
-            for(j = 0; j < 5000; ++j) buffer[j] = *rx_data;
+            for(j = 0; j < 5000; ++j) buffer[j] = cast_int32cplx_float32cplx(*rx_data);
             send(sock_client, buffer, 5000*8, MSG_NOSIGNAL | (i<9?MSG_MORE:0));
           }
           seq_config[0] = 0x00000000;
diff --git a/HDL/.gitignore b/HDL/.gitignore
index 83d92837..b5d5df77 100644
--- a/HDL/.gitignore
+++ b/HDL/.gitignore
@@ -3,4 +3,5 @@ uImage
 devicetree.dtb
 *~
 tmp/
-vivado*
\ No newline at end of file
+vivado*
+.Xil/
\ No newline at end of file
diff --git a/HDL/Makefile b/HDL/Makefile
index 90548bbf..d236ef61 100644
--- a/HDL/Makefile
+++ b/HDL/Makefile
@@ -15,7 +15,7 @@ CORES_PAVEL = axi_axis_reader_v1_0 axi_axis_writer_v1_0 axi_bram_reader_v1_0 \
         axis_zeroer_v1_0 axis_variable_v1_0 axis_interpolator_v1_0 \
         axi_sts_register_v1_0
 
-CORES = micro_sequencer_v1_0 axi_dac_spi_sequencer_v1_1 axi_dac_daisy_spi_sequencer_v1_0 axis_segmented_bram_reader_v1_0 axi_serial_attenuator_v1_0 axi_four_ltc2656_spi_v1_0 axi_trigger_core_v1_0 axis_red_pitaya_adc_v3_0 axi_config_registers_v1_0
+CORES = micro_sequencer_v1_0 axi_dac_spi_sequencer_v1_1 axi_dac_daisy_spi_sequencer_v1_0 axis_segmented_bram_reader_v1_0 axi_serial_attenuator_v1_0 axi_four_ltc2656_spi_v1_0 axi_trigger_core_v1_0 axis_red_pitaya_adc_v3_0 axi_config_registers_v1_0 axis_red_pitaya_dac_v1_1
 
 VIVADO = vivado -nolog -nojournal -mode batch
 HSI = xsct
@@ -23,7 +23,7 @@ RM = rm -rf
 
 VIVADO_VER = $(shell vivado -version | grep "v20" | sed -r 's/.*v(20[0-9]{2}.[0-9]).*/\1/g')
 
-DTREE_TAG = xlnx_rel_v2022.2
+DTREE_TAG = xlnx_rel_v2024.1
 
 DTREE_DIR = tmp/device-tree-xlnx-$(DTREE_TAG)
 DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/
@@ -34,8 +34,10 @@ DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/
 .PHONY: clean all xpr bit dtbo setup
 
 .ONESHELL:
-all: setup tmp/%.bin tmp/%.dtbo
+all: setup tmp/%.bin
 
+.ONESHELL:
+xsa: setup tmp/%.xsa
 
 .ONESHELL:
 xpr: setup tmp/%.xpr
diff --git a/HDL/README.md b/HDL/README.md
index 833cd580..e4d0595c 100644
--- a/HDL/README.md
+++ b/HDL/README.md
@@ -2,11 +2,11 @@
 
 This directory contains all the HDL code of the ocra project. The code is organized in projects, which can be found in subdirectories of the projects folders.
 
-In order to build the HDL code you need to have Xilinx Vitis 2022.2 full edition. We highly recommend that you use Linux, because the build system and other tooling relies on Linux. We are working on and recommend [Ubuntu 22.04 LTS](https://ubuntu.com/download/desktop).
+In order to build the HDL code you need to have at least Xilinx Vitis 2022.2 full edition. This build has been tested up to Vitis 2024.1. We highly recommend that you use Linux, because the build system and other tooling relies on Linux. We are working on and recommend [Ubuntu 22.04 LTS or Ubuntu 24.04 LTS](https://ubuntu.com/download/desktop).
 
 **Basic working knowledge of Linux and bash is more or less required to follow these instructions.**
 
-In order to install Vitis you will need about 110 GB of free disk space, and you will need to register an account with Xilinx website (remember the password, because the installer will also require the same login credentials that you created on the Xilinx website. It is best to download the [Vitis web installer](https://www.xilinx.com/member/forms/download/xef.html?filename=Xilinx_Unified_2022.2_1014_8888_Lin64.bin).
+In order to install Vitis you will need about 110 GB of free disk space, and you will need to register an account with Xilinx website (remember the password, because the installer will also require the same login credentials that you created on the Xilinx website. It is best to download the [Vitis web installer](https://account.amd.com/en/forms/downloads/xef.html?filename=FPGAs_AdaptiveSoCs_Unified_2024.1_0522_2023_Lin64.bin).
 
 Vivado (the main tool in the Vitis package) is a bit of a beast and requires a reasonably powerful workstation.
 
@@ -15,15 +15,18 @@ All building of the HDL is done by a [GNU Makefile](https://www.gnu.org/software
 This makes it straightforward to build multiple projects etc. from the command line without having to wrestle the Vivado GUI. This entire setup is based on the [red-pitaya-notes](https://github.com/pavel-demin/red-pitaya-notes) by Pavel Demin, and some of his architecture and cores can also be found in this repository.
 
 This repository makes use of Vivado board files, which requires additional configuration of your Vivado/Vitis setup. In order to make everything work the following configuration steps need to be taken:
-1. Add `source /tools/Xilinx/Vitis/2022.2/settings64.sh` to your `.bash_profile`
+1. Add `source /tools/Xilinx/Vitis/2024.1/settings64.sh` to your `.bash_profile`
 1. Define the environment variable OCRA_DIR in your `.bash_profile` to point to the ocra directory
-2. Include the following in your local Vivado config (i.e. $HOME/.Xilinx/Vivado/2022.2/Vivado_init.tcl):
+2. Include the following in your local Vivado config (i.e. $HOME/.Xilinx/Vivado/2024.1/Vivado_init.tcl):
 ```
 # set up the OCRA project
 set ocra_dir $::env(OCRA_DIR)
 source $ocra_dir/HDL/scripts/Vivado_ocra_init.tcl
 ```
 
+You may need to adjust the path of your Vitis installation as appropriate for this to be correct on your installation.
+
+
 To get a quick start, assuming you have Vitis/Vivado configured in your path, you should be able to build the base_pl project for the snickerdoodle_black
 ```
 cd $OCRA_DIR/HDL
@@ -34,5 +37,17 @@ Similarily, you can build the ocra_mri project for the stemlab_125_14 by calling
 ```
 make NAME=ocra_mri BOARD=stemlab_125_14
 ```
+This will build bitfiles that can be used with on a Linux installation on your Zynq so long it supports the fpga_manager. 
+
+Sometimes you might want to only quickly generate the project file for Vivado, which you make by calling:
+```
+make xpr NAME=ocra_mri BOARD=stemlab_125_14
+```
+
+If you want to build a device tree and the associated files to create your own bootloader etc. you need to run:
+```
+make dtbo NAME=ocra_mri BOARD=stemlab_125_14
+```
+Note that this requires the HSI tool xsct and the device tree compiler dtc.
 
 This is pretty easy, isn't it?
\ No newline at end of file
diff --git a/HDL/projects/base_pl/block_design.tcl b/HDL/blockdesign-projects/base_pl/block_design.tcl
similarity index 100%
rename from HDL/projects/base_pl/block_design.tcl
rename to HDL/blockdesign-projects/base_pl/block_design.tcl
diff --git a/HDL/projects/ocra_mri/README.md b/HDL/blockdesign-projects/ocra_mri/README.md
similarity index 100%
rename from HDL/projects/ocra_mri/README.md
rename to HDL/blockdesign-projects/ocra_mri/README.md
diff --git a/HDL/projects/ocra_mri/block_design.tcl b/HDL/blockdesign-projects/ocra_mri/block_design.tcl
similarity index 89%
rename from HDL/projects/ocra_mri/block_design.tcl
rename to HDL/blockdesign-projects/ocra_mri/block_design.tcl
index 75800427..aa406d18 100644
--- a/HDL/projects/ocra_mri/block_design.tcl
+++ b/HDL/blockdesign-projects/ocra_mri/block_design.tcl
@@ -3,6 +3,15 @@ global project_name
 
 set ps_preset boards/${board_name}/ps_${project_name}.xml
 
+# define some variables needed for later
+variable dsp_clk_freq
+
+if {$board_name == "stemlab_122_16"} {
+    set dsp_clk_freq 122.88
+} else {
+    set dsp_clk_freq 125.0
+}
+
 # Create processing_system7
 cell xilinx.com:ip:processing_system7:5.5 ps_0 {
   PCW_IMPORT_BOARD_PRESET $ps_preset
@@ -20,11 +29,14 @@ apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
 # Create proc_sys_reset
 cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
 
+puts "OCRA: DSP_CLK_FREQ:"
+puts $dsp_clk_freq
+
 # Create clk_wiz
 cell xilinx.com:ip:clk_wiz:6.0 pll_0 {
   PRIMITIVE PLL
   PRIM_IN_FREQ.VALUE_SRC USER
-  PRIM_IN_FREQ 125.0
+  PRIM_IN_FREQ $dsp_clk_freq
   PRIM_SOURCE Differential_clock_capable_pin
   CLKOUT1_USED true
   CLKOUT1_REQUESTED_OUT_FREQ 125.0
@@ -36,33 +48,12 @@ cell xilinx.com:ip:clk_wiz:6.0 pll_0 {
   clk_in1_p adc_clk_p_i
   clk_in1_n adc_clk_n_i
 }
+
 cell open-mri:user:axi_config_registers:1.0 cfg8 {
     AXI_ADDR_WIDTH 5
     AXI_DATA_WIDTH 32
 }
 
-# Create slice with the TX configuration, which uses the bottom 32 bits
-cell xilinx.com:ip:xlslice:1.0 txinterpolator_slice_0 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_0
-}
-
-# Create slice with the RX configuration and NCO configuration
-# RX seems to use the bottom 16 bit of the upper 32 bit
-# NCO uses the bottom 32 bit
-cell xilinx.com:ip:xlslice:1.0 nco_slice_0 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_1
-}
-
-cell xilinx.com:ip:xlslice:1.0 rx_slice_0 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_2
-}
-
 # ADC switch slice
 cell xilinx.com:ip:xlslice:1.0 cfg_adc_switch {
   DIN_WIDTH 32 DIN_FROM 1 DIN_TO 0 DOUT_WIDTH 2
@@ -81,12 +72,6 @@ cell xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 {
 set_property CONFIG.CDC_TYPE {xpm_cdc_array_single} [get_bd_cells xpm_cdc_gen_0]
 set_property CONFIG.WIDTH {2} [get_bd_cells xpm_cdc_gen_0]
 
-# Create another slice with data for the TX, which is another 32 bit
-cell xilinx.com:ip:xlslice:1.0 cfg_slice_1 {
-  DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
-} {
-  Din cfg8/config_3
-}
 # ADC
 
 # Create axis_red_pitaya_adc
@@ -99,7 +84,7 @@ cell open-mri:user:axis_red_pitaya_adc:3.0 adc_0 {} {
 }
 
 # Create axis_red_pitaya_dac
-cell pavel-demin:user:axis_red_pitaya_dac:1.0 dac_0 {} {
+cell open-mri:user:axis_red_pitaya_dac:1.1 dac_0 {} {
   aclk pll_0/clk_out1
   ddr_clk pll_0/clk_out2
   locked pll_0/locked
@@ -110,36 +95,35 @@ cell pavel-demin:user:axis_red_pitaya_dac:1.0 dac_0 {} {
   dac_dat dac_dat_o
 }
 
-
 # Create xlconstant
 cell xilinx.com:ip:xlconstant:1.1 const_0
 
 # Removed this connection from rx:
 # slice_0/Din rst_slice_0/Dout
 module rx_0 {
-  source projects/ocra_mri/rx2.tcl
+  source blockdesign-projects/ocra_mri/rx2.tcl
 } {
-  rate_slice/Din rx_slice_0/Dout
+  rate_slice/Din cfg8/config_2
   fifo_0/S_AXIS adc_0/M_AXIS
   fifo_0/s_axis_aclk pll_0/clk_out1
   fifo_0/s_axis_aresetn const_0/dout
 }
 
-#  axis_interpolator_0/cfg_data txinterpolator_slice_0/Dout  
+#  axis_interpolator_0/cfg_data cfg8/config_0  
 module tx_0 {
-  source projects/ocra_mri/tx6.tcl
+  source blockdesign-projects/ocra_mri/tx6.tcl
 } {
-  slice_1/Din cfg_slice_1/Dout
-  axis_interpolator_0/cfg_data txinterpolator_slice_0/Dout
+  slice_1/Din cfg8/config_3
+  axis_interpolator_0/cfg_data cfg8/config_0
   fifo_1/M_AXIS dac_0/S_AXIS
   fifo_1/m_axis_aclk pll_0/clk_out1
   fifo_1/m_axis_aresetn const_0/dout
 }
 
 module nco_0 {
-    source projects/ocra_mri/nco.tcl
+    source blockdesign-projects/ocra_mri/nco.tcl
 } {
-  slice_1/Din nco_slice_0/Dout
+  slice_1/Din cfg8/config_1
   bcast_nco/M00_AXIS rx_0/mult_0/S_AXIS_B
   bcast_nco/M01_AXIS tx_0/mult_0/S_AXIS_B
 }
@@ -362,7 +346,7 @@ set_property RANGE 8K [get_bd_addr_segs ps_0/Data/SEG_gradient_writerz2_reg0]
 set_property OFFSET 0x40008000 [get_bd_addr_segs ps_0/Data/SEG_gradient_writerz2_reg0]
 
 module gradient_dac_0 {
-    source projects/ocra_mri/gradient_dacs.tcl
+    source blockdesign-projects/ocra_mri/gradient_dacs.tcl
 } {
     spi_sequencer_0/BRAM_PORTX gradient_memoryx/BRAM_PORTB
     spi_sequencer_0/BRAM_PORTY gradient_memoryy/BRAM_PORTB
@@ -415,16 +399,6 @@ set_property -dict [list CONFIG.Register_PortB_Output_of_Memory_Primitives {true
 #
 # try to connect the bottom 8 bits of the pulse output of the sequencer to the positive gpoi
 #
-# Delete input/output port
-delete_bd_objs [get_bd_ports exp_p_tri_io]
-delete_bd_objs [get_bd_ports exp_n_tri_io]
-
-# Create newoutput port
-create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
-#connect_bd_net [get_bd_pins exp_p_tri_io] [get_bd_pins trigger_slice_0/Dout]
-
-# Create output port for the SPI stuff
-create_bd_port -dir O -from 7 -to 0 exp_n_tri_io
 
 # 09/2019: For the new board we are doing this differently. The SPI bus will use seven pins on the n side of the header
 #          and the txgate will use the eight' pin on the n side
diff --git a/HDL/projects/ocra_mri/client/COPYING b/HDL/blockdesign-projects/ocra_mri/client/COPYING
similarity index 100%
rename from HDL/projects/ocra_mri/client/COPYING
rename to HDL/blockdesign-projects/ocra_mri/client/COPYING
diff --git a/HDL/projects/ocra_mri/client/pulsed_nmr.py b/HDL/blockdesign-projects/ocra_mri/client/pulsed_nmr.py
similarity index 100%
rename from HDL/projects/ocra_mri/client/pulsed_nmr.py
rename to HDL/blockdesign-projects/ocra_mri/client/pulsed_nmr.py
diff --git a/HDL/projects/ocra_mri/client/pulsed_nmr.ui b/HDL/blockdesign-projects/ocra_mri/client/pulsed_nmr.ui
similarity index 100%
rename from HDL/projects/ocra_mri/client/pulsed_nmr.ui
rename to HDL/blockdesign-projects/ocra_mri/client/pulsed_nmr.ui
diff --git a/HDL/projects/ocra_mri/filters/fir_0.r b/HDL/blockdesign-projects/ocra_mri/filters/fir_0.r
similarity index 100%
rename from HDL/projects/ocra_mri/filters/fir_0.r
rename to HDL/blockdesign-projects/ocra_mri/filters/fir_0.r
diff --git a/HDL/projects/ocra_mri/gradient_dacs.tcl b/HDL/blockdesign-projects/ocra_mri/gradient_dacs.tcl
similarity index 100%
rename from HDL/projects/ocra_mri/gradient_dacs.tcl
rename to HDL/blockdesign-projects/ocra_mri/gradient_dacs.tcl
diff --git a/HDL/projects/ocra_mri/gradient_dacs_daisy.tcl b/HDL/blockdesign-projects/ocra_mri/gradient_dacs_daisy.tcl
similarity index 100%
rename from HDL/projects/ocra_mri/gradient_dacs_daisy.tcl
rename to HDL/blockdesign-projects/ocra_mri/gradient_dacs_daisy.tcl
diff --git a/HDL/projects/ocra_mri/nco.tcl b/HDL/blockdesign-projects/ocra_mri/nco.tcl
similarity index 95%
rename from HDL/projects/ocra_mri/nco.tcl
rename to HDL/blockdesign-projects/ocra_mri/nco.tcl
index 945d012e..9c3315fe 100644
--- a/HDL/projects/ocra_mri/nco.tcl
+++ b/HDL/blockdesign-projects/ocra_mri/nco.tcl
@@ -3,6 +3,8 @@
 # 2017 by Thomas Witzel
 # block design for the NCO 
 
+global dsp_clk_freq
+
 # Create xlslice
 cell xilinx.com:ip:xlslice:1.0 slice_1 {
   DIN_WIDTH 32 DIN_FROM 31 DIN_TO 0 DOUT_WIDTH 32
@@ -18,7 +20,7 @@ cell pavel-demin:user:axis_constant:1.0 phase_nco {
 
 # Create dds_compiler
 cell xilinx.com:ip:dds_compiler:6.0 dds_nco {
-  DDS_CLOCK_RATE 125
+  DDS_CLOCK_RATE $dsp_clk_freq
   SPURIOUS_FREE_DYNAMIC_RANGE 138
   FREQUENCY_RESOLUTION 0.2
   PHASE_INCREMENT Streaming
diff --git a/HDL/projects/ocra_mri/rx2.tcl b/HDL/blockdesign-projects/ocra_mri/rx2.tcl
similarity index 91%
rename from HDL/projects/ocra_mri/rx2.tcl
rename to HDL/blockdesign-projects/ocra_mri/rx2.tcl
index 67192183..f9b5faa0 100644
--- a/HDL/projects/ocra_mri/rx2.tcl
+++ b/HDL/blockdesign-projects/ocra_mri/rx2.tcl
@@ -1,3 +1,5 @@
+global dsp_clk_freq
+
 # Create xlslice
 # Trigger slice on Bit 1 (RX pulse)
 cell xilinx.com:ip:xlslice:1.0 slice_0 {
@@ -27,7 +29,7 @@ cell pavel-demin:user:axis_lfsr:1.0 lfsr_0 {} {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create cmpy
+# The top 24 bits is the most we need, 16 would probably be fine as well
 cell xilinx.com:ip:cmpy:6.0 mult_0 {
   FLOWCONTROL Blocking
   APORTWIDTH.VALUE_SRC USER
@@ -35,7 +37,7 @@ cell xilinx.com:ip:cmpy:6.0 mult_0 {
   APORTWIDTH 16
   BPORTWIDTH 24
   ROUNDMODE Random_Rounding
-  OUTPUTWIDTH 26
+  OUTPUTWIDTH 24
 } {
   S_AXIS_A fifo_0/M_AXIS
   S_AXIS_CTRL lfsr_0/M_AXIS
@@ -46,10 +48,10 @@ cell xilinx.com:ip:cmpy:6.0 mult_0 {
 cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
   S_TDATA_NUM_BYTES.VALUE_SRC USER
   M_TDATA_NUM_BYTES.VALUE_SRC USER
-  S_TDATA_NUM_BYTES 8
+  S_TDATA_NUM_BYTES 6
   M_TDATA_NUM_BYTES 3
   M00_TDATA_REMAP {tdata[23:0]}
-  M01_TDATA_REMAP {tdata[55:32]}
+  M01_TDATA_REMAP {tdata[47:24]}
 } {
   S_AXIS mult_0/M_AXIS_DOUT
   aclk /ps_0/FCLK_CLK0
@@ -83,7 +85,7 @@ cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
   MINIMUM_RATE 25
   MAXIMUM_RATE 8192
   FIXED_OR_INITIAL_RATE 625
-  INPUT_SAMPLE_FREQUENCY 125
+  INPUT_SAMPLE_FREQUENCY $dsp_clk_freq
   CLOCK_FREQUENCY 125
   INPUT_DATA_WIDTH 24
   QUANTIZATION Truncation
@@ -107,7 +109,7 @@ cell xilinx.com:ip:cic_compiler:4.0 cic_1 {
   MINIMUM_RATE 25
   MAXIMUM_RATE 8192
   FIXED_OR_INITIAL_RATE 625
-  INPUT_SAMPLE_FREQUENCY 125
+  INPUT_SAMPLE_FREQUENCY $dsp_clk_freq
   CLOCK_FREQUENCY 125
   INPUT_DATA_WIDTH 24
   QUANTIZATION Truncation
@@ -159,7 +161,7 @@ cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
   SAMPLE_FREQUENCY 5.0
   CLOCK_FREQUENCY 125
   OUTPUT_ROUNDING_MODE Convergent_Rounding_to_Even
-  OUTPUT_WIDTH 26
+  OUTPUT_WIDTH 32
   M_DATA_HAS_TREADY true
   HAS_ARESETN true
 } {
@@ -168,43 +170,13 @@ cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
   aresetn /rst_0/peripheral_aresetn
 }
 
-# Create axis_subset_converter
-cell xilinx.com:ip:axis_subset_converter:1.1 subset_0 {
-  S_TDATA_NUM_BYTES.VALUE_SRC USER
-  M_TDATA_NUM_BYTES.VALUE_SRC USER
-  S_TDATA_NUM_BYTES 4
-  M_TDATA_NUM_BYTES 3
-  TDATA_REMAP {tdata[23:0]}
-} {
-  S_AXIS fir_0/M_AXIS_DATA
-  aclk /ps_0/FCLK_CLK0
-  aresetn /rst_0/peripheral_aresetn
-}
-
-# Create floating_point
-cell xilinx.com:ip:floating_point:7.1 fp_0 {
-  OPERATION_TYPE Fixed_to_float
-  A_PRECISION_TYPE.VALUE_SRC USER
-  C_A_EXPONENT_WIDTH.VALUE_SRC USER
-  C_A_FRACTION_WIDTH.VALUE_SRC USER
-  A_PRECISION_TYPE Custom
-  C_A_EXPONENT_WIDTH 2
-  C_A_FRACTION_WIDTH 22
-  RESULT_PRECISION_TYPE Single
-  HAS_ARESETN true
-} {
-  S_AXIS_A subset_0/M_AXIS
-  aclk /ps_0/FCLK_CLK0
-  aresetn /rst_0/peripheral_aresetn
-}
-
-# Create axis_dwidth_converter
+# Convert the 64 bit wide complex word into sequential 32 bit words of real and imag
 cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_1 {
   S_TDATA_NUM_BYTES.VALUE_SRC USER
   S_TDATA_NUM_BYTES 4
   M_TDATA_NUM_BYTES 8
 } {
-  S_AXIS fp_0/M_AXIS_RESULT
+  S_AXIS fir_0/M_AXIS_DATA
   aclk /ps_0/FCLK_CLK0
   aresetn /rst_0/peripheral_aresetn
 }
diff --git a/HDL/projects/ocra_mri/server-c++/pulsed_nmr_server.cpp b/HDL/blockdesign-projects/ocra_mri/server-c++/pulsed_nmr_server.cpp
similarity index 100%
rename from HDL/projects/ocra_mri/server-c++/pulsed_nmr_server.cpp
rename to HDL/blockdesign-projects/ocra_mri/server-c++/pulsed_nmr_server.cpp
diff --git a/HDL/projects/ocra_mri/server/pulsed_nmr_old_backend.c b/HDL/blockdesign-projects/ocra_mri/server/pulsed_nmr_old_backend.c
similarity index 100%
rename from HDL/projects/ocra_mri/server/pulsed_nmr_old_backend.c
rename to HDL/blockdesign-projects/ocra_mri/server/pulsed_nmr_old_backend.c
diff --git a/HDL/projects/ocra_mri/tx6.tcl b/HDL/blockdesign-projects/ocra_mri/tx6.tcl
similarity index 58%
rename from HDL/projects/ocra_mri/tx6.tcl
rename to HDL/blockdesign-projects/ocra_mri/tx6.tcl
index 787d8ce3..b5a3b028 100644
--- a/HDL/projects/ocra_mri/tx6.tcl
+++ b/HDL/blockdesign-projects/ocra_mri/tx6.tcl
@@ -76,13 +76,15 @@ cell pavel-demin:user:axis_interpolator:1.0 axis_interpolator_0 {
 # ROUNDMODE Random_Rounding
 # No control connection needed
 # S_AXIS_CTRL lfsr_0/M_AXIS
+
+# take the top 16 bit of the product. This means TX pulses should be scaled full range of a signed short in the data to the FPGA
 cell xilinx.com:ip:cmpy:6.0 mult_0 {
   FLOWCONTROL Blocking
   APORTWIDTH.VALUE_SRC USER
   BPORTWIDTH.VALUE_SRC USER
   APORTWIDTH 16
   BPORTWIDTH 24
-  OUTPUTWIDTH 41
+  OUTPUTWIDTH 16
 } {
   S_AXIS_A axis_interpolator_0/M_AXIS
   aclk /ps_0/FCLK_CLK0
@@ -91,43 +93,17 @@ cell xilinx.com:ip:cmpy:6.0 mult_0 {
 # extract the real component of the product using a broadcaster in to I and Q
 # a simpler alternative would be to use a axis_subset_converter
 cell xilinx.com:ip:axis_subset_converter:1.1 real_0 {
-    S_TDATA_NUM_BYTES.VALUE_SRC USER
-    M_TDATA_NUM_BYTES.VALUE_SRC USER
-    S_TDATA_NUM_BYTES 10
-    M_TDATA_NUM_BYTES 2
-    TDATA_REMAP {tdata[40:25]}
-} {
-    S_AXIS mult_0/M_AXIS_DOUT
-    aclk /ps_0/FCLK_CLK0
-    aresetn /rst_0/peripheral_aresetn
-}
-
-# extract the real component of the product using a broadcaster in to I and Q
-# a simpler alternative would be to use a axis_subset_converter
-cell xilinx.com:ip:axis_subset_converter:1.1 quotient_0 {
     S_TDATA_NUM_BYTES.VALUE_SRC USER
     M_TDATA_NUM_BYTES.VALUE_SRC USER
     S_TDATA_NUM_BYTES 4
     M_TDATA_NUM_BYTES 2
-    TDATA_REMAP {tdata[31:16]}
+    TDATA_REMAP {tdata[15:0]}
 } {
+    S_AXIS mult_0/M_AXIS_DOUT
     aclk /ps_0/FCLK_CLK0
     aresetn /rst_0/peripheral_aresetn
 }
 
-#cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
-#  S_TDATA_NUM_BYTES.VALUE_SRC USER
-#  M_TDATA_NUM_BYTES.VALUE_SRC USER
-#  S_TDATA_NUM_BYTES 8
-#  M_TDATA_NUM_BYTES 3
-#  M00_TDATA_REMAP {tdata[23:0]}
-#  M01_TDATA_REMAP {tdata[55:32]}
-#} {
-#  S_AXIS mult_0/M_AXIS_DOUT
-#  aclk /ps_0/FCLK_CLK0
-#  aresetn /rst_0/peripheral_aresetn
-#}
-
 # Create axis_clock_converter
 cell xilinx.com:ip:axis_clock_converter:1.1 fifo_1 {
   TDATA_NUM_BYTES.VALUE_SRC USER
@@ -138,18 +114,3 @@ cell xilinx.com:ip:axis_clock_converter:1.1 fifo_1 {
   s_axis_aresetn /rst_0/peripheral_aresetn
 }
 
-## DO all this below to insert the divider by 4
-create_bd_cell -type ip -vlnv xilinx.com:ip:div_gen:5.1 div_gen_0
-create_bd_cell -type ip -vlnv pavel-demin:user:axis_constant:1.0 axis_constant_0
-set_property -dict [list CONFIG.AXIS_TDATA_WIDTH {16}] [get_bd_cells axis_constant_0]
-connect_bd_intf_net [get_bd_intf_pins axis_constant_0/M_AXIS] [get_bd_intf_pins div_gen_0/S_AXIS_DIVISOR]
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0
-# Constant was 4, now its 1
-set_property -dict [list CONFIG.CONST_WIDTH {16} CONFIG.CONST_VAL {1}] [get_bd_cells xlconstant_0]
-connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins axis_constant_0/cfg_data]
-connect_bd_net [get_bd_pins aclk] [get_bd_pins axis_constant_0/aclk]
-connect_bd_net [get_bd_pins aclk] [get_bd_pins div_gen_0/aclk]
-delete_bd_objs [get_bd_intf_nets real_0_M_AXIS]
-connect_bd_intf_net [get_bd_intf_pins real_0/M_AXIS] [get_bd_intf_pins div_gen_0/S_AXIS_DIVIDEND]
-connect_bd_intf_net [get_bd_intf_pins div_gen_0/M_AXIS_DOUT] [get_bd_intf_pins quotient_0/S_AXIS]
-connect_bd_intf_net [get_bd_intf_pins quotient_0/M_AXIS] [get_bd_intf_pins fifo_1/S_AXIS]
diff --git a/HDL/projects/shim_controller/block_design.tcl b/HDL/blockdesign-projects/shim_controller/block_design.tcl
similarity index 100%
rename from HDL/projects/shim_controller/block_design.tcl
rename to HDL/blockdesign-projects/shim_controller/block_design.tcl
diff --git a/HDL/projects/shim_controller/shim_dacs.tcl b/HDL/blockdesign-projects/shim_controller/shim_dacs.tcl
similarity index 100%
rename from HDL/projects/shim_controller/shim_dacs.tcl
rename to HDL/blockdesign-projects/shim_controller/shim_dacs.tcl
diff --git a/HDL/boards/eclypse_z7/brd/A.0/board.xml b/HDL/boards/eclypse_z7/brd/A.0/board.xml
new file mode 100644
index 00000000..f5148031
--- /dev/null
+++ b/HDL/boards/eclypse_z7/brd/A.0/board.xml
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://www.digilentinc.com" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">A.0</revision>
+</compatible_board_revisions>
+<file_version>1.0</file_version>
+<description>Eclypse Z7</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com">
+		<interfaces> 
+			<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+				<port_maps>
+					<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+						<pin_maps>
+							<pin_map port_index="0" component_pin="sys_clk"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+				<parameters>
+					<parameter name="frequency" value="125000000"/>
+				</parameters>
+			</interface>
+			<interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+				<description>Buttons</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
+				<description>8 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/> 
+							<pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/> 
+							<pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+		<description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
+	</component>
+	<component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>Buttons 1 to 0</description>
+	</component>
+	<component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+		<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+	</component>
+	<component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JA</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+		<connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+	</connection>
+	<connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+		<connection_map name="part0_btn_2bits_map"    c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+	<connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
+		<connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+	</connection>
+	<connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
+		<connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
\ No newline at end of file
diff --git a/HDL/boards/eclypse_z7/brd/A.0/part0_pins.xml b/HDL/boards/eclypse_z7/brd/A.0/part0_pins.xml
new file mode 100644
index 00000000..b2155f3e
--- /dev/null
+++ b/HDL/boards/eclypse_z7/brd/A.0/part0_pins.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg484-1">
+<pins>
+    <pin index="0"  name="sys_clk"              iostandard="LVCMOS33" loc="D18"/> <!-- Sch=sysclk    -->
+    
+	<pin index="1"  name="btn_2bits_tri_i_0"    iostandard="LVCMOS33" loc="C17"/> <!-- Sch=btn[0]    -->
+    <pin index="2"  name="btn_2bits_tri_i_1"    iostandard="LVCMOS33" loc="C18"/> <!-- Sch=btn[1]    -->
+    
+	<pin index="3"  name="rgbled_6bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/> <!-- Sch=led0_b    -->
+    <pin index="4"  name="rgbled_6bits_tri_o_1" iostandard="LVCMOS33" loc="B16"/> <!-- Sch=led0_g    -->
+    <pin index="5"  name="rgbled_6bits_tri_o_2" iostandard="LVCMOS33" loc="B17"/> <!-- Sch=led0_r    -->
+    <pin index="6"  name="rgbled_6bits_tri_o_3" iostandard="LVCMOS33" loc="A16"/> <!-- Sch=led1_b    -->
+    <pin index="7"  name="rgbled_6bits_tri_o_4" iostandard="LVCMOS33" loc="A18"/> <!-- Sch=led1_g    -->
+    <pin index="8"  name="rgbled_6bits_tri_o_5" iostandard="LVCMOS33" loc="A19"/> <!-- Sch=led1_r    -->
+	
+    <pin index="9"  name="JA1"                  iostandard="LVCMOS33" loc="H17"/> <!-- Sch=ja1_fpga  -->
+    <pin index="10" name="JA2"                  iostandard="LVCMOS33" loc="H18"/> <!-- Sch=ja2_fpga  -->
+    <pin index="11" name="JA3"                  iostandard="LVCMOS33" loc="E16"/> <!-- Sch=ja3_fpga  -->
+    <pin index="12" name="JA4"                  iostandard="LVCMOS33" loc="F16"/> <!-- Sch=ja4_fpga  -->
+    <pin index="13" name="JA7"                  iostandard="LVCMOS33" loc="D17"/> <!-- Sch=ja7_fpga  -->
+    <pin index="14" name="JA8"                  iostandard="LVCMOS33" loc="D16"/> <!-- Sch=ja8_fpga  -->
+    <pin index="15" name="JA9"                  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=ja9_fpga  -->
+    <pin index="16" name="JA10"                 iostandard="LVCMOS33" loc="E15"/> <!-- Sch=ja10_fpga -->
+    
+	<pin index="17" name="JB1"                  iostandard="LVCMOS33" loc="G16"/> <!-- Sch=jb1_fpga  -->
+    <pin index="18" name="JB2"                  iostandard="LVCMOS33" loc="G15"/> <!-- Sch=jb2_fpga  -->
+    <pin index="19" name="JB3"                  iostandard="LVCMOS33" loc="E18"/> <!-- Sch=jb3_fpga  -->
+    <pin index="20" name="JB4"                  iostandard="LVCMOS33" loc="F18"/> <!-- Sch=jb4_fpga  -->
+    <pin index="21" name="JB7"                  iostandard="LVCMOS33" loc="F17"/> <!-- Sch=jb7_fpga  -->
+    <pin index="22" name="JB8"                  iostandard="LVCMOS33" loc="G17"/> <!-- Sch=jb8_fpga  -->
+    <pin index="23" name="JB9"                  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=jb9_fpga  -->
+    <pin index="24" name="JB10"                 iostandard="LVCMOS33" loc="C15"/> <!-- Sch=jb10_fpga -->
+</pins>
+</part_info>
diff --git a/HDL/boards/eclypse_z7/brd/A.0/preset.xml b/HDL/boards/eclypse_z7/brd/A.0/preset.xml
new file mode 100644
index 00000000..352e4591
--- /dev/null
+++ b/HDL/boards/eclypse_z7/brd/A.0/preset.xml
@@ -0,0 +1,608 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="ps7_preset">
+		<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" 			value="666.666687"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" 			value="10.158730"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" 			value="125.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" 			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ"  			value="50.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ"  			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ"   			value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" 					value="40"					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1"   			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" 					value="1333.333"  			/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0"   			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1"   			value="7"  					/>
+				<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" 					value="32"					/>
+				<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" 					value="1066.667"  			/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" 						value="0x3FFFFFFF"			/>
+				<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" 						value="MIO 16 .. 27"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO"						value="MIO 52 .. 53"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" 				value="IO PLL"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" 			value="8"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" 				value="1000 Mbps"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" 						value="MIO 9"				/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE"					value="0" 					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT"						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" 						value="0"		  			/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_ENET0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_I2C1"     						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_UART0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_ENET0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_GPIO"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_I2C1"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_QSPI"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_SDIO0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_UART0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_USB0"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" 				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" 						value="MIO"  				/>
+				<user_parameter name="CONFIG.PCW_I2C0_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_GRP_INT_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" 							value="MIO 12 .. 13"  		/>
+				<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ"   				value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_SELECT" 						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV"  					value="30"					/>
+				<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ"   					value="1000.000"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE"							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_10_PULLUP"							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_10_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" 						value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_11_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_12_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_13_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_14_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_15_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_16_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_17_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_18_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_19_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_1_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_20_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_21_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_22_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_23_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_24_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_25_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_26_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_27_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_28_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_29_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_2_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_30_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_31_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_32_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_33_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_34_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_35_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_36_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_37_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_38_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_39_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_3_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_40_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_41_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_42_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_43_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_44_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_45_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_46_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_47_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_48_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_49_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_4_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_50_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_51_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE"							value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_52_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_53_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_5_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_6_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_7_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_8_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_9_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" 					value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#I2C 1#I2C 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" 						value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+				<user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" 		value="0.029" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" 		value="0.031" 				/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0"  			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" 					value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO"						value="MIO 8"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO"					value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" 				value="5"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ"  				value="200"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" 							value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO"							value="MIO 47"  			/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE"					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" 				value="1"					/>
+				<user_parameter name="CONFIG.PCW_SD0_SD0_IO"							value="MIO 40 .. 45"  		/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" 				value="20"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ"  				value="50"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" 				value="x4"  				/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0"  			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_UART0_IO" 						value="MIO 14 .. 15"  		/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" 				value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ"  				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ"   			value="533.333374"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" 			value="3"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" 						value="8"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" 			value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" 						value="6"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" 			value="4096 MBits"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" 			value="32.2611"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" 			value="32.2666"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" 			value="44.6376"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" 			value="44.3743"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2"		value="0.029"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3"		value="0.031"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" 			value="32.5236"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" 			value="32.3526"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" 			value="44.4929"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" 			value="44.4683"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" 				value="16 Bits"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" 				value="DDR 3 (Low Voltage)" />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" 					value="MT41K256M16 RE-125"  />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" 			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" 				value="DDR3_1066F"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW"						value="40.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN"					value="35.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" 						value="48.75"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD"						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ"  				value="60"  				/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_IO" 						value="MIO 46"  			/>
+				<user_parameter name="CONFIG.PCW_USB0_USB0_IO" 							value="MIO 28 .. 39"  		/>
+				<user_parameter name="CONFIG.PCW_USB1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" 						value="Share reset pin"  	/>
+				<!--
+				<user_parameter name="CONFIG.PCW_USE_DMA0" 								value="0" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" 			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" 			value="2"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CLK0_FREQ"								value="100000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK1_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK2_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK3_FREQ"								value="10000000"  			/>
+				-->
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="sys_clock_preset">
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+			<user_parameters>
+				<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"                            /> 
+				<user_parameter name="CONFIG.PRIM_SOURCE"  value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"                           />
+				<user_parameter name="CONFIG.SECONDARY_IN_FREQ"    value="125"                            />
+				<user_parameter name="CONFIG.SECONDARY_SOURCE"     value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="btn_2bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_6bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/HDL/boards/eclypse_z7/brd/B.0/board.xml b/HDL/boards/eclypse_z7/brd/B.0/board.xml
new file mode 100644
index 00000000..20768cd0
--- /dev/null
+++ b/HDL/boards/eclypse_z7/brd/B.0/board.xml
@@ -0,0 +1,376 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://digilent.com/reference/programmable-logic/eclypse-z7/start" preset_file="preset.xml">
+<compatible_board_revisions>
+	<revision id="0">B.0</revision>
+</compatible_board_revisions>
+<file_version>1.1</file_version>
+<description>Eclypse Z7</description>
+
+<components>
+	<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
+	<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/eclypse-z7/start">
+		<interfaces> 
+			<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
+				<port_maps>
+					<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
+						<pin_maps>
+							<pin_map port_index="0" component_pin="sys_clk"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+				<parameters>
+					<parameter name="frequency" value="125000000"/>
+				</parameters>
+			</interface>
+			<interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
+				<description>Buttons</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/> 
+							<pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
+				<description>8 LEDs</description>
+				<preferred_ips>
+					<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+				</preferred_ips>
+				<port_maps>
+					<port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/> 
+							<pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/> 
+							<pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/> 
+							<pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/> 
+							<pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/> 
+							<pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JA10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
+				<port_maps>
+					<port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB1"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB2"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB3"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB4"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB7"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB8"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB9"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+					<port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+						<pin_maps>
+							<pin_map port_index="0" component_pin="JB10"/> 
+						</pin_maps>
+					</port_map>
+				</port_maps>
+			</interface>
+			<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset"> 
+			</interface>
+		</interfaces>
+	</component>
+	
+	<!-- Descriptions of components that will appear in the IPI Board tab -->
+	<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
+		<description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
+	</component>
+	<component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+		<description>Buttons 1 to 0</description>
+	</component>
+	<component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
+		<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
+	</component>
+	<component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JA</description>
+	</component>
+	<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+		<description>Pmod Connector JB</description>
+	</component>
+	<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+</components>
+
+<jtag_chains>
+	<jtag_chain name="chain1">
+		<position name="0" component="part0"/>
+	</jtag_chain>
+</jtag_chains>
+
+<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
+	<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+		<connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
+	</connection>
+	<connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
+		<connection_map name="part0_btn_2bits_map"    c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+	<connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
+		<connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
+	</connection>
+	<connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
+		<connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+	<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
+		<connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
+	</connection>
+</connections>
+
+</board>
\ No newline at end of file
diff --git a/HDL/boards/eclypse_z7/brd/B.0/part0_pins.xml b/HDL/boards/eclypse_z7/brd/B.0/part0_pins.xml
new file mode 100644
index 00000000..71a442f5
--- /dev/null
+++ b/HDL/boards/eclypse_z7/brd/B.0/part0_pins.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7z020clg484-1">
+<pins>
+    <pin index="0"  name="sys_clk"              iostandard="LVCMOS33" loc="D18"/> <!-- Sch=sysclk    -->
+    
+	<pin index="1"  name="btn_2bits_tri_i_0"    iostandard="LVCMOS33" loc="C17"/> <!-- Sch=btn[0]    -->
+    <pin index="2"  name="btn_2bits_tri_i_1"    iostandard="LVCMOS33" loc="C18"/> <!-- Sch=btn[1]    -->
+    
+	<pin index="3"  name="rgbled_6bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/> <!-- Sch=led0_b    -->
+    <pin index="4"  name="rgbled_6bits_tri_o_1" iostandard="LVCMOS33" loc="B16"/> <!-- Sch=led0_g    -->
+    <pin index="5"  name="rgbled_6bits_tri_o_2" iostandard="LVCMOS33" loc="B17"/> <!-- Sch=led0_r    -->
+    <pin index="6"  name="rgbled_6bits_tri_o_3" iostandard="LVCMOS33" loc="A16"/> <!-- Sch=led1_b    -->
+    <pin index="7"  name="rgbled_6bits_tri_o_4" iostandard="LVCMOS33" loc="A18"/> <!-- Sch=led1_g    -->
+    <pin index="8"  name="rgbled_6bits_tri_o_5" iostandard="LVCMOS33" loc="A19"/> <!-- Sch=led1_r    -->
+	
+    <pin index="9"  name="JA1"                  iostandard="LVCMOS33" loc="B15"/> <!-- Sch=ja1_fpga  -->
+    <pin index="10" name="JA2"                  iostandard="LVCMOS33" loc="C15"/> <!-- Sch=ja2_fpga  -->
+    <pin index="11" name="JA3"                  iostandard="LVCMOS33" loc="D15"/> <!-- Sch=ja3_fpga  -->
+    <pin index="12" name="JA4"                  iostandard="LVCMOS33" loc="E16"/> <!-- Sch=ja4_fpga  -->
+    <pin index="13" name="JA7"                  iostandard="LVCMOS33" loc="E15"/> <!-- Sch=ja7_fpga  -->
+    <pin index="14" name="JA8"                  iostandard="LVCMOS33" loc="F17"/> <!-- Sch=ja8_fpga  -->
+    <pin index="15" name="JA9"                  iostandard="LVCMOS33" loc="F16"/> <!-- Sch=ja9_fpga  -->
+    <pin index="16" name="JA10"                 iostandard="LVCMOS33" loc="G16"/> <!-- Sch=ja10_fpga -->
+    
+	<pin index="17" name="JB1"                  iostandard="LVCMOS33" loc="G15"/> <!-- Sch=jb1_fpga  -->
+    <pin index="18" name="JB2"                  iostandard="LVCMOS33" loc="D16"/> <!-- Sch=jb2_fpga  -->
+    <pin index="19" name="JB3"                  iostandard="LVCMOS33" loc="D17"/> <!-- Sch=jb3_fpga  -->
+    <pin index="20" name="JB4"                  iostandard="LVCMOS33" loc="E18"/> <!-- Sch=jb4_fpga  -->
+    <pin index="21" name="JB7"                  iostandard="LVCMOS33" loc="F18"/> <!-- Sch=jb7_fpga  -->
+    <pin index="22" name="JB8"                  iostandard="LVCMOS33" loc="G17"/> <!-- Sch=jb8_fpga  -->
+    <pin index="23" name="JB9"                  iostandard="LVCMOS33" loc="H18"/> <!-- Sch=jb9_fpga  -->
+    <pin index="24" name="JB10"                 iostandard="LVCMOS33" loc="H17"/> <!-- Sch=jb10_fpga -->
+</pins>
+</part_info>
diff --git a/HDL/boards/eclypse_z7/brd/B.0/preset.xml b/HDL/boards/eclypse_z7/brd/B.0/preset.xml
new file mode 100644
index 00000000..c32c99d5
--- /dev/null
+++ b/HDL/boards/eclypse_z7/brd/B.0/preset.xml
@@ -0,0 +1,608 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<!-- Contains IP configurations for Block/Connection Automation flows -->
+<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
+<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
+<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+	<ip_preset preset_proc_name="ps7_preset">
+		<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+			<user_parameters>
+				<user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" 			value="666.666687"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" 			value="10.158730"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" 			value="125.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" 			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" 			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ"  			value="50.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ"   			value="10.000000"  			/>
+				<user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ"  			value="200.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" 		value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ"  			value="100.000000"  		/>
+				<user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ"   			value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" 					value="40"					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1"   			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" 					value="1333.333"  			/>
+				<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0"   			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1"   			value="7"  					/>
+				<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" 					value="32"					/>
+				<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" 					value="1066.667"  			/>
+				<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0"  				value="2"  					/>
+				<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" 						value="0x3FFFFFFF"			/>
+				<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" 						value="MIO 16 .. 27"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO"						value="MIO 52 .. 53"  		/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" 				value="IO PLL"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" 			value="8"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" 				value="1000 Mbps"  			/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" 						value="MIO 9"				/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE"					value="0" 					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT"						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" 						value="0"		  			/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_ENET0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_I2C1"     						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_EMIO_UART0"    						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_EN_ENET0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_GPIO"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_I2C1"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_QSPI"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_SDIO0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_UART0" 								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_EN_USB0"  								value="1" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" 				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" 						value="MIO"  				/>
+				<user_parameter name="CONFIG.PCW_I2C0_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_GRP_INT_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" 							value="MIO 12 .. 13"  		/>
+				<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ"   				value="111.111115"  		/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_I2C_RESET_SELECT" 						value="Share reset pin"  	/>
+				<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV"  					value="30"					/>
+				<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ"   					value="1000.000"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_0_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE"							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_10_PULLUP"							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_10_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" 						value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_11_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_12_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_13_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_14_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" 						value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_15_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_16_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_17_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_18_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_19_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_1_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_20_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_21_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_22_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_23_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_24_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_25_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_26_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_27_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_28_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_29_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_2_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_30_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_31_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_32_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_33_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_34_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_35_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_36_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_37_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_38_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_39_SLEW"	 						value="fast"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_3_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_40_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_41_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_42_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_43_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_44_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_45_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_46_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" 						value="in"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_47_SLEW"	 						value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_48_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_49_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_4_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_50_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_51_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE"							value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_52_SLEW"							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" 						value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" 						value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_53_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" 						value="inout"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_5_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_6_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_7_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" 							value="disabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_8_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" 						value="out"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" 							value="LVCMOS 3.3V"  		/>
+				<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" 							value="enabled"  			/>
+				<user_parameter name="CONFIG.PCW_MIO_9_SLEW" 							value="slow"  				/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" 					value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#I2C 1#I2C 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
+				<user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" 						value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
+				<user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE"				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" 		value="0.202" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" 		value="0.029" 				/>
+				<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" 		value="0.031" 				/>
+				<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0"  			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" 					value="LVCMOS 1.8V"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO"						value="MIO 8"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO"					value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" 				value="5"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" 				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ"  				value="200"  				/>
+				<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" 							value="MIO 1 .. 6"  		/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO"							value="MIO 47"  			/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE"					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" 				value="1"					/>
+				<user_parameter name="CONFIG.PCW_SD0_SD0_IO"							value="MIO 40 .. 45"  		/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" 				value="20"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ"  				value="50"  				/>
+				<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" 				value="x4"  				/>
+				<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0"  				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0"  			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" 				value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_UART0_UART0_IO" 						value="MIO 14 .. 15"  		/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" 				value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ"  				value="100"  				/>
+				<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" 				value="1"			  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ"   			value="533.333374"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" 			value="3"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" 						value="8"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" 				value="0.311"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" 				value="0.304"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" 		value="63.2909"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" 		value="49.1639"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH"	value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" 			value="10"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" 						value="6"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" 			value="4096 MBits"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" 			value="32.2611"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" 			value="32.2666"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" 			value="44.6376"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" 			value="44.3743"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" 		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY"	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1"		value="0.202"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2"		value="0.029"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3"		value="0.031"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" 			value="32.5236"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" 			value="32.3526"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" 			value="44.4929"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" 			value="44.4683"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH"		value="0"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" 	value="165.1"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" 				value="16 Bits"  			/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" 				value="DDR 3 (Low Voltage)" />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" 					value="MT41K256M16 RE-125"  />
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" 			value="15"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" 				value="DDR3_1066F"  		/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW"						value="40.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN"					value="35.0"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" 						value="48.75"  				/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD"						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" 						value="7"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE"				value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ"  				value="60"  				/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE"						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB0_RESET_IO" 						value="MIO 46"  			/>
+				<user_parameter name="CONFIG.PCW_USB0_USB0_IO" 							value="MIO 28 .. 39"  		/>
+				<user_parameter name="CONFIG.PCW_USB1_RESET_ENABLE"						value="0"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" 						value="1"  					/>
+				<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" 						value="Share reset pin"  	/>
+				<!--
+				<user_parameter name="CONFIG.PCW_USE_DMA0" 								value="0" 					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" 					value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" 					value="0"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" 			value="5"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" 			value="2"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" 			value="1"  					/>
+				<user_parameter name="CONFIG.PCW_CLK0_FREQ"								value="100000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK1_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK2_FREQ"								value="10000000"  			/>
+				<user_parameter name="CONFIG.PCW_CLK3_FREQ"								value="10000000"  			/>
+				-->
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="sys_clock_preset">
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
+			<user_parameters>
+				<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"                            /> 
+				<user_parameter name="CONFIG.PRIM_SOURCE"  value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"                           />
+				<user_parameter name="CONFIG.SECONDARY_IN_FREQ"    value="125"                            />
+				<user_parameter name="CONFIG.SECONDARY_SOURCE"     value="Single_ended_clock_capable_pin" />
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="btn_2bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="2"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+	<ip_preset preset_proc_name="rgbled_6bits_preset">
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+				<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+				<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/> 
+				<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+				<user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+		<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+			<user_parameters>
+				<user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+				<user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+			</user_parameters>
+		</ip>
+	</ip_preset>
+</ip_presets>
\ No newline at end of file
diff --git a/HDL/boards/snickerdoodle_black/brd/1.0/board.xml b/HDL/boards/snickerdoodle_black/brd/1.0/board.xml
index 6d54eaa5..cce08a60 100755
--- a/HDL/boards/snickerdoodle_black/brd/1.0/board.xml
+++ b/HDL/boards/snickerdoodle_black/brd/1.0/board.xml
@@ -25,6 +25,4 @@
       <position name="0" component="part0"/>
     </jtag_chain>
   </jtag_chains>
-  <connections>
-  </connections>
 </board>
diff --git a/HDL/boards/stemlab_122_16/brd/1.0/board.xml b/HDL/boards/stemlab_122_16/brd/1.0/board.xml
index 7a46bdb3..bfb54d83 100644
--- a/HDL/boards/stemlab_122_16/brd/1.0/board.xml
+++ b/HDL/boards/stemlab_122_16/brd/1.0/board.xml
@@ -26,6 +26,4 @@
       <position name="0" component="part0"/>
     </jtag_chain>
   </jtag_chains>
-  <connections>
-  </connections>
 </board>
diff --git a/HDL/boards/stemlab_122_16/brd/1.0/part0_pins.xml b/HDL/boards/stemlab_122_16/brd/1.0/part0_pins.xml
index 3b45ff68..5f20aba7 100644
--- a/HDL/boards/stemlab_122_16/brd/1.0/part0_pins.xml
+++ b/HDL/boards/stemlab_122_16/brd/1.0/part0_pins.xml
@@ -2,81 +2,81 @@
 <part_info part_name="xc7z020clg400-1">
   <pins>
 
-    <pin index="0"  name="led_o[0]" iostandard="LVCMOS33" loc="F16"/>
-    <pin index="1"  name="led_o[1]" iostandard="LVCMOS33" loc="F17"/>
-    <pin index="2"  name="led_o[2]" iostandard="LVCMOS33" loc="G15"/>
-    <pin index="3"  name="led_o[3]" iostandard="LVCMOS33" loc="H15"/>
-    <pin index="4"  name="led_o[4]" iostandard="LVCMOS33" loc="K14"/>
-    <pin index="5"  name="led_o[5]" iostandard="LVCMOS33" loc="G14"/>
-    <pin index="6"  name="led_o[6]" iostandard="LVCMOS33" loc="J15"/>
-    <pin index="7"  name="led_o[7]" iostandard="LVCMOS33" loc="J14"/>
+    <pin index="0"  name="led_o_0" iostandard="LVCMOS33" loc="F16"/>
+    <pin index="1"  name="led_o_1" iostandard="LVCMOS33" loc="F17"/>
+    <pin index="2"  name="led_o_2" iostandard="LVCMOS33" loc="G15"/>
+    <pin index="3"  name="led_o_3" iostandard="LVCMOS33" loc="H15"/>
+    <pin index="4"  name="led_o_4" iostandard="LVCMOS33" loc="K14"/>
+    <pin index="5"  name="led_o_5" iostandard="LVCMOS33" loc="G14"/>
+    <pin index="6"  name="led_o_6" iostandard="LVCMOS33" loc="J15"/>
+    <pin index="7"  name="led_o_7" iostandard="LVCMOS33" loc="J14"/>
 
-    <pin index="8"  name="exp_p_io[0]" iostandard="LVCMOS33" loc="G17"/>
-    <pin index="9"  name="exp_p_io[1]" iostandard="LVCMOS33" loc="H16"/>
-    <pin index="10" name="exp_p_io[2]" iostandard="LVCMOS33" loc="J18"/>
-    <pin index="11" name="exp_p_io[3]" iostandard="LVCMOS33" loc="K17"/>
-    <pin index="12" name="exp_p_io[4]" iostandard="LVCMOS33" loc="L14"/>
-    <pin index="13" name="exp_p_io[5]" iostandard="LVCMOS33" loc="L16"/>
-    <pin index="14" name="exp_p_io[6]" iostandard="LVCMOS33" loc="K16"/>
-    <pin index="15" name="exp_p_io[7]" iostandard="LVCMOS33" loc="M14"/>
+    <pin index="8"  name="exp_p_io_0" iostandard="LVCMOS33" loc="G17"/>
+    <pin index="9"  name="exp_p_io_1" iostandard="LVCMOS33" loc="H16"/>
+    <pin index="10" name="exp_p_io_2" iostandard="LVCMOS33" loc="J18"/>
+    <pin index="11" name="exp_p_io_3" iostandard="LVCMOS33" loc="K17"/>
+    <pin index="12" name="exp_p_io_4" iostandard="LVCMOS33" loc="L14"/>
+    <pin index="13" name="exp_p_io_5" iostandard="LVCMOS33" loc="L16"/>
+    <pin index="14" name="exp_p_io_6" iostandard="LVCMOS33" loc="K16"/>
+    <pin index="15" name="exp_p_io_7" iostandard="LVCMOS33" loc="M14"/>
 
-    <pin index="16" name="exp_n_io[0]" iostandard="LVCMOS33" loc="G18"/>
-    <pin index="17" name="exp_n_io[1]" iostandard="LVCMOS33" loc="H17"/>
-    <pin index="18" name="exp_n_io[2]" iostandard="LVCMOS33" loc="H18"/>
-    <pin index="29" name="exp_n_io[3]" iostandard="LVCMOS33" loc="K18"/>
-    <pin index="20" name="exp_n_io[4]" iostandard="LVCMOS33" loc="L15"/>
-    <pin index="21" name="exp_n_io[5]" iostandard="LVCMOS33" loc="L17"/>
-    <pin index="22" name="exp_n_io[6]" iostandard="LVCMOS33" loc="J16"/>
-    <pin index="23" name="exp_n_io[7]" iostandard="LVCMOS33" loc="M15"/>
+    <pin index="16" name="exp_n_io_0" iostandard="LVCMOS33" loc="G18"/>
+    <pin index="17" name="exp_n_io_1" iostandard="LVCMOS33" loc="H17"/>
+    <pin index="18" name="exp_n_io_2" iostandard="LVCMOS33" loc="H18"/>
+    <pin index="29" name="exp_n_io_3" iostandard="LVCMOS33" loc="K18"/>
+    <pin index="20" name="exp_n_io_4" iostandard="LVCMOS33" loc="L15"/>
+    <pin index="21" name="exp_n_io_5" iostandard="LVCMOS33" loc="L17"/>
+    <pin index="22" name="exp_n_io_6" iostandard="LVCMOS33" loc="J16"/>
+    <pin index="23" name="exp_n_io_7" iostandard="LVCMOS33" loc="M15"/>
 
-    <pin index="24" name="daisy_p_i[0]" iostandard="LVCMOS33" loc="P14"/>
-    <pin index="25" name="daisy_n_i[0]" iostandard="LVCMOS33" loc="R14"/>
-    <pin index="26" name="daisy_p_i[1]" iostandard="LVCMOS33" loc="N18"/>
-    <pin index="27" name="daisy_n_i[1]" iostandard="LVCMOS33" loc="P19"/>
-    <pin index="28" name="daisy_p_o[0]" iostandard="LVCMOS33" loc="T12"/>
-    <pin index="29" name="daisy_n_o[0]" iostandard="LVCMOS33" loc="U12"/>
-    <pin index="30" name="daisy_p_o[1]" iostandard="LVCMOS33" loc="U14"/>
-    <pin index="31" name="daisy_n_o[1]" iostandard="LVCMOS33" loc="U15"/>
+    <pin index="24" name="daisy_p_i_0" iostandard="DIFF_HSTL_I_18" loc="P14"/>
+    <pin index="25" name="daisy_n_i_0" iostandard="DIFF_HSTL_I_18" loc="R14"/>
+    <pin index="26" name="daisy_p_i_1" iostandard="DIFF_HSTL_I_18" loc="N18"/>
+    <pin index="27" name="daisy_n_i_1" iostandard="DIFF_HSTL_I_18" loc="P19"/>
+    <pin index="28" name="daisy_p_o_0" iostandard="DIFF_HSTL_I_18" loc="T12"/>
+    <pin index="29" name="daisy_n_o_0" iostandard="DIFF_HSTL_I_18" loc="U12"/>
+    <pin index="30" name="daisy_p_o_1" iostandard="DIFF_HSTL_I_18" loc="U14"/>
+    <pin index="31" name="daisy_n_o_1" iostandard="DIFF_HSTL_I_18" loc="U15"/>
 
-    <pin index="32" name="adc_dat_i[0][0]"  iostandard="LVCMOS18" loc="V17"/>
-    <pin index="33" name="adc_dat_i[0][1]"  iostandard="LVCMOS18" loc="U17"/>
-    <pin index="34" name="adc_dat_i[0][2]"  iostandard="LVCMOS18" loc="Y17"/>
-    <pin index="35" name="adc_dat_i[0][3]"  iostandard="LVCMOS18" loc="W16"/>
-    <pin index="36" name="adc_dat_i[0][4]"  iostandard="LVCMOS18" loc="Y16"/>
-    <pin index="37" name="adc_dat_i[0][5]"  iostandard="LVCMOS18" loc="W15"/>
-    <pin index="38" name="adc_dat_i[0][6]"  iostandard="LVCMOS18" loc="W14"/>
-    <pin index="39" name="adc_dat_i[0][7]"  iostandard="LVCMOS18" loc="Y14"/>
-    <pin index="40" name="adc_dat_i[0][8]"  iostandard="LVCMOS18" loc="W13"/>
-    <pin index="41" name="adc_dat_i[0][9]"  iostandard="LVCMOS18" loc="V12"/>
-    <pin index="42" name="adc_dat_i[0][10]" iostandard="LVCMOS18" loc="V13"/>
-    <pin index="43" name="adc_dat_i[0][11]" iostandard="LVCMOS18" loc="T14"/>
-    <pin index="44" name="adc_dat_i[0][12]" iostandard="LVCMOS18" loc="T15"/>
-    <pin index="45" name="adc_dat_i[0][13]" iostandard="LVCMOS18" loc="V15"/>
-    <pin index="46" name="adc_dat_i[0][14]" iostandard="LVCMOS18" loc="T16"/>
-    <pin index="47" name="adc_dat_i[0][15]" iostandard="LVCMOS18" loc="V16"/>
+    <pin index="32" name="adc_dat_i_0_0"  iostandard="LVCMOS18" loc="V17"/>
+    <pin index="33" name="adc_dat_i_0_1"  iostandard="LVCMOS18" loc="U17"/>
+    <pin index="34" name="adc_dat_i_0_2"  iostandard="LVCMOS18" loc="Y17"/>
+    <pin index="35" name="adc_dat_i_0_3"  iostandard="LVCMOS18" loc="W16"/>
+    <pin index="36" name="adc_dat_i_0_4"  iostandard="LVCMOS18" loc="Y16"/>
+    <pin index="37" name="adc_dat_i_0_5"  iostandard="LVCMOS18" loc="W15"/>
+    <pin index="38" name="adc_dat_i_0_6"  iostandard="LVCMOS18" loc="W14"/>
+    <pin index="39" name="adc_dat_i_0_7"  iostandard="LVCMOS18" loc="Y14"/>
+    <pin index="40" name="adc_dat_i_0_8"  iostandard="LVCMOS18" loc="W13"/>
+    <pin index="41" name="adc_dat_i_0_9"  iostandard="LVCMOS18" loc="V12"/>
+    <pin index="42" name="adc_dat_i_0_10" iostandard="LVCMOS18" loc="V13"/>
+    <pin index="43" name="adc_dat_i_0_11" iostandard="LVCMOS18" loc="T14"/>
+    <pin index="44" name="adc_dat_i_0_12" iostandard="LVCMOS18" loc="T15"/>
+    <pin index="45" name="adc_dat_i_0_13" iostandard="LVCMOS18" loc="V15"/>
+    <pin index="46" name="adc_dat_i_0_14" iostandard="LVCMOS18" loc="T16"/>
+    <pin index="47" name="adc_dat_i_0_15" iostandard="LVCMOS18" loc="V16"/>
 
-    <pin index="48" name="adc_dat_i[1][0]"  iostandard="LVCMOS18" loc="T17"/>
-    <pin index="49" name="adc_dat_i[1][1]"  iostandard="LVCMOS18" loc="R16"/>
-    <pin index="50" name="adc_dat_i[1][2]"  iostandard="LVCMOS18" loc="R18"/>
-    <pin index="51" name="adc_dat_i[1][3]"  iostandard="LVCMOS18" loc="P16"/>
-    <pin index="52" name="adc_dat_i[1][4]"  iostandard="LVCMOS18" loc="P18"/>
-    <pin index="53" name="adc_dat_i[1][5]"  iostandard="LVCMOS18" loc="N17"/>
-    <pin index="54" name="adc_dat_i[1][6]"  iostandard="LVCMOS18" loc="R19"/>
-    <pin index="55" name="adc_dat_i[1][7]"  iostandard="LVCMOS18" loc="T20"/>
-    <pin index="56" name="adc_dat_i[1][8]"  iostandard="LVCMOS18" loc="T19"/>
-    <pin index="57" name="adc_dat_i[1][9]"  iostandard="LVCMOS18" loc="U20"/>
-    <pin index="58" name="adc_dat_i[1][10]" iostandard="LVCMOS18" loc="V20"/>
-    <pin index="59" name="adc_dat_i[1][11]" iostandard="LVCMOS18" loc="W20"/>
-    <pin index="60" name="adc_dat_i[1][12]" iostandard="LVCMOS18" loc="W19"/>
-    <pin index="61" name="adc_dat_i[1][13]" iostandard="LVCMOS18" loc="Y19"/>
-    <pin index="62" name="adc_dat_i[1][14]" iostandard="LVCMOS18" loc="W18"/>
-    <pin index="63" name="adc_dat_i[1][15]" iostandard="LVCMOS18" loc="Y18"/>
+    <pin index="48" name="adc_dat_i_1_0"  iostandard="LVCMOS18" loc="T17"/>
+    <pin index="49" name="adc_dat_i_1_1"  iostandard="LVCMOS18" loc="R16"/>
+    <pin index="50" name="adc_dat_i_1_2"  iostandard="LVCMOS18" loc="R18"/>
+    <pin index="51" name="adc_dat_i_1_3"  iostandard="LVCMOS18" loc="P16"/>
+    <pin index="52" name="adc_dat_i_1_4"  iostandard="LVCMOS18" loc="P18"/>
+    <pin index="53" name="adc_dat_i_1_5"  iostandard="LVCMOS18" loc="N17"/>
+    <pin index="54" name="adc_dat_i_1_6"  iostandard="LVCMOS18" loc="R19"/>
+    <pin index="55" name="adc_dat_i_1_7"  iostandard="LVCMOS18" loc="T20"/>
+    <pin index="56" name="adc_dat_i_1_8"  iostandard="LVCMOS18" loc="T19"/>
+    <pin index="57" name="adc_dat_i_1_9"  iostandard="LVCMOS18" loc="U20"/>
+    <pin index="58" name="adc_dat_i_1_10" iostandard="LVCMOS18" loc="V20"/>
+    <pin index="59" name="adc_dat_i_1_11" iostandard="LVCMOS18" loc="W20"/>
+    <pin index="60" name="adc_dat_i_1_12" iostandard="LVCMOS18" loc="W19"/>
+    <pin index="61" name="adc_dat_i_1_13" iostandard="LVCMOS18" loc="Y19"/>
+    <pin index="62" name="adc_dat_i_1_14" iostandard="LVCMOS18" loc="W18"/>
+    <pin index="63" name="adc_dat_i_1_15" iostandard="LVCMOS18" loc="Y18"/>
 
-    <pin index="64" name="adc_clk_i[0]" iostandard="DIFF_HSTL_I_18" loc="U19"/>
-    <pin index="65" name="adc_clk_i[1]" iostandard="DIFF_HSTL_I_18" loc="U18"/>
+    <pin index="64" name="adc_clk_i_0" iostandard="DIFF_HSTL_I_18" loc="U19"/>
+    <pin index="65" name="adc_clk_i_1" iostandard="DIFF_HSTL_I_18" loc="U18"/>
 
-    <pin index="66" name="adc_clk_o[0]" iostandard="LVCMOS18" loc="N20"/>
-    <pin index="67" name="adc_clk_o[1]" iostandard="LVCMOS18" loc="P20"/>
+    <pin index="66" name="adc_clk_o_0" iostandard="LVCMOS18" loc="N20"/>
+    <pin index="67" name="adc_clk_o_1" iostandard="LVCMOS18" loc="P20"/>
     <pin index="67" name="adc_cdcs_o" iostandard="LVCMOS18" loc="V18"/>
 
     
diff --git a/HDL/boards/stemlab_125_14/brd/1.1/board.xml b/HDL/boards/stemlab_125_14/brd/1.1/board.xml
index a8d751d9..927a8f07 100644
--- a/HDL/boards/stemlab_125_14/brd/1.1/board.xml
+++ b/HDL/boards/stemlab_125_14/brd/1.1/board.xml
@@ -26,6 +26,4 @@
       <position name="0" component="part0"/>
     </jtag_chain>
   </jtag_chains>
-  <connections>
-  </connections>
 </board>
diff --git a/HDL/boards/stemlab_125_14/brd/1.1/part0_pins.xml b/HDL/boards/stemlab_125_14/brd/1.1/part0_pins.xml
index 0d6e4168..785721bd 100644
--- a/HDL/boards/stemlab_125_14/brd/1.1/part0_pins.xml
+++ b/HDL/boards/stemlab_125_14/brd/1.1/part0_pins.xml
@@ -2,81 +2,81 @@
 <part_info part_name="xc7z010clg400-1">
   <pins>
 
-    <pin index="0"  name="led_o[0]" iostandard="LVCMOS33" loc="F16"/>
-    <pin index="1"  name="led_o[1]" iostandard="LVCMOS33" loc="F17"/>
-    <pin index="2"  name="led_o[2]" iostandard="LVCMOS33" loc="G15"/>
-    <pin index="3"  name="led_o[3]" iostandard="LVCMOS33" loc="H15"/>
-    <pin index="4"  name="led_o[4]" iostandard="LVCMOS33" loc="K14"/>
-    <pin index="5"  name="led_o[5]" iostandard="LVCMOS33" loc="G14"/>
-    <pin index="6"  name="led_o[6]" iostandard="LVCMOS33" loc="J15"/>
-    <pin index="7"  name="led_o[7]" iostandard="LVCMOS33" loc="J14"/>
+    <pin index="0"  name="led_o_0" iostandard="LVCMOS33" loc="F16"/>
+    <pin index="1"  name="led_o_1" iostandard="LVCMOS33" loc="F17"/>
+    <pin index="2"  name="led_o_2" iostandard="LVCMOS33" loc="G15"/>
+    <pin index="3"  name="led_o_3" iostandard="LVCMOS33" loc="H15"/>
+    <pin index="4"  name="led_o_4" iostandard="LVCMOS33" loc="K14"/>
+    <pin index="5"  name="led_o_5" iostandard="LVCMOS33" loc="G14"/>
+    <pin index="6"  name="led_o_6" iostandard="LVCMOS33" loc="J15"/>
+    <pin index="7"  name="led_o_7" iostandard="LVCMOS33" loc="J14"/>
 
-    <pin index="8"  name="exp_p_io[0]" iostandard="LVCMOS33" loc="G17"/>
-    <pin index="9"  name="exp_p_io[1]" iostandard="LVCMOS33" loc="H16"/>
-    <pin index="10" name="exp_p_io[2]" iostandard="LVCMOS33" loc="J18"/>
-    <pin index="11" name="exp_p_io[3]" iostandard="LVCMOS33" loc="K17"/>
-    <pin index="12" name="exp_p_io[4]" iostandard="LVCMOS33" loc="L14"/>
-    <pin index="13" name="exp_p_io[5]" iostandard="LVCMOS33" loc="L16"/>
-    <pin index="14" name="exp_p_io[6]" iostandard="LVCMOS33" loc="K16"/>
-    <pin index="15" name="exp_p_io[7]" iostandard="LVCMOS33" loc="M14"/>
+    <pin index="8"  name="exp_p_io_0" iostandard="LVCMOS33" loc="G17"/>
+    <pin index="9"  name="exp_p_io_1" iostandard="LVCMOS33" loc="H16"/>
+    <pin index="10" name="exp_p_io_2" iostandard="LVCMOS33" loc="J18"/>
+    <pin index="11" name="exp_p_io_3" iostandard="LVCMOS33" loc="K17"/>
+    <pin index="12" name="exp_p_io_4" iostandard="LVCMOS33" loc="L14"/>
+    <pin index="13" name="exp_p_io_5" iostandard="LVCMOS33" loc="L16"/>
+    <pin index="14" name="exp_p_io_6" iostandard="LVCMOS33" loc="K16"/>
+    <pin index="15" name="exp_p_io_7" iostandard="LVCMOS33" loc="M14"/>
 
-    <pin index="16" name="exp_n_io[0]" iostandard="LVCMOS33" loc="G18"/>
-    <pin index="17" name="exp_n_io[1]" iostandard="LVCMOS33" loc="H17"/>
-    <pin index="18" name="exp_n_io[2]" iostandard="LVCMOS33" loc="H18"/>
-    <pin index="29" name="exp_n_io[3]" iostandard="LVCMOS33" loc="K18"/>
-    <pin index="20" name="exp_n_io[4]" iostandard="LVCMOS33" loc="L15"/>
-    <pin index="21" name="exp_n_io[5]" iostandard="LVCMOS33" loc="L17"/>
-    <pin index="22" name="exp_n_io[6]" iostandard="LVCMOS33" loc="J16"/>
-    <pin index="23" name="exp_n_io[7]" iostandard="LVCMOS33" loc="M15"/>
+    <pin index="16" name="exp_n_io_0" iostandard="LVCMOS33" loc="G18"/>
+    <pin index="17" name="exp_n_io_1" iostandard="LVCMOS33" loc="H17"/>
+    <pin index="18" name="exp_n_io_2" iostandard="LVCMOS33" loc="H18"/>
+    <pin index="29" name="exp_n_io_3" iostandard="LVCMOS33" loc="K18"/>
+    <pin index="20" name="exp_n_io_4" iostandard="LVCMOS33" loc="L15"/>
+    <pin index="21" name="exp_n_io_5" iostandard="LVCMOS33" loc="L17"/>
+    <pin index="22" name="exp_n_io_6" iostandard="LVCMOS33" loc="J16"/>
+    <pin index="23" name="exp_n_io_7" iostandard="LVCMOS33" loc="M15"/>
 
-    <pin index="24" name="daisy_p_i[0]" iostandard="LVCMOS33" loc="P14"/>
-    <pin index="25" name="daisy_n_i[0]" iostandard="LVCMOS33" loc="R14"/>
-    <pin index="26" name="daisy_p_i[1]" iostandard="LVCMOS33" loc="N18"/>
-    <pin index="27" name="daisy_n_i[1]" iostandard="LVCMOS33" loc="P19"/>
-    <pin index="28" name="daisy_p_o[0]" iostandard="LVCMOS33" loc="T12"/>
-    <pin index="29" name="daisy_n_o[0]" iostandard="LVCMOS33" loc="U12"/>
-    <pin index="30" name="daisy_p_o[1]" iostandard="LVCMOS33" loc="U14"/>
-    <pin index="31" name="daisy_n_o[1]" iostandard="LVCMOS33" loc="U15"/>
+    <pin index="24" name="daisy_p_i_0" iostandard="DIFF_HSTL_I_18" loc="P14"/>
+    <pin index="25" name="daisy_n_i_0" iostandard="DIFF_HSTL_I_18" loc="R14"/>
+    <pin index="26" name="daisy_p_i_1" iostandard="DIFF_HSTL_I_18" loc="N18"/>
+    <pin index="27" name="daisy_n_i_1" iostandard="DIFF_HSTL_I_18" loc="P19"/>
+    <pin index="28" name="daisy_p_o_0" iostandard="DIFF_HSTL_I_18" loc="T12"/>
+    <pin index="29" name="daisy_n_o_0" iostandard="DIFF_HSTL_I_18" loc="U12"/>
+    <pin index="30" name="daisy_p_o_1" iostandard="DIFF_HSTL_I_18" loc="U14"/>
+    <pin index="31" name="daisy_n_o_1" iostandard="DIFF_HSTL_I_18" loc="U15"/>
 
-    <pin index="32" name="adc_dat_i[0][0]"  iostandard="LVCMOS18" loc="V17"/>
-    <pin index="33" name="adc_dat_i[0][1]"  iostandard="LVCMOS18" loc="U17"/>
-    <pin index="34" name="adc_dat_i[0][2]"  iostandard="LVCMOS18" loc="Y17"/>
-    <pin index="35" name="adc_dat_i[0][3]"  iostandard="LVCMOS18" loc="W16"/>
-    <pin index="36" name="adc_dat_i[0][4]"  iostandard="LVCMOS18" loc="Y16"/>
-    <pin index="37" name="adc_dat_i[0][5]"  iostandard="LVCMOS18" loc="W15"/>
-    <pin index="38" name="adc_dat_i[0][6]"  iostandard="LVCMOS18" loc="W14"/>
-    <pin index="39" name="adc_dat_i[0][7]"  iostandard="LVCMOS18" loc="Y14"/>
-    <pin index="40" name="adc_dat_i[0][8]"  iostandard="LVCMOS18" loc="W13"/>
-    <pin index="41" name="adc_dat_i[0][9]"  iostandard="LVCMOS18" loc="V12"/>
-    <pin index="42" name="adc_dat_i[0][10]" iostandard="LVCMOS18" loc="V13"/>
-    <pin index="43" name="adc_dat_i[0][11]" iostandard="LVCMOS18" loc="T14"/>
-    <pin index="44" name="adc_dat_i[0][12]" iostandard="LVCMOS18" loc="T15"/>
-    <pin index="45" name="adc_dat_i[0][13]" iostandard="LVCMOS18" loc="V15"/>
-    <pin index="46" name="adc_dat_i[0][14]" iostandard="LVCMOS18" loc="T16"/>
-    <pin index="47" name="adc_dat_i[0][15]" iostandard="LVCMOS18" loc="V16"/>
+    <pin index="32" name="adc_dat_i_0_0"  iostandard="LVCMOS18" loc="V17"/>
+    <pin index="33" name="adc_dat_i_0_1"  iostandard="LVCMOS18" loc="U17"/>
+    <pin index="34" name="adc_dat_i_0_2"  iostandard="LVCMOS18" loc="Y17"/>
+    <pin index="35" name="adc_dat_i_0_3"  iostandard="LVCMOS18" loc="W16"/>
+    <pin index="36" name="adc_dat_i_0_4"  iostandard="LVCMOS18" loc="Y16"/>
+    <pin index="37" name="adc_dat_i_0_5"  iostandard="LVCMOS18" loc="W15"/>
+    <pin index="38" name="adc_dat_i_0_6"  iostandard="LVCMOS18" loc="W14"/>
+    <pin index="39" name="adc_dat_i_0_7"  iostandard="LVCMOS18" loc="Y14"/>
+    <pin index="40" name="adc_dat_i_0_8"  iostandard="LVCMOS18" loc="W13"/>
+    <pin index="41" name="adc_dat_i_0_9"  iostandard="LVCMOS18" loc="V12"/>
+    <pin index="42" name="adc_dat_i_0_10" iostandard="LVCMOS18" loc="V13"/>
+    <pin index="43" name="adc_dat_i_0_11" iostandard="LVCMOS18" loc="T14"/>
+    <pin index="44" name="adc_dat_i_0_12" iostandard="LVCMOS18" loc="T15"/>
+    <pin index="45" name="adc_dat_i_0_13" iostandard="LVCMOS18" loc="V15"/>
+    <pin index="46" name="adc_dat_i_0_14" iostandard="LVCMOS18" loc="T16"/>
+    <pin index="47" name="adc_dat_i_0_15" iostandard="LVCMOS18" loc="V16"/>
 
-    <pin index="48" name="adc_dat_i[1][0]"  iostandard="LVCMOS18" loc="T17"/>
-    <pin index="49" name="adc_dat_i[1][1]"  iostandard="LVCMOS18" loc="R16"/>
-    <pin index="50" name="adc_dat_i[1][2]"  iostandard="LVCMOS18" loc="R18"/>
-    <pin index="51" name="adc_dat_i[1][3]"  iostandard="LVCMOS18" loc="P16"/>
-    <pin index="52" name="adc_dat_i[1][4]"  iostandard="LVCMOS18" loc="P18"/>
-    <pin index="53" name="adc_dat_i[1][5]"  iostandard="LVCMOS18" loc="N17"/>
-    <pin index="54" name="adc_dat_i[1][6]"  iostandard="LVCMOS18" loc="R19"/>
-    <pin index="55" name="adc_dat_i[1][7]"  iostandard="LVCMOS18" loc="T20"/>
-    <pin index="56" name="adc_dat_i[1][8]"  iostandard="LVCMOS18" loc="T19"/>
-    <pin index="57" name="adc_dat_i[1][9]"  iostandard="LVCMOS18" loc="U20"/>
-    <pin index="58" name="adc_dat_i[1][10]" iostandard="LVCMOS18" loc="V20"/>
-    <pin index="59" name="adc_dat_i[1][11]" iostandard="LVCMOS18" loc="W20"/>
-    <pin index="60" name="adc_dat_i[1][12]" iostandard="LVCMOS18" loc="W19"/>
-    <pin index="61" name="adc_dat_i[1][13]" iostandard="LVCMOS18" loc="Y19"/>
-    <pin index="62" name="adc_dat_i[1][14]" iostandard="LVCMOS18" loc="W18"/>
-    <pin index="63" name="adc_dat_i[1][15]" iostandard="LVCMOS18" loc="Y18"/>
+    <pin index="48" name="adc_dat_i_1_0"  iostandard="LVCMOS18" loc="T17"/>
+    <pin index="49" name="adc_dat_i_1_1"  iostandard="LVCMOS18" loc="R16"/>
+    <pin index="50" name="adc_dat_i_1_2"  iostandard="LVCMOS18" loc="R18"/>
+    <pin index="51" name="adc_dat_i_1_3"  iostandard="LVCMOS18" loc="P16"/>
+    <pin index="52" name="adc_dat_i_1_4"  iostandard="LVCMOS18" loc="P18"/>
+    <pin index="53" name="adc_dat_i_1_5"  iostandard="LVCMOS18" loc="N17"/>
+    <pin index="54" name="adc_dat_i_1_6"  iostandard="LVCMOS18" loc="R19"/>
+    <pin index="55" name="adc_dat_i_1_7"  iostandard="LVCMOS18" loc="T20"/>
+    <pin index="56" name="adc_dat_i_1_8"  iostandard="LVCMOS18" loc="T19"/>
+    <pin index="57" name="adc_dat_i_1_9"  iostandard="LVCMOS18" loc="U20"/>
+    <pin index="58" name="adc_dat_i_1_10" iostandard="LVCMOS18" loc="V20"/>
+    <pin index="59" name="adc_dat_i_1_11" iostandard="LVCMOS18" loc="W20"/>
+    <pin index="60" name="adc_dat_i_1_12" iostandard="LVCMOS18" loc="W19"/>
+    <pin index="61" name="adc_dat_i_1_13" iostandard="LVCMOS18" loc="Y19"/>
+    <pin index="62" name="adc_dat_i_1_14" iostandard="LVCMOS18" loc="W18"/>
+    <pin index="63" name="adc_dat_i_1_15" iostandard="LVCMOS18" loc="Y18"/>
 
-    <pin index="64" name="adc_clk_i[0]" iostandard="DIFF_HSTL_I_18" loc="U19"/>
-    <pin index="65" name="adc_clk_i[1]" iostandard="DIFF_HSTL_I_18" loc="U18"/>
+    <pin index="64" name="adc_clk_i_0" iostandard="DIFF_HSTL_I_18" loc="U19"/>
+    <pin index="65" name="adc_clk_i_1" iostandard="DIFF_HSTL_I_18" loc="U18"/>
 
-    <pin index="66" name="adc_clk_o[0]" iostandard="LVCMOS18" loc="N20"/>
-    <pin index="67" name="adc_clk_o[1]" iostandard="LVCMOS18" loc="P20"/>
+    <pin index="66" name="adc_clk_o_0" iostandard="LVCMOS18" loc="N20"/>
+    <pin index="67" name="adc_clk_o_1" iostandard="LVCMOS18" loc="P20"/>
     <pin index="67" name="adc_cdcs_o" iostandard="LVCMOS18" loc="V18"/>
 
   </pins>
diff --git a/HDL/boards/stemlab_125_14/ocra_config.json b/HDL/boards/stemlab_125_14/ocra_config.json
index e491552d..6afb074b 100644
--- a/HDL/boards/stemlab_125_14/ocra_config.json
+++ b/HDL/boards/stemlab_125_14/ocra_config.json
@@ -3,6 +3,6 @@
         "part": "xc7z010clg400-1",
         "proc": "ps7_cortexa9_0",
 	"board_part": "redpitaya.com:stemlab_125_14:part0:1.0",
-        "projects": ["ocra_mri", "shim_controller", "base_pl"]
+        "projects": ["ocra_mri", "shim_controller", "base_pl","base_pl_new"]
     }
 }
diff --git a/HDL/boards/stemlab_125_14/ports.tcl b/HDL/boards/stemlab_125_14/ports.tcl
index 5823941c..fbee07e5 100644
--- a/HDL/boards/stemlab_125_14/ports.tcl
+++ b/HDL/boards/stemlab_125_14/ports.tcl
@@ -26,17 +26,16 @@ create_bd_port -dir O dac_wrt_o
 create_bd_port -dir O -from 3 -to 0 dac_pwm_o
 
 ### XADC
-
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
 
 ### Expansion connector
 
-create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io
-create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
+create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
+create_bd_port -dir O -from 7 -to 0 exp_n_tri_io
 
 ### LED
 
diff --git a/HDL/boards/stemlab_125_14/ps_base_pl_new.xml b/HDL/boards/stemlab_125_14/ps_base_pl_new.xml
new file mode 100644
index 00000000..33a9fc8d
--- /dev/null
+++ b/HDL/boards/stemlab_125_14/ps_base_pl_new.xml
@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE project PUBLIC "project" "project.dtd" >
+<project version="1.0" >
+  <description >
+  </description>
+  <Projinfo Part="xc7z010clg400-1" DeviceSize="xc7z010" Package="clg400" Speed="-1" />
+  <set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
+  <set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
+  <set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
+  <set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::GPIO::MIO_GPIO::ENABLE" value="1" />
+  <set param="PCW::GPIO::EMIO_GPIO::ENABLE" value="1" />
+  <set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::I2C0::I2C0::IO" value="MIO 50 .. 51" />
+  <set param="PCW::I2C1::PERIPHERAL::ENABLE" value="0" />
+  <set param="PCW::UART0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::UART0::UART0::IO" value="MIO 14 .. 15" />
+  <set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::UART1::UART1::IO" value="MIO 8 .. 9" />
+  <set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::USB0::RESET::ENABLE" value="1" />
+  <set param="PCW::USB0::RESET::IO" value="MIO 48" />
+  <set param="PCW::USB1::PERIPHERAL::ENABLE" value="0" />
+  <set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::QSPI::GRP_SS1::ENABLE" value="0" />
+  <set param="PCW::QSPI::GRP_FBCLK::ENABLE" value="0" />
+  <set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_CD::IO" value="MIO 46" />
+  <set param="PCW::SD0::GRP_WP::IO" value="MIO 47" />
+  <set param="PCW::SPI0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SPI1::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SPI1::SPI1::IO" value="MIO 10 .. 15" />
+  <set param="PCW::TTC0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::FPGA0::PERIPHERAL::FREQMHZ" value="143" />
+  <set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="100" />
+  <set param="PCW::QSPI::PERIPHERAL::FREQMHZ" value="125" />
+  <set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="1000 Mbps" />
+  <set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z010clg400-1" />
+  <set param="PCW::PRESET::FPGA::SPEED" value="-1" />
+  <set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 3.3V" />
+  <set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 2.5V" />
+  <set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" />
+  <set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" />
+  <set param="PCW::UIPARAM::DDR::PARTNO" value="MT41J256M16 RE-125" />
+  <set param="PCW::UIPARAM::DDR::BUS_WIDTH" value="16 Bit" />
+  <set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="16 Bits" />
+  <set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="4096 MBits" />
+  <set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" />
+  <set param="PCW::UIPARAM::DDR::ROW_ADDR_COUNT" value="15" />
+  <set param="PCW::UIPARAM::DDR::CWL" value="6" />
+  <set param="PCW::UIPARAM::DDR::T_RC" value="48.91" />
+  <set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="35.0" />
+  <set param="PCW::UIPARAM::DDR::T_FAW" value="40.0" />
+  <set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[0]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[8]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[9]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[16]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[16]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[16]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[17]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[17]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[17]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[18]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[18]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[18]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[19]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[19]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[19]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[20]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[20]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[20]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[21]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[21]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[21]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[22]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[22]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[22]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[23]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[23]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[23]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[24]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[24]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[24]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[25]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[25]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[25]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[26]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[26]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[26]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[27]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[27]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[27]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[28]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[29]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[30]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[31]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[32]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[33]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[34]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[35]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[36]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[37]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[38]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[39]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[52]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[53]::DIRECTION" value="inout" />
+</project>
diff --git a/HDL/boards/stemlab_125_14_4in/brd/1.0/board.xml b/HDL/boards/stemlab_125_14_4in/brd/1.0/board.xml
new file mode 100644
index 00000000..1b869b60
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/brd/1.0/board.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.0" vendor="redpitaya.com" name="stemlab_125_14_4in" display_name="Red Pitaya STEMLab-125.14 4-input" url="http://redpitaya.com" preset_file="preset.xml">
+    <images>
+    <image name="redpitaya.jpg" display_name="Stemlab 125.14 4-input" sub_type="board">
+      <description>STEMLab-125.14 4-input Board File</description>
+    </image>
+  </images>
+  <file_version>1.0</file_version>
+  <description>Red Pitaya STEMLab-125.14 4-input</description>
+  <compatible_board_revisions>
+    <revision id="0">1.0</revision>
+  </compatible_board_revisions>
+  <components>
+    <component name="part0" display_name="STEMLab Development Platform" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://redpitaya.com">
+      <description>FPGA part on the board</description>
+      <interfaces>
+        <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+        </interface>
+      </interfaces>
+    </component>
+    <component name="ps7_fixedio" display_name="PS7 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+  </components>
+
+  <jtag_chains>
+    <jtag_chain name="chain1">
+      <position name="0" component="part0"/>
+    </jtag_chain>
+  </jtag_chains>
+</board>
diff --git a/HDL/boards/stemlab_125_14_4in/brd/1.0/part0_pins.xml b/HDL/boards/stemlab_125_14_4in/brd/1.0/part0_pins.xml
new file mode 100644
index 00000000..5f20aba7
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/brd/1.0/part0_pins.xml
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<part_info part_name="xc7z020clg400-1">
+  <pins>
+
+    <pin index="0"  name="led_o_0" iostandard="LVCMOS33" loc="F16"/>
+    <pin index="1"  name="led_o_1" iostandard="LVCMOS33" loc="F17"/>
+    <pin index="2"  name="led_o_2" iostandard="LVCMOS33" loc="G15"/>
+    <pin index="3"  name="led_o_3" iostandard="LVCMOS33" loc="H15"/>
+    <pin index="4"  name="led_o_4" iostandard="LVCMOS33" loc="K14"/>
+    <pin index="5"  name="led_o_5" iostandard="LVCMOS33" loc="G14"/>
+    <pin index="6"  name="led_o_6" iostandard="LVCMOS33" loc="J15"/>
+    <pin index="7"  name="led_o_7" iostandard="LVCMOS33" loc="J14"/>
+
+    <pin index="8"  name="exp_p_io_0" iostandard="LVCMOS33" loc="G17"/>
+    <pin index="9"  name="exp_p_io_1" iostandard="LVCMOS33" loc="H16"/>
+    <pin index="10" name="exp_p_io_2" iostandard="LVCMOS33" loc="J18"/>
+    <pin index="11" name="exp_p_io_3" iostandard="LVCMOS33" loc="K17"/>
+    <pin index="12" name="exp_p_io_4" iostandard="LVCMOS33" loc="L14"/>
+    <pin index="13" name="exp_p_io_5" iostandard="LVCMOS33" loc="L16"/>
+    <pin index="14" name="exp_p_io_6" iostandard="LVCMOS33" loc="K16"/>
+    <pin index="15" name="exp_p_io_7" iostandard="LVCMOS33" loc="M14"/>
+
+    <pin index="16" name="exp_n_io_0" iostandard="LVCMOS33" loc="G18"/>
+    <pin index="17" name="exp_n_io_1" iostandard="LVCMOS33" loc="H17"/>
+    <pin index="18" name="exp_n_io_2" iostandard="LVCMOS33" loc="H18"/>
+    <pin index="29" name="exp_n_io_3" iostandard="LVCMOS33" loc="K18"/>
+    <pin index="20" name="exp_n_io_4" iostandard="LVCMOS33" loc="L15"/>
+    <pin index="21" name="exp_n_io_5" iostandard="LVCMOS33" loc="L17"/>
+    <pin index="22" name="exp_n_io_6" iostandard="LVCMOS33" loc="J16"/>
+    <pin index="23" name="exp_n_io_7" iostandard="LVCMOS33" loc="M15"/>
+
+    <pin index="24" name="daisy_p_i_0" iostandard="DIFF_HSTL_I_18" loc="P14"/>
+    <pin index="25" name="daisy_n_i_0" iostandard="DIFF_HSTL_I_18" loc="R14"/>
+    <pin index="26" name="daisy_p_i_1" iostandard="DIFF_HSTL_I_18" loc="N18"/>
+    <pin index="27" name="daisy_n_i_1" iostandard="DIFF_HSTL_I_18" loc="P19"/>
+    <pin index="28" name="daisy_p_o_0" iostandard="DIFF_HSTL_I_18" loc="T12"/>
+    <pin index="29" name="daisy_n_o_0" iostandard="DIFF_HSTL_I_18" loc="U12"/>
+    <pin index="30" name="daisy_p_o_1" iostandard="DIFF_HSTL_I_18" loc="U14"/>
+    <pin index="31" name="daisy_n_o_1" iostandard="DIFF_HSTL_I_18" loc="U15"/>
+
+    <pin index="32" name="adc_dat_i_0_0"  iostandard="LVCMOS18" loc="V17"/>
+    <pin index="33" name="adc_dat_i_0_1"  iostandard="LVCMOS18" loc="U17"/>
+    <pin index="34" name="adc_dat_i_0_2"  iostandard="LVCMOS18" loc="Y17"/>
+    <pin index="35" name="adc_dat_i_0_3"  iostandard="LVCMOS18" loc="W16"/>
+    <pin index="36" name="adc_dat_i_0_4"  iostandard="LVCMOS18" loc="Y16"/>
+    <pin index="37" name="adc_dat_i_0_5"  iostandard="LVCMOS18" loc="W15"/>
+    <pin index="38" name="adc_dat_i_0_6"  iostandard="LVCMOS18" loc="W14"/>
+    <pin index="39" name="adc_dat_i_0_7"  iostandard="LVCMOS18" loc="Y14"/>
+    <pin index="40" name="adc_dat_i_0_8"  iostandard="LVCMOS18" loc="W13"/>
+    <pin index="41" name="adc_dat_i_0_9"  iostandard="LVCMOS18" loc="V12"/>
+    <pin index="42" name="adc_dat_i_0_10" iostandard="LVCMOS18" loc="V13"/>
+    <pin index="43" name="adc_dat_i_0_11" iostandard="LVCMOS18" loc="T14"/>
+    <pin index="44" name="adc_dat_i_0_12" iostandard="LVCMOS18" loc="T15"/>
+    <pin index="45" name="adc_dat_i_0_13" iostandard="LVCMOS18" loc="V15"/>
+    <pin index="46" name="adc_dat_i_0_14" iostandard="LVCMOS18" loc="T16"/>
+    <pin index="47" name="adc_dat_i_0_15" iostandard="LVCMOS18" loc="V16"/>
+
+    <pin index="48" name="adc_dat_i_1_0"  iostandard="LVCMOS18" loc="T17"/>
+    <pin index="49" name="adc_dat_i_1_1"  iostandard="LVCMOS18" loc="R16"/>
+    <pin index="50" name="adc_dat_i_1_2"  iostandard="LVCMOS18" loc="R18"/>
+    <pin index="51" name="adc_dat_i_1_3"  iostandard="LVCMOS18" loc="P16"/>
+    <pin index="52" name="adc_dat_i_1_4"  iostandard="LVCMOS18" loc="P18"/>
+    <pin index="53" name="adc_dat_i_1_5"  iostandard="LVCMOS18" loc="N17"/>
+    <pin index="54" name="adc_dat_i_1_6"  iostandard="LVCMOS18" loc="R19"/>
+    <pin index="55" name="adc_dat_i_1_7"  iostandard="LVCMOS18" loc="T20"/>
+    <pin index="56" name="adc_dat_i_1_8"  iostandard="LVCMOS18" loc="T19"/>
+    <pin index="57" name="adc_dat_i_1_9"  iostandard="LVCMOS18" loc="U20"/>
+    <pin index="58" name="adc_dat_i_1_10" iostandard="LVCMOS18" loc="V20"/>
+    <pin index="59" name="adc_dat_i_1_11" iostandard="LVCMOS18" loc="W20"/>
+    <pin index="60" name="adc_dat_i_1_12" iostandard="LVCMOS18" loc="W19"/>
+    <pin index="61" name="adc_dat_i_1_13" iostandard="LVCMOS18" loc="Y19"/>
+    <pin index="62" name="adc_dat_i_1_14" iostandard="LVCMOS18" loc="W18"/>
+    <pin index="63" name="adc_dat_i_1_15" iostandard="LVCMOS18" loc="Y18"/>
+
+    <pin index="64" name="adc_clk_i_0" iostandard="DIFF_HSTL_I_18" loc="U19"/>
+    <pin index="65" name="adc_clk_i_1" iostandard="DIFF_HSTL_I_18" loc="U18"/>
+
+    <pin index="66" name="adc_clk_o_0" iostandard="LVCMOS18" loc="N20"/>
+    <pin index="67" name="adc_clk_o_1" iostandard="LVCMOS18" loc="P20"/>
+    <pin index="67" name="adc_cdcs_o" iostandard="LVCMOS18" loc="V18"/>
+
+    
+  </pins>
+</part_info>
diff --git a/HDL/boards/stemlab_125_14_4in/brd/1.0/preset.xml b/HDL/boards/stemlab_125_14_4in/brd/1.0/preset.xml
new file mode 100644
index 00000000..07481caf
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/brd/1.0/preset.xml
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ps7_preset">
+    <ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
+      <user_parameters>
+	<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
+	<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_I2C0_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_I2C0_I2C0_IO" value="MIO 50 .. 51"/>
+	<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" value="0"/>
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
+	<user_parameter name="CONFIG.PCW_UART1_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_UART1_UART1_IO" value="MIO 8 .. 9"/>
+	<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 48"/>
+	<user_parameter name="CONFIG.PCW_USB1_PERIPHERAL_ENABLE" value="0"/>
+	<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
+	<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
+	<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 46"/>
+	<user_parameter name="CONFIG.PCW_SD0_GRP_WP_IO" value="MIO 47"/>
+	<user_parameter name="CONFIG.PCW_SPI0_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_SPI1_PERIPHERAL_ENABLE" value="1"/>
+	<user_parameter name="CONFIG.PCW_SPI1_SPI1_IO" value="MIO 10 .. 15"/>
+	<user_parameter name="CONFIG.PCW_TTC0_PERIPHERAL_ENABLE" value="1"/>
+	
+	<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 2.5V"/>
+		<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
+	<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="in"/>
+	<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
+	<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
+        <user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
+        <user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
+        <user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
+        <user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
+        <user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
+        <user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
+        <user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
+        <user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
+        <user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
+        <user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
+        <user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
+        <user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="disabled"/>
+	<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast"/>
+	<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
+	<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 2.5V"/>
+	<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
+	<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="143"/>
+	<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ" value="100"/>
+	<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="125"/>
+	<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="533.333333"/>
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)"/>
+        <user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41J256M16 RE-125"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.91"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
+	<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
+      </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/HDL/boards/stemlab_125_14_4in/brd/1.0/redpitaya.jpg b/HDL/boards/stemlab_125_14_4in/brd/1.0/redpitaya.jpg
new file mode 100644
index 00000000..e5676cbf
Binary files /dev/null and b/HDL/boards/stemlab_125_14_4in/brd/1.0/redpitaya.jpg differ
diff --git a/HDL/boards/stemlab_125_14_4in/clocks.xdc b/HDL/boards/stemlab_125_14_4in/clocks.xdc
new file mode 100644
index 00000000..d2cfe3fa
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/clocks.xdc
@@ -0,0 +1,2 @@
+set_input_delay -max 1.000 -clock adc_clk_p_i [get_ports adc_dat_a_i[*]]
+set_input_delay -max 1.000 -clock adc_clk_p_i [get_ports adc_dat_b_i[*]]
diff --git a/HDL/boards/stemlab_125_14_4in/ocra_config.json b/HDL/boards/stemlab_125_14_4in/ocra_config.json
new file mode 100644
index 00000000..c3b762ae
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/ocra_config.json
@@ -0,0 +1,8 @@
+{
+    "HDL": {
+        "part": "xc7z020clg400-1",
+        "proc": "ps7_cortexa9_0",
+	"board_part": "redpitaya.com:stemlab_125_14_4in:part0:1.0",
+        "projects": ["ocra_mri", "base_pl"]
+    }
+}
diff --git a/HDL/boards/stemlab_125_14_4in/ports.tcl b/HDL/boards/stemlab_125_14_4in/ports.tcl
new file mode 100644
index 00000000..9a7319b7
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/ports.tcl
@@ -0,0 +1,43 @@
+
+### ADC
+
+create_bd_port -dir I -from 15 -to 0 adc_dat_a_i
+create_bd_port -dir I -from 15 -to 0 adc_dat_b_i
+
+create_bd_port -dir I adc_clk_p_i
+create_bd_port -dir I adc_clk_n_i
+
+create_bd_port -dir O adc_enc_p_o
+create_bd_port -dir O adc_enc_n_o
+
+create_bd_port -dir O adc_csn_o
+
+### DAC
+
+create_bd_port -dir O -from 13 -to 0 dac_dat_o
+
+create_bd_port -dir O dac_clk_o
+create_bd_port -dir O dac_rst_o
+create_bd_port -dir O dac_sel_o
+create_bd_port -dir O dac_wrt_o
+
+### PWM
+
+create_bd_port -dir O -from 3 -to 0 dac_pwm_o
+
+### XADC
+
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
+
+### Expansion connector
+
+create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io
+create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
+
+### LED
+
+create_bd_port -dir O -from 7 -to 0 led_o
diff --git a/HDL/boards/stemlab_125_14_4in/ports.xdc b/HDL/boards/stemlab_125_14_4in/ports.xdc
new file mode 100644
index 00000000..8bdea47d
--- /dev/null
+++ b/HDL/boards/stemlab_125_14_4in/ports.xdc
@@ -0,0 +1,225 @@
+
+# set_property CFGBVS VCCO [current_design]
+# set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+### ADC
+
+# data
+
+set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_a_i[*]}]
+set_property IOB TRUE [get_ports {adc_dat_a_i[*]}]
+
+set_property PACKAGE_PIN V17 [get_ports {adc_dat_a_i[0]}]
+set_property PACKAGE_PIN_U17 [get_ports {adc_dat_a_i[1]}]
+set_property PACKAGE_PIN Y17 [get_ports {adc_dat_a_i[2]}]
+set_property PACKAGE_PIN W16 [get_ports {adc_dat_a_i[3]}]
+set_property PACKAGE_PIN Y16 [get_ports {adc_dat_a_i[4]}]
+set_property PACKAGE_PIN W15 [get_ports {adc_dat_a_i[5]}]
+set_property PACKAGE_PIN W14 [get_ports {adc_dat_a_i[6]}]
+set_property PACKAGE_PIN Y14 [get_ports {adc_dat_a_i[7]}]
+set_property PACKAGE_PIN W13 [get_ports {adc_dat_a_i[8]}]
+set_property PACKAGE_PIN V12 [get_ports {adc_dat_a_i[9]}]
+set_property PACKAGE_PIN V13 [get_ports {adc_dat_a_i[10]}]
+set_property PACKAGE_PIN T14 [get_ports {adc_dat_a_i[11]}]
+set_property PACKAGE_PIN T15 [get_ports {adc_dat_a_i[12]}]
+set_property PACKAGE_PIN V15 [get_ports {adc_dat_a_i[13]}]
+set_property PACKAGE_PIN T16 [get_ports {adc_dat_a_i[14]}]
+set_property PACKAGE_PIN V16 [get_ports {adc_dat_a_i[15]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_b_i[*]}]
+set_property IOB TRUE [get_ports {adc_dat_b_i[*]}]
+
+set_property PACKAGE_PIN T17 [get_ports {adc_dat_b_i[0]}]
+set_property PACKAGE_PIN R16 [get_ports {adc_dat_b_i[1]}]
+set_property PACKAGE_PIN R18 [get_ports {adc_dat_b_i[2]}]
+set_property PACKAGE_PIN P16 [get_ports {adc_dat_b_i[3]}]
+set_property PACKAGE_PIN P18 [get_ports {adc_dat_b_i[4]}]
+set_property PACKAGE_PIN N17 [get_ports {adc_dat_b_i[5]}]
+set_property PACKAGE_PIN R19 [get_ports {adc_dat_b_i[6]}]
+set_property PACKAGE_PIN T20 [get_ports {adc_dat_b_i[7]}]
+set_property PACKAGE_PIN T19 [get_ports {adc_dat_b_i[8]}]
+set_property PACKAGE_PIN U20 [get_ports {adc_dat_b_i[9]}]
+set_property PACKAGE_PIN V20 [get_ports {adc_dat_b_i[10]}]
+set_property PACKAGE_PIN W20 [get_ports {adc_dat_b_i[11]}]
+set_property PACKAGE_PIN W19 [get_ports {adc_dat_b_i[12]}]
+set_property PACKAGE_PIN Y19 [get_ports {adc_dat_b_i[13]}]
+set_property PACKAGE_PIN W18 [get_ports {adc_dat_b_i[14]}]
+set_property PACKAGE_PIN Y18 [get_ports {adc_dat_b_i[15]}]
+
+# clock input
+
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_p_i]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_n_i]
+set_property PACKAGE_PIN U18 [get_ports adc_clk_p_i]
+set_property PACKAGE_PIN U19 [get_ports adc_clk_n_i]
+
+# clock output
+
+set_property IOSTANDARD LVCMOS18 [get_ports adc_enc_p_o]
+set_property IOSTANDARD LVCMOS18 [get_ports adc_enc_n_o]
+
+set_property SLEW FAST [get_ports adc_enc_p_o]
+set_property SLEW FAST [get_ports adc_enc_n_o]
+
+set_property DRIVE 8 [get_ports adc_enc_p_o]
+set_property DRIVE 8 [get_ports adc_enc_n_o]
+
+set_property PACKAGE_PIN N20 [get_ports adc_enc_p_o]
+set_property PACKAGE_PIN P20 [get_ports adc_enc_n_o]
+
+# clock duty cycle stabilizer (CSn)
+
+set_property IOSTANDARD LVCMOS18 [get_ports adc_csn_o]
+set_property PACKAGE_PIN V18 [get_ports adc_csn_o]
+set_property SLEW FAST [get_ports adc_csn_o]
+set_property DRIVE 8 [get_ports adc_csn_o]
+
+### DAC
+
+# data
+
+set_property IOSTANDARD LVCMOS33 [get_ports {dac_dat_o[*]}]
+set_property SLEW SLOW [get_ports {dac_dat_o[*]}]
+set_property DRIVE 4 [get_ports {dac_dat_o[*]}]
+# set_property IOB TRUE [get_ports {dac_dat_o[*]}]
+
+set_property PACKAGE_PIN M19 [get_ports {dac_dat_o[0]}]
+set_property PACKAGE_PIN M20 [get_ports {dac_dat_o[1]}]
+set_property PACKAGE_PIN L19 [get_ports {dac_dat_o[2]}]
+set_property PACKAGE_PIN L20 [get_ports {dac_dat_o[3]}]
+set_property PACKAGE_PIN K19 [get_ports {dac_dat_o[4]}]
+set_property PACKAGE_PIN J19 [get_ports {dac_dat_o[5]}]
+set_property PACKAGE_PIN J20 [get_ports {dac_dat_o[6]}]
+set_property PACKAGE_PIN H20 [get_ports {dac_dat_o[7]}]
+set_property PACKAGE_PIN G19 [get_ports {dac_dat_o[8]}]
+set_property PACKAGE_PIN G20 [get_ports {dac_dat_o[9]}]
+set_property PACKAGE_PIN F19 [get_ports {dac_dat_o[10]}]
+set_property PACKAGE_PIN F20 [get_ports {dac_dat_o[11]}]
+set_property PACKAGE_PIN D20 [get_ports {dac_dat_o[12]}]
+set_property PACKAGE_PIN D19 [get_ports {dac_dat_o[13]}]
+
+# control
+
+set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o]
+set_property SLEW FAST [get_ports dac_*_o]
+set_property DRIVE 8 [get_ports dac_*_o]
+# set_property IOB TRUE [get_ports {dac_*_o}]
+
+set_property PACKAGE_PIN M17 [get_ports dac_wrt_o]
+set_property PACKAGE_PIN N16 [get_ports dac_sel_o]
+set_property PACKAGE_PIN M18 [get_ports dac_clk_o]
+set_property PACKAGE_PIN N15 [get_ports dac_rst_o]
+
+### PWM
+
+set_property IOSTANDARD LVCMOS18 [get_ports {dac_pwm_o[*]}]
+set_property SLEW FAST [get_ports {dac_pwm_o[*]}]
+set_property DRIVE 12 [get_ports {dac_pwm_o[*]}]
+# set_property IOB TRUE [get_ports {dac_pwm_o[*]}]
+
+set_property PACKAGE_PIN T10 [get_ports {dac_pwm_o[0]}]
+set_property PACKAGE_PIN T11 [get_ports {dac_pwm_o[1]}]
+set_property PACKAGE_PIN P15 [get_ports {dac_pwm_o[2]}]
+set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}]
+
+### XADC
+
+set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_n]
+
+set_property PACKAGE_PIN K9  [get_ports Vp_Vn_v_p]
+set_property PACKAGE_PIN L10 [get_ports Vp_Vn_v_n]
+set_property PACKAGE_PIN C20 [get_ports Vaux0_v_p]
+set_property PACKAGE_PIN B20 [get_ports Vaux0_v_n]
+set_property PACKAGE_PIN E17 [get_ports Vaux1_v_p]
+set_property PACKAGE_PIN D18 [get_ports Vaux1_v_n]
+set_property PACKAGE_PIN B19 [get_ports Vaux8_v_p]
+set_property PACKAGE_PIN A20 [get_ports Vaux8_v_n]
+set_property PACKAGE_PIN E18 [get_ports Vaux9_v_p]
+set_property PACKAGE_PIN E19 [get_ports Vaux9_v_n]
+
+### Expansion connector
+
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_tri_io[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_tri_io[*]}]
+set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
+set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
+set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
+set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
+set_property PULLTYPE PULLUP [get_ports {exp_p_tri_io[*]}]
+set_property PULLTYPE PULLUP [get_ports {exp_n_tri_io[*]}]
+
+set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
+set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
+set_property PACKAGE_PIN H16 [get_ports {exp_p_tri_io[1]}]
+set_property PACKAGE_PIN H17 [get_ports {exp_n_tri_io[1]}]
+set_property PACKAGE_PIN J18 [get_ports {exp_p_tri_io[2]}]
+set_property PACKAGE_PIN H18 [get_ports {exp_n_tri_io[2]}]
+set_property PACKAGE_PIN K17 [get_ports {exp_p_tri_io[3]}]
+set_property PACKAGE_PIN K18 [get_ports {exp_n_tri_io[3]}]
+set_property PACKAGE_PIN L14 [get_ports {exp_p_tri_io[4]}]
+set_property PACKAGE_PIN L15 [get_ports {exp_n_tri_io[4]}]
+set_property PACKAGE_PIN L16 [get_ports {exp_p_tri_io[5]}]
+set_property PACKAGE_PIN L17 [get_ports {exp_n_tri_io[5]}]
+set_property PACKAGE_PIN K16 [get_ports {exp_p_tri_io[6]}]
+set_property PACKAGE_PIN J16 [get_ports {exp_n_tri_io[6]}]
+set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]
+set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports exp_p_trg]
+set_property SLEW FAST [get_ports exp_p_trg]
+set_property DRIVE 8 [get_ports exp_p_trg]
+
+set_property PACKAGE_PIN M14 [get_ports exp_p_trg]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_alex[*]}]
+set_property SLEW FAST [get_ports {exp_n_alex[*]}]
+set_property DRIVE 8 [get_ports {exp_n_alex[*]}]
+
+set_property PACKAGE_PIN L15 [get_ports {exp_n_alex[0]}]
+set_property PACKAGE_PIN L17 [get_ports {exp_n_alex[1]}]
+set_property PACKAGE_PIN J16 [get_ports {exp_n_alex[2]}]
+set_property PACKAGE_PIN M15 [get_ports {exp_n_alex[3]}]
+
+### SATA connector
+
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_o[*]]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_o[*]]
+
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_i[*]]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_i[*]]
+
+set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
+set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
+
+set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
+set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
+
+set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
+set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
+
+set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
+set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
+
+### LED
+
+set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}]
+set_property SLEW SLOW [get_ports {led_o[*]}]
+set_property DRIVE 8 [get_ports {led_o[*]}]
+
+set_property PACKAGE_PIN F16 [get_ports {led_o[0]}]
+set_property PACKAGE_PIN F17 [get_ports {led_o[1]}]
+set_property PACKAGE_PIN G15 [get_ports {led_o[2]}]
+set_property PACKAGE_PIN H15 [get_ports {led_o[3]}]
+set_property PACKAGE_PIN K14 [get_ports {led_o[4]}]
+set_property PACKAGE_PIN G14 [get_ports {led_o[5]}]
+set_property PACKAGE_PIN J15 [get_ports {led_o[6]}]
+set_property PACKAGE_PIN J14 [get_ports {led_o[7]}]
diff --git a/HDL/boards/zub1cg/brd/1.2/LICENSE b/HDL/boards/zub1cg/brd/1.2/LICENSE
new file mode 100644
index 00000000..64d3aace
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2021, Avnet Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/HDL/boards/zub1cg/brd/1.2/ZUBoard_temp.xdc b/HDL/boards/zub1cg/brd/1.2/ZUBoard_temp.xdc
new file mode 100644
index 00000000..0225a080
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/ZUBoard_temp.xdc
@@ -0,0 +1,5 @@
+set_property PACKAGE_PIN G7 [get_ports {click_spi_pl_ss_io[0]}]
+set_property PACKAGE_PIN G5 [get_ports {click_spi_pl_ss_io[1]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {click_spi_pl_ss_io[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {click_spi_pl_ss_io[0]}]
\ No newline at end of file
diff --git a/HDL/boards/zub1cg/brd/1.2/board.xml b/HDL/boards/zub1cg/brd/1.2/board.xml
new file mode 100644
index 00000000..2c62c351
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/board.xml
@@ -0,0 +1,580 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--<!DOCTYPE board SYSTEM "C:/Xilinx/Vivado/2021.2/data/boards/board_schemas/current/board.dtd">-->
+<!-- -->
+<!--   ** **        **          **  ****      **  **********  ********** ®   
+      **   **        **        **   ** **     **  **              **
+     **     **        **      **    **  **    **  **              **
+    **       **        **    **     **   **   **  *********       **
+   **         **        **  **      **    **  **  **              **
+  **           **        ****       **     ** **  **              **
+ **  .........  **        **        **      ****  **********      **
+    ...........
+                                    Reach Further™
+ Copyright (C) 2022, Avnet Inc - All rights reserved
+ Licensed under the Apache License, Version 2.0 (the "License"). You may
+ not use this file except in compliance with the License. A copy of the
+ License is located at
+     http://www.apache.org/licenses/LICENSE-2.0
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ License for the specific language governing permissions and limitations
+ under the License. -->
+ 
+<board 
+   schema_version="2.2" 
+   vendor="Avnet-tria" 
+   name="ZUBoard_1CG" 
+   display_name="Avnet-Tria ZUBoard 1CG Development Board" 
+   url="http://avnet.me/ZUBoard-1CG" 
+   preset_file="preset.xml">
+
+   <images>
+      <image 
+         name="zub1cg_top.png" 
+         display_name="ZUBoard 1CG Development Board" 
+         sub_type="board">
+         <description>ZUBoard 1CG DK Image</description>
+      </image>
+   </images>
+
+   <compatible_board_revisions>
+      <revision id="0">Rev 1</revision>
+   </compatible_board_revisions>
+
+   <file_version>1.2</file_version>
+
+   <description>ZUBoard 1CG Development Board</description>
+
+   <parameters>
+   </parameters>
+
+   <jumpers>
+   </jumpers>
+     
+   <data_properties>
+      <data_property_group name="OPERATING_CONDITIONS">
+        <data_property_group name="SUPPLY_CURRENT_BUDGET">
+          <data_property name="VCCINT"     value="3"/>
+		  <!--
+          <data_property name="VCCINT_IO"  value="7.38"/>
+          <data_property name="VCCBRAM"    value="1.62"/>
+          <data_property name="VCCAUX"     value="1.19"/>
+          <data_property name="VCCAUX_IO"  value="0.056"/>
+          <data_property name="VCCO18"     value="0.014"/>
+          <data_property name="VCC_IO_HBM" value="3.84"/>
+          <data_property name="VCC_HBM"    value="4.16"/>
+          <data_property name="VCCAUX_HBM" value="0.2"/>
+          <data_property name="MGTYVCCAUX" value="0.144"/>
+          <data_property name="MGTYAVCC"   value="1.4"/>
+          <data_property name="MGTYAVTT"   value="3.6"/>
+          <data_property name="VCCADC"     value="0.02"/>
+		  -->
+        </data_property_group>
+        <data_property name="THETAJA"             value="0.75"/>
+        <data_property name="AMBIENT_TEMP"        value="25"/>
+        <data_property name="DESIGN_POWER_BUDGET" value="45"/>
+        <data_property name="HEATSINK"            value="medium"/>
+        <data_property name="BOARD_TEMP"          value="40"/>
+        <data_property name="BOARD_LAYERS"        value="8to11"/>
+    </data_property_group>
+  </data_properties>
+
+   <components>   
+
+      <!-- ZU+ MPSoC -->
+      <component name="part0" display_name="ZU+ MPSoC" type="fpga" part_name="xczu1cg-sbva484-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="http://avnet.me/ZUBoard-1CG">
+         <description>Zynq UltraScale+ part on the board</description>
+         <interfaces>
+
+            <!-- ZU+ PS Fixed I/O -->
+            <interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 
+               <preferred_ips>
+                  <preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
+               </preferred_ips>
+            </interface>
+
+            <!-- MikroE Click I2C -->
+             <interface mode="master" name="click_i2c_pl" type="xilinx.com:interface:iic_rtl:1.0" of_component="click_i2c_pl">
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="SCL_I" physical_port="click_i2c_main_scl_i" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SCL_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCL_O" physical_port="click_i2c_main_scl_o" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SCL_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCL_T" physical_port="click_i2c_main_scl_t" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SCL_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_I" physical_port="click_i2c_main_sda_i" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SDA_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_O" physical_port="click_i2c_main_sda_o" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SDA_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_T" physical_port="click_i2c_main_sda_t" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SDA_1V8"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+    
+            <!-- MikroE Click Interrupt -->
+
+            <!-- MikroE Click PWM -->
+
+            <!-- MikroE Click Reset Output from ZU and Input to Click-->
+            <interface mode="master" name="click_reset_pl"   type="xilinx.com:interface:gpio_rtl:1.0" of_component="click_reset_pl"   preset_proc="click_reset_pl_preset">
+            <description>Click Reset</description>
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="TRI_O" physical_port="click_reset_pl_tri_o" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_RST_1V8"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+               
+            <!-- MikroE Click SPI -->
+            <interface mode="master" name="click_spi_pl" type="xilinx.com:interface:spi_rtl:1.0" of_component="click_spi_pl" preset_proc="click_spi_pl_preset">
+              <preferred_ips>
+                  <preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="IO0_I" physical_port="HD_CLICK_MOSI_1V8" dir="in">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_MOSI_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_MOSI_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_MOSI_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="IO1_I" physical_port="HD_CLICK_MISO_1V8" dir="in">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_MISO_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_MISO_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_MISO_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCK_I" physical_port="HD_CLICK_SCK_1V8" dir="in">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SCK_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SCK_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_SCK_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in" left="1" right="0">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_CS0_1V8"/> 
+                    <pin_map port_index="1" component_pin="HD_CLICK_CS1_AN_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out" left="1" right="0">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_CS0_1V8"/> 
+                    <pin_map port_index="1" component_pin="HD_CLICK_CS1_AN_1V8"/> 
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_CLICK_CS0_1V8"/> 
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>      
+
+            <!-- MikroE Click UART -->
+            <interface mode="master" name="click_uart_pl" type="xilinx.com:interface:uart_rtl:1.0" of_component="click_uart_pl">
+              <preferred_ips>
+               <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+              </preferred_ips>
+               <port_maps>
+                 <port_map logical_port="TxD" physical_port="rs232_uart_txd" dir="out">
+                  <pin_maps>
+                     <pin_map port_index="0" component_pin="HD_CLICK_TX_1V8"/>
+                  </pin_maps>
+                 </port_map>
+                 <port_map logical_port="RxD" physical_port="rs232_uart_rxd" dir="in">
+                   <pin_maps>
+                      <pin_map port_index="0" component_pin="HD_CLICK_RX_1V8"/>
+                   </pin_maps>
+                 </port_map>
+               </port_maps>
+            </interface>
+
+            <!-- PUSH BUTTON -->
+            <interface mode="master" name="push_button_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_button_1bit" preset_proc="push_button_1bit_preset">
+              <description>PL Push Button</description>
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="TRI_I" physical_port="push_button_1bit_tri_i" dir="in">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_GPIO_PB1"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+
+            <!-- TRI-COLOR LEDS -->
+            <interface mode="master" name="rgb1_led_3bits"   type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb1_led_3bits"   preset_proc="rgb1_led_3bits_preset">
+            <description>PL RGB LED 1</description>
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="TRI_O" physical_port="rgb1_led_3bits_tri_o" dir="out" left="2" right="0">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_GPIO_RGB1_B"/>
+                    <pin_map port_index="1" component_pin="HD_GPIO_RGB1_G"/>
+                    <pin_map port_index="2" component_pin="HD_GPIO_RGB1_R"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+            <interface mode="master" name="rgb2_led_3bits"   type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb2_led_3bits"   preset_proc="rgb2_led_3bits_preset">
+            <description>PL RGB LED 2</description>
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="TRI_O" physical_port="rgb2_led_3bits_tri_o" dir="out" left="2" right="0">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HP_GPIO_RGB2_B"/>
+                    <pin_map port_index="1" component_pin="HP_GPIO_RGB2_G"/>
+                    <pin_map port_index="2" component_pin="HP_GPIO_RGB2_R"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+
+            <!-- TEMPERATURE SENSOR I2C -->
+             <interface mode="master" name="tempsensor_i2c_pl" type="xilinx.com:interface:iic_rtl:1.0" of_component="tempsensor_i2c_pl">
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="SCL_I" physical_port="TempSensor_i2c_main_scl_i" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_SENSOR_I2C_SCL"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCL_O" physical_port="TempSensor_i2c_main_scl_o" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_SENSOR_I2C_SCL"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCL_T" physical_port="TempSensor_i2c_main_scl_t" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_SENSOR_I2C_SCL"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_I" physical_port="TempSensor_i2c_main_sda_i" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_SENSOR_I2C_SDA"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_O" physical_port="TempSensor_i2c_main_sda_o" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_SENSOR_I2C_SDA"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_T" physical_port="TempSensor_i2c_main_sda_t" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_SENSOR_I2C_SDA"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+
+            <!-- HSIO DNA I2C -->
+            <interface mode="master" name="hsio_dna_i2c_pl" type="xilinx.com:interface:iic_rtl:1.0" of_component="hsio_dna_i2c_pl">
+              <preferred_ips>
+                <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+              </preferred_ips>
+              <port_maps>
+                <port_map logical_port="SCL_I" physical_port="HSIO_DNA_i2c_main_scl_i" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_HSIO_SCL_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCL_O" physical_port="HSIO_DNA_i2c_main_scl_o" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_HSIO_SCL_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SCL_T" physical_port="HSIO_DNA_i2c_main_scl_t" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_HSIO_SCL_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_I" physical_port="HSIO_DNA_i2c_main_sda_i" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_HSIO_SDA_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_O" physical_port="HSIO_DNA_i2c_main_sda_o" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_HSIO_SDA_1V8"/>
+                  </pin_maps>
+                </port_map>
+                <port_map logical_port="SDA_T" physical_port="HSIO_DNA_i2c_main_sda_t" dir="inout">
+                  <pin_maps>
+                    <pin_map port_index="0" component_pin="HD_HSIO_SDA_1V8"/>
+                  </pin_maps>
+                </port_map>
+              </port_maps>
+            </interface>
+            <!-- HSIO STD PL (J6) -->
+            <!-- HSIO TXR2 PL (J1) -->
+            <!-- HSIO TXR2 MIO (J2) -->
+         </interfaces> 
+      </component>
+
+      <!-- ZU+ PS Fixed I/O -->
+      <component name="ps8_fixedio" display_name="PS8 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+
+      <!-- MikroE Click I2C -->
+      <component name="click_i2c_pl" display_name="PL Click I2C" type="chip" sub_type="mux" major_group="Click" part_name="Click" vendor="MikroE">
+        <description>PL Click I2C</description>
+      </component>
+
+      <!-- MikroE Click Interrupt -->
+
+      <!-- MikroE Click PWM -->
+
+      <!-- MikroE Click Reset -->
+      <component name="click_reset_pl" display_name="PL Click Reset" type="chip" sub_type="reset" major_group="Click" part_name="Click" vendor="MikroE">
+        <description>PL Click Reset Input</description>
+      </component>
+
+      <!-- MikroE Click SPI -->
+      <component name="click_spi_pl" display_name="PL Click SPI" type="chip" sub_type="mux" major_group="Click" part_name="Click" vendor="MikroE">
+          <description>PL Click SPI</description>
+      </component>
+
+      <!-- MikroE Click UART -->
+      <component name="click_uart_pl" display_name="PL Click UART" type="chip" sub_type="uart" major_group="Click" part_name="Click" vendor="MikroE">
+        <description>PL Click UART</description>
+      </component>
+
+      <!-- PUSH BUTTON -->
+      <component name="push_button_1bit" display_name="PL Push Button" type="chip" sub_type="switch" major_group="GPIO" part_name="PTS810SJG250SMTRLFS" vendor="CandK" spec_url="www.ck-components.com">
+        <description>PL Push Button</description>
+      </component>
+
+      <!-- TRI-COLOR LEDS -->
+      <component name="rgb1_led_3bits" display_name="PL RGB1 LED" type="chip" sub_type="led" major_group="GPIO" part_name="LRTBGVSR-U4V2-JW+A6BB-D8+S2U2-7Z-20-S" vendor="Osram" spec_url="www.osram.com">
+        <description>PL RGB LED, 2 to 0, Active High</description>
+      </component>
+      <component name="rgb2_led_3bits" display_name="PL RGB2 LED" type="chip" sub_type="led" major_group="GPIO" part_name="LRTBGVSR-U4V2-JW+A6BB-D8+S2U2-7Z-20-S" vendor="Osram" spec_url="www.osram.com">
+        <description>PL RGB LED, 2 to 0, Active High</description>
+      </component>
+
+      <!-- TEMPERATURE SENSOR I2C -->
+      <component name="tempsensor_i2c_pl" display_name="PL TempSensor I2C" type="chip" sub_type="mux" major_group="Sensors" part_name="STTS22HTR" vendor="STMicro" spec_url="www.st.com">
+        <description>PL Temp Sensor I2C</description>
+      </component>
+
+      <!-- HSIO DNA I2C -->
+      <component name="hsio_dna_i2c_pl" display_name="PL HSIO_DNA I2C" type="chip" sub_type="mux" major_group="HSIO" part_name="ATTINY44A-MMH" vendor="Microchip" spec_url="www.microchip.com">
+        <description>HSIO DNA I2C</description>
+      </component>
+
+      <!-- HSIO STD PL (J6) -->
+      <component name="hsio_std_J6" type="connector" sub_type="som" display_name="HSIO PL J6 (STD)">
+        <pins>
+          <pin index="0"  name="hsio_std_J6_s0_d0p"   ></pin> 
+          <pin index="1"  name="hsio_std_J6_s1_d1p"   ></pin> 
+          <pin index="2"  name="hsio_std_J6_s2_d0n"   ></pin> 
+          <pin index="3"  name="hsio_std_J6_s3_d1n"   ></pin> 
+          <pin index="4"  name="hsio_std_J6_s4_d2p"   ></pin> 
+          <pin index="5"  name="hsio_std_J6_s5_d3p"   ></pin> 
+          <pin index="6"  name="hsio_std_J6_s6_d2n"   ></pin> 
+          <pin index="7"  name="hsio_std_J6_s7_d3n"   ></pin> 
+          <pin index="8"  name="hsio_std_J6_s8_d4p"   ></pin> 
+          <pin index="9"  name="hsio_std_J6_s9_d5p"   ></pin> 
+          <pin index="10" name="hsio_std_J6_s10_d4n"  ></pin> 
+          <pin index="11" name="hsio_std_J6_s11_d5n"  ></pin> 
+          <pin index="12" name="hsio_std_J6_s12_d6p"  ></pin> 
+          <pin index="13" name="hsio_std_J6_s13_d7p"  ></pin> 
+          <pin index="14" name="hsio_std_J6_s14_d6n"  ></pin> 
+          <pin index="15" name="hsio_std_J6_s15_d7n"  ></pin> 
+          <pin index="16" name="hsio_std_J6_s16_d8p"  ></pin> 
+          <pin index="17" name="hsio_std_J6_s17_d9p"  ></pin> 
+          <pin index="18" name="hsio_std_J6_s18_d8n"  ></pin> 
+          <pin index="19" name="hsio_std_J6_s19_d9n"  ></pin> 
+          <pin index="20" name="hsio_std_J6_s20_d10p" ></pin> 
+          <pin index="21" name="hsio_std_J6_s21_d11p" ></pin> 
+          <pin index="22" name="hsio_std_J6_s22_d10n" ></pin> 
+          <pin index="23" name="hsio_std_J6_s23_d11n" ></pin> 
+          <pin index="24" name="hsio_std_J6_s24_d12p" ></pin> 
+          <pin index="25" name="hsio_std_J6_s25_d13p" ></pin> 
+          <pin index="26" name="hsio_std_J6_s26_d12n" ></pin> 
+          <pin index="27" name="hsio_std_J6_s27_d13n" ></pin> 
+          <pin index="28" name="hsio_std_J6_p2c_clkp" ></pin> 
+          <pin index="29" name="hsio_std_J6_c2p_clkp" ></pin> 
+          <pin index="30" name="hsio_std_J6_p2c_clkn" ></pin> 
+          <pin index="31" name="hsio_std_J6_c2p_clkn" ></pin> 
+        </pins>
+      </component>
+       
+      <!-- HSIO TXR2 PL (J1) -->
+      <component name="hsio_txr2_pl_J1" type="connector" sub_type="som" display_name="HSIO PL J1 (TXR2)">
+        <pins>
+          <pin index="0"  name="hsio_txr2_pl_J1_s0_d0p"   ></pin> 
+          <pin index="2"  name="hsio_txr2_pl_J1_s1_d0n"   ></pin> 
+          <pin index="1"  name="hsio_txr2_pl_J1_s2_d1p"   ></pin> 
+          <pin index="5"  name="hsio_txr2_pl_J1_s3_d2p"   ></pin> 
+          <pin index="6"  name="hsio_txr2_pl_J1_s4_d1n"   ></pin> 
+          <pin index="7"  name="hsio_txr2_pl_J1_s5_d2n"   ></pin> 
+          <pin index="8"  name="hsio_txr2_pl_J1_s6_d3p"   ></pin> 
+          <pin index="9"  name="hsio_txr2_pl_J1_s7_d4p"   ></pin> 
+          <pin index="10" name="hsio_txr2_pl_J1_s8_d3n"   ></pin> 
+          <pin index="11" name="hsio_txr2_pl_J1_s9_d4n"   ></pin> 
+          <pin index="12" name="hsio_txr2_pl_J1_s10_d5p"  ></pin> 
+          <pin index="13" name="hsio_txr2_pl_J1_s11_d6p"  ></pin> 
+          <pin index="14" name="hsio_txr2_pl_J1_s12_d5n"  ></pin> 
+          <pin index="15" name="hsio_txr2_pl_J1_s13_d6n"  ></pin> 
+          <pin index="16" name="hsio_txr2_pl_J1_s14_d7p"  ></pin> 
+          <pin index="17" name="hsio_txr2_pl_J1_s15_d8p"  ></pin> 
+          <pin index="18" name="hsio_txr2_pl_J1_s16_d7n"  ></pin> 
+          <pin index="18" name="hsio_txr2_pl_J1_s17_d8n"  ></pin> 
+          <pin index="19" name="hsio_txr2_pl_J1_p2c_clkp" ></pin> 
+          <pin index="20" name="hsio_txr2_pl_J1_c2p_clkp" ></pin> 
+          <pin index="21" name="hsio_txr2_pl_J1_p2c_clkn" ></pin> 
+          <pin index="22" name="hsio_txr2_pl_J1_c2p_clkn" ></pin> 
+        </pins>
+      </component>
+       
+       <!-- HSIO TXR2 MIO (J2) -->
+      <component name="hsio_txr2_mio_J2" type="connector" sub_type="som" display_name="HSIO MIO J2 (TXR2)">
+        <pins>
+          <pin index="0"  name="hsio_txr2_mio_J2_p2c_clkp" ></pin> 
+          <pin index="1"  name="hsio_txr2_mio_J2_c2p_clkp" ></pin> 
+          <pin index="2"  name="hsio_txr2_mio_J2_p2c_clkn" ></pin> 
+          <pin index="3"  name="hsio_txr2_mio_J2_c2p_clkn" ></pin> 
+        </pins>
+      </component>
+   </components>
+
+   <jtag_chains>
+      <jtag_chain name="chain1">
+          <position name="0" component="part0"/>
+      </jtag_chain>
+   </jtag_chains>
+     
+   <connections>
+     <!-- MikroE Click I2C -->
+     <connection name="part0_click_i2c_pl" component1="part0" component2="click_i2c_pl">
+       <connection_map name="part0_click_i2c_pl" typical_delay="5" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
+     </connection>
+   
+     <!-- MikroE Click Interrupt -->
+   
+     <!-- MikroE Click PWM -->
+   
+     <!-- MikroE Click Reset -->
+     <connection name="part0_click_reset_pl" component1="part0" component2="click_reset_pl">
+       <connection_map name="part0_click_reset_pl" typical_delay="5" c1_st_index="4" c1_end_index="4" component2="click_reset_pl" c2_st_index="0" c2_end_index="0"/>
+     </connection>
+   
+     <!-- MikroE Click SPI -->
+     <connection name="part0_click_spi_pl" component1="part0" component2="click_spi_pl">
+       <connection_map name="part0_click_spi_pl_1" c1_st_index="5" c1_end_index="9" c2_st_index="0" c2_end_index="4"/>
+     </connection>
+   
+     <!-- MikroE Click UART -->
+     <connection name="part0_click_uart_pl" component1="part0" component2="click_uart_pl">
+        <connection_map name="part0_click_uart_pl" typical_delay="5" c1_st_index="10" c1_end_index="11" c2_st_index="0" c2_end_index="1"/>
+     </connection>
+   
+     <!-- PUSH BUTTON -->
+     <connection name="part0_push_button_1bit" component1="part0" component2="push_button_1bit">
+       <connection_map name="part0_push_button_1bit_1" typical_delay="5" c1_st_index="12" c1_end_index="12" c2_st_index="0" c2_end_index="0"/>
+     </connection>
+   
+     <!-- TRI-COLOR LEDS -->
+     <connection name="part0_rgb1_led_3bits" component1="part0" component2="rgb1_led_3bits">
+       <connection_map name="part0_rgb1_led_3bits" typical_delay="5" c1_st_index="13" c1_end_index="15" c2_st_index="0" c2_end_index="2"/>
+     </connection>
+     <connection name="part0_rgb2_led_3bits" component1="part0" component2="rgb2_led_3bits">
+       <connection_map name="part0_rgb2_led_3bits" typical_delay="5" c1_st_index="16" c1_end_index="18" c2_st_index="0" c2_end_index="2"/>
+     </connection>
+   
+     <!-- TEMPERATURE SENSOR I2C -->
+     <connection name="part0_tempsensor_i2c_pl" component1="part0" component2="tempsensor_i2c_pl">
+       <connection_map name="part0_tempsensor_i2c_pl" typical_delay="5" c1_st_index="19" c1_end_index="20" c2_st_index="0" c2_end_index="1"/>
+     </connection>
+   
+     <!-- HSIO DNA I2C -->
+     <connection name="part0_hsio_dna_i2c_pl" component1="part0" component2="hsio_dna_i2c_pl">
+       <connection_map name="part0_hsio_dna_i2c_pl" typical_delay="5" c1_st_index="21" c1_end_index="22" c2_st_index="0" c2_end_index="1"/>
+     </connection>
+   
+     <!-- HSIO STD PL (J6) -->
+     <connection name="part0_hsio_std_J6_connector" component1="part0" component2="hsio_std_J6">   
+       <connection_map name="part0_hsio_std_J6_map" typical_delay="5" c1_st_index="23" c1_end_index="54" c2_st_index="0" c2_end_index="31" />
+     </connection> 
+     
+     <!-- HSIO TXR2 PL (J1) -->
+     <connection name="part0_hsio_txr2_pl_J1_connector" component1="part0" component2="hsio_txr2_pl_J1">   
+       <connection_map name="part0_hsio_txr2_pl_J1_map" typical_delay="5" c1_st_index="55" c1_end_index="76" c2_st_index="0" c2_end_index="21" />
+     </connection> 
+   
+     <!-- HSIO TXR2 MIO (J2) -->
+     <connection name="part0_hsio_txr2_mio_J2_connector" component1="part0" component2="hsio_txr2_mio_J2">   
+       <connection_map name="part0_hsio_txr2_mio_J2_map" typical_delay="5" c1_st_index="77" c1_end_index="80" c2_st_index="0" c2_end_index="3" />
+     </connection> 
+
+   </connections> 
+   
+ <!-- 
+  <ip_associated_rules>
+    <ip_associated_rule name="default">
+    </ip_associated_rule>
+  </ip_associated_rules>
+ -->
+ 
+</board>
diff --git a/HDL/boards/zub1cg/brd/1.2/changelog.txt b/HDL/boards/zub1cg/brd/1.2/changelog.txt
new file mode 100644
index 00000000..a65eb0cc
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/changelog.txt
@@ -0,0 +1,6 @@
+1.2
+Updated company to Tria (an Avnet Company)
+Updated search keywords
+
+1.0
+Original version
diff --git a/HDL/boards/zub1cg/brd/1.2/part0_pins.xml b/HDL/boards/zub1cg/brd/1.2/part0_pins.xml
new file mode 100644
index 00000000..0c2b89a2
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/part0_pins.xml
@@ -0,0 +1,126 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--<!DOCTYPE part_info SYSTEM "C:/Xilinx/Vivado/2021.2/data/boards/board_schemas/current/part0_pins.dtd">-->
+<!-- -->
+<!--   ** **        **          **  ****      **  **********  ********** ®   
+      **   **        **        **   ** **     **  **              **
+     **     **        **      **    **  **    **  **              **
+    **       **        **    **     **   **   **  *********       **
+   **         **        **  **      **    **  **  **              **
+  **           **        ****       **     ** **  **              **
+ **  .........  **        **        **      ****  **********      **
+    ...........
+                                    Reach Further™
+ Copyright (C) 2022, Avnet Inc - All rights reserved
+ Licensed under the Apache License, Version 2.0 (the "License"). You may
+ not use this file except in compliance with the License. A copy of the
+ License is located at
+     http://www.apache.org/licenses/LICENSE-2.0
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ License for the specific language governing permissions and limitations
+ under the License. -->
+
+<part_info part_name="xczu1cg-sbva484-1-e">
+   <pins>
+      <!-- MikroE Click Interface -->
+	  <!-- ZUBoard 1CG has external pull-ups on SCL/SDA, so internal pull-ups not required -->
+      <pin index="0"   name ="HD_CLICK_SCL_1V8"      iostandard="LVCMOS18" loc="F8"/>
+      <pin index="1"   name ="HD_CLICK_SDA_1V8"      iostandard="LVCMOS18" loc="F7"/>
+      <pin index="2"   name ="HD_CLICK_INT_1V8"      iostandard="LVCMOS18" loc="E8"/>
+      <pin index="3"   name ="HD_CLICK_PWM_1V8"      iostandard="LVCMOS18" loc="G6"/>
+      <pin index="4"   name ="HD_CLICK_RST_1V8"      iostandard="LVCMOS18" loc="D8"/>
+      <pin index="5"   name ="HD_CLICK_CS0_1V8"      iostandard="LVCMOS18" loc="G7"/>
+      <pin index="6"   name ="HD_CLICK_CS1_AN_1V8"   iostandard="LVCMOS18" loc="G5"/>
+      <pin index="7"   name ="HD_CLICK_MISO_1V8"     iostandard="LVCMOS18" loc="E6"/>
+      <pin index="8"   name ="HD_CLICK_MOSI_1V8"     iostandard="LVCMOS18" loc="E5"/>
+      <pin index="9"   name ="HD_CLICK_SCK_1V8"      iostandard="LVCMOS18" loc="F6"/>
+      <pin index="10"  name ="HD_CLICK_RX_1V8"       iostandard="LVCMOS18" loc="D7"/>
+      <pin index="11"  name ="HD_CLICK_TX_1V8"       iostandard="LVCMOS18" loc="D6"/>
+
+      <!-- PUSH BUTTON -->
+      <pin index="12"  name ="HD_GPIO_PB1"           iostandard="LVCMOS18" loc="A8"/>
+
+      <!-- TRI-COLOR LEDS -->
+      <pin index="13"  name ="HD_GPIO_RGB1_B"        iostandard="LVCMOS18" loc="B5"/>
+      <pin index="14"  name ="HD_GPIO_RGB1_G"        iostandard="LVCMOS18" loc="B6"/>
+      <pin index="15"  name ="HD_GPIO_RGB1_R"        iostandard="LVCMOS18" loc="A7"/>
+      <pin index="16"  name ="HP_GPIO_RGB2_B"        iostandard="LVCMOS12" loc="F4"/>
+      <pin index="17"  name ="HP_GPIO_RGB2_G"        iostandard="LVCMOS12" loc="A2"/>
+      <pin index="18"  name ="HP_GPIO_RGB2_R"        iostandard="LVCMOS12" loc="B4"/>
+
+      <!-- TEMPERATURE SENSOR I2C -->
+	  <!-- ZUBoard 1CG has external pull-ups on SCL/SDA, so internal pull-ups not required -->
+      <pin index="19"  name ="HD_SENSOR_I2C_SCL"     iostandard="LVCMOS18" loc="A6"/>
+      <pin index="20"  name ="HD_SENSOR_I2C_SDA"     iostandard="LVCMOS18" loc="B7"/>
+
+      <!-- HSIO DNA ALL -->
+	  <!-- ZUBoard 1CG has external pull-ups on SCL/SDA, so internal pull-ups not required -->
+      <pin index="21"  name ="HD_HSIO_SCL_1V8"     iostandard="LVCMOS18" loc="B9"/>
+      <pin index="22"  name ="HD_HSIO_SDA_1V8"     iostandard="LVCMOS18" loc="A9"/>
+
+      <!-- HSIO STD PL (J6) -->
+      <pin index="23"  name ="HP_DP_07_QBC_N"        iostandard="LVCMOS12" loc="P1"/>
+      <pin index="24"  name ="HP_DP_07_QBC_P"        iostandard="LVCMOS12" loc="N2"/>
+      <pin index="25"  name ="HP_DP_08_N"            iostandard="LVCMOS12" loc="N4"/>
+      <pin index="26"  name ="HP_DP_08_P"            iostandard="LVCMOS12" loc="N5"/>
+      <pin index="27"  name ="HP_DP_09_N"            iostandard="LVCMOS12" loc="M1"/>
+      <pin index="28"  name ="HP_DP_09_P"            iostandard="LVCMOS12" loc="M2"/>
+      <pin index="29"  name ="HP_DP_10_QBC_N"        iostandard="LVCMOS12" loc="M4"/>
+      <pin index="30"  name ="HP_DP_10_QBC_P"        iostandard="LVCMOS12" loc="M5"/>
+      <pin index="31"  name ="HP_DP_11_GC_N"         iostandard="LVCMOS12" loc="L1"/>
+      <pin index="32"  name ="HP_DP_11_GC_P"         iostandard="LVCMOS12" loc="L2"/>
+      <pin index="33"  name ="HP_DP_12_GC_N"         iostandard="LVCMOS12" loc="L3"/>
+      <pin index="34"  name ="HP_DP_12_GC_P"         iostandard="LVCMOS12" loc="L4"/>
+      <pin index="35"  name ="HP_DP_13_GC_N"         iostandard="LVCMOS12" loc="J2"/>
+      <pin index="36"  name ="HP_DP_13_GC_P"         iostandard="LVCMOS12" loc="J3"/>
+      <pin index="37"  name ="HP_DP_16_QBC_N"        iostandard="LVCMOS12" loc="H5"/>
+      <pin index="38"  name ="HP_DP_16_QBC_P"        iostandard="LVCMOS12" loc="J5"/>
+      <pin index="39"  name ="HP_DP_17_N"            iostandard="LVCMOS12" loc="G2"/>
+      <pin index="40"  name ="HP_DP_17_P"            iostandard="LVCMOS12" loc="H2"/>
+      <pin index="41"  name ="HP_DP_18_N"            iostandard="LVCMOS12" loc="G4"/>
+      <pin index="42"  name ="HP_DP_18_P"            iostandard="LVCMOS12" loc="H4"/>
+      <pin index="43"  name ="HP_DP_19_DBC_N"        iostandard="LVCMOS12" loc="F1"/>
+      <pin index="44"  name ="HP_DP_19_DBC_P"        iostandard="LVCMOS12" loc="G1"/>
+      <pin index="45"  name ="HP_DP_20_N"            iostandard="LVCMOS12" loc="E3"/>
+      <pin index="46"  name ="HP_DP_20_P"            iostandard="LVCMOS12" loc="E4"/>
+      <pin index="47"  name ="HP_DP_21_N"            iostandard="LVCMOS12" loc="D1"/>
+      <pin index="48"  name ="HP_DP_21_P"            iostandard="LVCMOS12" loc="E1"/>
+      <pin index="49"  name ="HP_DP_22_N"            iostandard="LVCMOS12" loc="C3"/>
+      <pin index="50"  name ="HP_DP_22_P"            iostandard="LVCMOS12" loc="D3"/>
+      <pin index="51"  name ="HP_DP_23_N"            iostandard="LVCMOS12" loc="F2"/>
+      <pin index="52"  name ="HP_DP_23_P"            iostandard="LVCMOS12" loc="F3"/>
+      <pin index="53"  name ="HP_SE_01"              iostandard="LVCMOS12" loc="N3"/>
+      <pin index="54"  name ="HP_SE_02"              iostandard="LVCMOS12" loc="H3"/>
+
+      <!-- HSIO TXR2 PL (J1) -->
+      <pin index="55"  name ="HP_DP_01_DBC_N"        iostandard="LVCMOS12" loc="T2"/>
+      <pin index="56"  name ="HP_DP_01_DBC_P"        iostandard="LVCMOS12" loc="T3"/>
+      <pin index="57"  name ="HP_DP_02_N"            iostandard="LVCMOS12" loc="R3"/>
+      <pin index="58"  name ="HP_DP_02_P"            iostandard="LVCMOS12" loc="P3"/>
+      <pin index="59"  name ="HP_DP_03_N"            iostandard="LVCMOS12" loc="U1"/>
+      <pin index="60"  name ="HP_DP_03_P"            iostandard="LVCMOS12" loc="U2"/>
+      <pin index="61"  name ="HP_DP_04_N"            iostandard="LVCMOS12" loc="T4"/>
+      <pin index="62"  name ="HP_DP_04_P"            iostandard="LVCMOS12" loc="R4"/>
+      <pin index="63"  name ="HP_DP_05_N"            iostandard="LVCMOS12" loc="T1"/>
+      <pin index="64"  name ="HP_DP_05_P"            iostandard="LVCMOS12" loc="R1"/>
+      <pin index="65"  name ="HP_DP_06_N"            iostandard="LVCMOS12" loc="R5"/>
+      <pin index="66"  name ="HP_DP_06_P"            iostandard="LVCMOS12" loc="P5"/>
+      <pin index="67"  name ="HP_DP_11_GC_66_N"      iostandard="LVCMOS12" loc="B1"/>
+      <pin index="68"  name ="HP_DP_11_GC_66_P"      iostandard="LVCMOS12" loc="B2"/>
+      <pin index="69"  name ="HP_DP_12_GC_66_N"      iostandard="LVCMOS12" loc="A3"/>
+      <pin index="70"  name ="HP_DP_12_GC_66_P"      iostandard="LVCMOS12" loc="A4"/>
+      <pin index="71"  name ="HP_DP_14_GC_N"         iostandard="LVCMOS12" loc="K3"/>
+      <pin index="72"  name ="HP_DP_14_GC_P"         iostandard="LVCMOS12" loc="K4"/>
+      <pin index="73"  name ="HP_DP_15_N"            iostandard="LVCMOS12" loc="J1"/>
+      <pin index="74"  name ="HP_DP_15_P"            iostandard="LVCMOS12" loc="K1"/>
+      <pin index="75"  name ="HP_DP_24_N"            iostandard="LVCMOS12" loc="C2"/>
+      <pin index="76"  name ="HP_DP_24_P"            iostandard="LVCMOS12" loc="D2"/>
+	  
+  	  <!-- HSIO TXR2 MIO (J2) -->
+      <pin index="77"  name ="HD_DP_07_GC_N"         iostandard="LVCMOS18" loc="C5"/>
+      <pin index="78"  name ="HD_DP_07_GC_P"         iostandard="LVCMOS18" loc="D5"/>
+      <pin index="79"  name ="HD_DP_08_GC_N"         iostandard="LVCMOS18" loc="C7"/>
+      <pin index="80"  name ="HD_DP_08_GC_P"         iostandard="LVCMOS18" loc="C8"/>
+   </pins>
+</part_info>
diff --git a/HDL/boards/zub1cg/brd/1.2/preset.xml b/HDL/boards/zub1cg/brd/1.2/preset.xml
new file mode 100644
index 00000000..3bf146c4
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/preset.xml
@@ -0,0 +1,736 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--<!DOCTYPE ip_presets SYSTEM "C:/Xilinx/Vivado/2021.1/data/boards/board_schemas/current/preset.dtd">-->
+<!-- -->
+<!--   ** **        **          **  ****      **  **********  ********** ®   
+      **   **        **        **   ** **     **  **              **
+     **     **        **      **    **  **    **  **              **
+    **       **        **    **     **   **   **  *********       **
+   **         **        **  **      **    **  **  **              **
+  **           **        ****       **     ** **  **              **
+ **  .........  **        **        **      ****  **********      **
+    ...........
+                                    Reach Further™
+ Copyright (C) 2022, Avnet Inc - All rights reserved
+ Licensed under the Apache License, Version 2.0 (the "License"). You may
+ not use this file except in compliance with the License. A copy of the
+ License is located at
+     http://www.apache.org/licenses/LICENSE-2.0
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ License for the specific language governing permissions and limitations
+ under the License. -->
+     
+<ip_presets schema="1.0">
+   <ip_preset preset_proc_name="zynq_ultra_ps_e_preset"> 
+      <ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" version="*"> 
+         <user_parameters>
+            <user_parameter name="CONFIG.PSU__PRESET_APPLIED" value="1"/>     
+      
+            <user_parameter name="CONFIG.PSU__PSS_REF_CLK__FREQMHZ" value="33.333333"/>
+            
+            <user_parameter name="CONFIG.PSU__USE__IRQ0"      value="0"/>
+            <user_parameter name="CONFIG.PSU__USE__IRQ1"      value="0"/>
+            <user_parameter name="CONFIG.PSU__USE__M_AXI_GP0" value="1"/>
+            <user_parameter name="CONFIG.PSU__USE__M_AXI_GP1" value="1"/>
+            <user_parameter name="CONFIG.PSU__USE__M_AXI_GP2" value="0"/>
+            
+            <user_parameter name="CONFIG.PSU_BANK_0_IO_STANDARD" value="LVCMOS18"/>
+            <user_parameter name="CONFIG.PSU_BANK_1_IO_STANDARD" value="LVCMOS18"/>
+            <user_parameter name="CONFIG.PSU_BANK_2_IO_STANDARD" value="LVCMOS18"/>
+            <user_parameter name="CONFIG.PSU_BANK_3_IO_STANDARD" value="LVCMOS18"/>
+
+            <user_parameter name="CONFIG.PSU_MIO_0_DIRECTION"       value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_0_INPUT_TYPE"      value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_5_DIRECTION"       value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_5_INPUT_TYPE"      value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_7_PULLUPDOWN"      value="pulldown"/>
+            <user_parameter name="CONFIG.PSU_MIO_6_DIRECTION"       value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_6_INPUT_TYPE"      value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_10_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_10_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_10_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_11_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_11_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_12_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_12_PULLUPDOWN"     value="pullup"/>
+            <user_parameter name="CONFIG.PSU_MIO_22_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_22_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_23_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_23_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_24_PULLUPDOWN"     value="pulldown"/>
+            <user_parameter name="CONFIG.PSU_MIO_25_PULLUPDOWN"     value="pulldown"/>
+            <user_parameter name="CONFIG.PSU_MIO_26_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_26_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_26_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_27_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_27_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_28_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_28_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_28_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_29_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_29_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_30_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_30_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_30_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_33_PULLUPDOWN"     value="pulldown"/>
+            <user_parameter name="CONFIG.PSU_MIO_34_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_34_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_45_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_45_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_45_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_46_DRIVE_STRENGTH" value="4"/>
+            <user_parameter name="CONFIG.PSU_MIO_47_DRIVE_STRENGTH" value="4"/>
+            <user_parameter name="CONFIG.PSU_MIO_48_DRIVE_STRENGTH" value="4"/>
+            <user_parameter name="CONFIG.PSU_MIO_49_DRIVE_STRENGTH" value="4"/>
+            <user_parameter name="CONFIG.PSU_MIO_50_DRIVE_STRENGTH" value="4"/>
+            <user_parameter name="CONFIG.PSU_MIO_51_DRIVE_STRENGTH" value="4"/>
+            <user_parameter name="CONFIG.PSU_MIO_51_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_51_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_52_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_52_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_52_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_52_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_53_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_53_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_53_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_53_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_54_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_54_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_55_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_55_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_55_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_55_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_56_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_56_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_57_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_57_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_58_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_58_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_58_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_58_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_59_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_59_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_59_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_60_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_60_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_60_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_61_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_61_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_61_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_62_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_62_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_62_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_63_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_63_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_63_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_64_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_64_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_64_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_65_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_65_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_65_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_67_DIRECTION"      value="in"/>
+            <user_parameter name="CONFIG.PSU_MIO_67_DRIVE_STRENGTH" value="12"/>
+            <user_parameter name="CONFIG.PSU_MIO_67_SLEW"           value="fast"/>
+            <user_parameter name="CONFIG.PSU_MIO_70_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_70_INPUT_TYPE"     value="cmos"/>
+            <user_parameter name="CONFIG.PSU_MIO_76_DIRECTION"      value="out"/>
+            <user_parameter name="CONFIG.PSU_MIO_76_INPUT_TYPE"     value="cmos"/>
+
+            <user_parameter name="CONFIG.PSU__DDRC__ECC"                value="Disabled"/>
+            <user_parameter name="CONFIG.PSU__DDRC__BUS_WIDTH"          value="32 Bit"/>
+            <user_parameter name="CONFIG.PSU__DDRC__DRAM_WIDTH"         value="32 Bits"/>
+            <user_parameter name="CONFIG.PSU__DDRC__MEMORY_TYPE"        value="LPDDR 4"/>
+            <user_parameter name="CONFIG.PSU__DDRC__SPEED_BIN"          value="LPDDR4_1066"/>
+            <user_parameter name="CONFIG.PSU__DDRC__BANK_ADDR_COUNT"    value="3"/>
+            <user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY"    value="8192 MBits"/>
+            <user_parameter name="CONFIG.PSU__DDRC__RANK_ADDR_COUNT"    value="0"/>
+            <user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT"     value="15"/>
+            <user_parameter name="CONFIG.PSU__DDRC__COL_ADDR_COUNT"     value="10"/>
+            <user_parameter name="CONFIG.PSU__DDRC__T_FAW"              value="40.0"/>
+            <user_parameter name="CONFIG.PSU__DDRC__T_RAS_MIN"          value="42"/>
+            <user_parameter name="CONFIG.PSU__DDRC__T_RC"               value="63"/>
+            <user_parameter name="CONFIG.PSU__DDRC__T_RCD"              value="10"/>
+            <user_parameter name="CONFIG.PSU__DDRC__T_RP"               value="12"/>
+            <user_parameter name="CONFIG.PSU__DDRC__DM_DBI"             value="DM_NO_DBI"/>
+            <user_parameter name="CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE" value="Normal (0-85)"/>
+            <user_parameter name="CONFIG.PSU__DDRC__ADDR_MIRROR"        value="1"/>
+            <user_parameter name="CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN"     value="0"/>
+
+            <user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__IO"          value="GT Lane1"/>
+            <user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__IO"          value="GT Lane0"/>
+            <user_parameter name="CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__DLL__ISUSED"                     value="1"/>
+            <user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__DP__LANE_SEL"                    value="Dual Lower"/>
+            <user_parameter name="CONFIG.PSU__DP__REF_CLK_FREQ"                value="27"/>
+            <user_parameter name="CONFIG.PSU__DP__REF_CLK_SEL"                 value="Ref Clk2"/>
+         
+            <user_parameter name="CONFIG.PSU__ENET0__FIFO__ENABLE"            value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET0__GRP_MDIO__ENABLE"        value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET0__PERIPHERAL__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET0__PTP__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET0__TSU__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET1__FIFO__ENABLE"            value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET1__GRP_MDIO__ENABLE"        value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET1__PERIPHERAL__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET1__PTP__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET1__TSU__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET2__FIFO__ENABLE"            value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET2__GRP_MDIO__ENABLE"        value="1"/>
+            <user_parameter name="CONFIG.PSU__ENET2__GRP_MDIO__IO"            value="MIO 76 .. 77"/>
+            <user_parameter name="CONFIG.PSU__ENET2__PERIPHERAL__ENABLE"      value="1"/>
+            <user_parameter name="CONFIG.PSU__ENET2__PERIPHERAL__IO"          value="MIO 52 .. 63"/>
+            <user_parameter name="CONFIG.PSU__ENET2__PTP__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET2__TSU__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET3__FIFO__ENABLE"            value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__ENABLE"        value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET3__PTP__ENABLE"             value="0"/>
+            <user_parameter name="CONFIG.PSU__ENET3__TSU__ENABLE"             value="0"/>
+               
+            <user_parameter name="CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ"   value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ"       value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT" value="APB"/>
+
+            <user_parameter name="CONFIG.PSU__GEM0_COHERENCY"         value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD" value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM1_COHERENCY"         value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD" value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM2_COHERENCY"         value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD" value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM3_COHERENCY"         value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD" value="0"/>
+            <user_parameter name="CONFIG.PSU__GEM__TSU__ENABLE"       value="0"/>
+
+            <user_parameter name="CONFIG.PSU__GPIO0_MIO__IO"                 value="MIO 0 .. 25"/>
+            <user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__GPIO1_MIO__IO"                 value="MIO 26 .. 51"/>
+            <user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__GPIO2_MIO__IO"                 value="MIO 52 .. 77"/>
+            <user_parameter name="CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__GPIO_EMIO_WIDTH"               value="30"/>
+            <user_parameter name="CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__GT__LINK_SPEED"     value="HBR"/>
+            <user_parameter name="CONFIG.PSU__GT__PRE_EMPH_LVL_4" value="0"/>
+            <user_parameter name="CONFIG.PSU__GT__VLT_SWNG_LVL_4" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__HIGH_ADDRESS__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__IO"     value="MIO 8 .. 9"/>
+
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ"   value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ"       value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ"   value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ"       value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ"   value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ"       value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ"   value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ"       value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ"   value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ"       value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT" value="APB"/>
+
+            <user_parameter name="CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ"     value="100.000000"/>
+
+            <user_parameter name="CONFIG.PSU__MAXIGP0__DATA_WIDTH" value="128"/>
+            <user_parameter name="CONFIG.PSU__MAXIGP2__DATA_WIDTH" value="32"/>
+
+            <user_parameter name="CONFIG.PSU__NAND_COHERENCY"            value="0"/>
+            <user_parameter name="CONFIG.PSU__NAND_ROUTE_THROUGH_FPD"    value="0"/>
+            <user_parameter name="CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__NAND__DATA_STROBE__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__NAND__PERIPHERAL__ENABLE"  value="0"/>
+            <user_parameter name="CONFIG.PSU__NAND__READY0_BUSY__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__NAND__READY1_BUSY__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__NUM_FABRIC_RESETS" value="1"/>
+            <user_parameter name="CONFIG.PSU__USE__FABRIC__RST"  value="1"/>
+
+            <user_parameter name="CONFIG.PSU__PL_CLK0_BUF" value="TRUE"/>
+            <user_parameter name="CONFIG.PSU__PL_CLK1_BUF" value="FALSE"/>
+            <user_parameter name="CONFIG.PSU__PL_CLK2_BUF" value="FALSE"/>
+            <user_parameter name="CONFIG.PSU__PL_CLK3_BUF" value="FALSE"/>
+
+            <user_parameter name="CONFIG.PSU__PMU_COHERENCY"           value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__AIBACK__ENABLE"     value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__EMIO_GPI__ENABLE"   value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__EMIO_GPO__ENABLE"   value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI0__ENABLE"       value="1"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI0__IO"           value="MIO 26"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI1__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI2__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI3__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI4__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPI5__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO0__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO1__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO2__ENABLE"       value="1"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO2__IO"           value="MIO 34"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO2__POLARITY"     value="high"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO3__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO4__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__GPO5__ENABLE"       value="0"/>
+            <user_parameter name="CONFIG.PSU__PMU__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__PMU__PLERROR__ENABLE"    value="0"/>
+
+            <user_parameter name="CONFIG.PSU__QSPI_COHERENCY"              value="0"/>
+            <user_parameter name="CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD"      value="0"/>
+            <user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE"     value="1"/>
+            <user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__IO"         value="MIO 6"/>
+            <user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE" value="x4"/>
+            <user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE"    value="1"/>
+            <user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__IO"        value="MIO 0 .. 5"/>
+            <user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__MODE"      value="Single"/>
+
+            <user_parameter name="CONFIG.PSU__SATA__LANE0__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__SATA__LANE1__ENABLE"      value="0"/>
+            <user_parameter name="CONFIG.PSU__SATA__PERIPHERAL__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__SD0_COHERENCY"           value="0"/>
+            <user_parameter name="CONFIG.PSU__SD0_ROUTE_THROUGH_FPD"   value="0"/>
+            <user_parameter name="CONFIG.PSU__SD0__DATA_TRANSFER_MODE" value="8Bit"/>
+            <user_parameter name="CONFIG.PSU__SD0__GRP_CD__ENABLE"     value="0"/>
+            <user_parameter name="CONFIG.PSU__SD0__GRP_POW__ENABLE"    value="0"/>
+            <user_parameter name="CONFIG.PSU__SD0__GRP_WP__ENABLE"     value="0"/>
+            <user_parameter name="CONFIG.PSU__SD0__PERIPHERAL__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SD0__RESET__ENABLE"      value="1"/>
+            <user_parameter name="CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH"   value="8"/>
+
+            <user_parameter name="CONFIG.PSU__SD1_COHERENCY" value="0"/>
+            <user_parameter name="CONFIG.PSU__SD1_ROUTE_THROUGH_FPD" value="0"/>
+            <user_parameter name="CONFIG.PSU__SD1__DATA_TRANSFER_MODE" value="4Bit"/>
+            <user_parameter name="CONFIG.PSU__SD1__GRP_CD__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__SD1__GRP_CD__IO" value="MIO 45"/>
+            <user_parameter name="CONFIG.PSU__SD1__GRP_POW__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SD1__GRP_WP__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 46 .. 51"/>
+            <user_parameter name="CONFIG.PSU__SD1__RESET__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 2.0"/>
+            <user_parameter name="CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH" value="4"/>
+
+            <user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__SPI0__GRP_SS0__IO" value="MIO 41"/>
+            <user_parameter name="CONFIG.PSU__SPI0__GRP_SS1__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SPI0__GRP_SS2__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__SPI0__PERIPHERAL__IO" value="MIO 38 .. 43"/>
+
+            <user_parameter name="CONFIG.PSU__SWDT0__CLOCK__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SWDT0__RESET__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SWDT1__CLOCK__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__SWDT1__RESET__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__TSU__BUFG_PORT_PAIR" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__TTC0__CLOCK__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC0__WAVEOUT__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC1__CLOCK__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC1__WAVEOUT__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC2__CLOCK__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC2__WAVEOUT__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC3__CLOCK__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__TTC3__WAVEOUT__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__UART0__BAUD_RATE" value="115200"/>
+            <user_parameter name="CONFIG.PSU__UART0__MODEM__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__IO" value="MIO 10 .. 11"/>
+
+            <user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__USB0_COHERENCY" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB0__REF_CLK_FREQ" value="26"/>
+            <user_parameter name="CONFIG.PSU__USB0__REF_CLK_SEL" value="Ref Clk3"/>
+            <user_parameter name="CONFIG.PSU__USB0__RESET__ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__USB1_COHERENCY" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__USB1__PERIPHERAL__IO" value="MIO 64 .. 75"/>
+            <user_parameter name="CONFIG.PSU__USB1__RESET__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB2_0__EMIO__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB2_1__EMIO__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB3_0__EMIO__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB3_1__EMIO__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__USB__RESET__MODE" value="Boot Pin"/>
+            <user_parameter name="CONFIG.PSU__USB__RESET__POLARITY" value="Active Low"/>
+
+            <user_parameter name="CONFIG.PSU__ACT_DDR_FREQ_MHZ" value="533.333313"/>
+            <user_parameter name="CONFIG.PSU__DDR__INTERFACE__FREQMHZ" value="266.500"/>
+
+            <user_parameter name="CONFIG.PSU__CSUPMU__PERIPHERAL__VALID" value="1"/>
+
+            <user_parameter name="CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE" value="1"/>
+         
+            <user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__TTC1__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__TTC2__PERIPHERAL__ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__TTC3__PERIPHERAL__ENABLE" value="1"/>
+
+            <user_parameter name="CONFIG.PSU__FPGA_PL0_ENABLE" value="1"/>
+            <user_parameter name="CONFIG.PSU__FPGA_PL1_ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__FPGA_PL2_ENABLE" value="0"/>
+            <user_parameter name="CONFIG.PSU__FPGA_PL3_ENABLE" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__OVERRIDE__BASIC_CLOCK" value="1"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" value="1200.000000"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL" value="APLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV" value="72"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" value="2"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" value="IOPLL"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" value="5"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" value="IOPLL"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" value="2"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" value="266.666656"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0" value="4"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ" value="533"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL" value="DPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" value="2"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" value="APLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV" value="64"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ" value="300"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" value="9.362301"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" value="42"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" value="RPLL"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" value="10.082479"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" value="39"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" value="RPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" value="297.029572"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" value="4"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" value="VPLL"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED" value="0"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" value="600.000000"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" value="2"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" value="APLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" value="3"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0" value="6"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0" value="5"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" value="250"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" value="5"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+            
+            <user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" value="533.333313"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" value="2"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" value="DPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV" value="71"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA" value="0.2871"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ" value="300"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" value="3"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" value="500.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" value="3"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0" value="3"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" value="50.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" value="30"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" value="500.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" value="3"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" value="IOPLL"/>
+
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ" value="500"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0" value="4"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ" value="400"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL" value="IOPLL"/>
+
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" value="6"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" value="1500.000000"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0" value="12"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0" value="12"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ" value="125.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0" value="12"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ" value="125.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0" value="12"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0" value="6"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV" value="45"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" value="0"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" value="3"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" value="6"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" value="500.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" value="3"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ" value="99.999001"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" value="187.500000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0" value="8"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" value="50.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" value="30"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" value="100"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" value="RPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ" value="25.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0" value="60"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ" value="100"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL" value="RPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ" value="150.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0" value="10"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ" value="100"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL" value="RPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" value="300.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" value="5"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV" value="70"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA" value="0.779"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ" value="25"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" value="3"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ" value="187.500000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0" value="8"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" value="187.500000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" value="8"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ" value="187.500000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0" value="8"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0" value="7"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ" value="100.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0" value="6"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" value="IOPLL"/>
+
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ" value="250.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0" value="6"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1" value="1"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL" value="IOPLL"/>
+               
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" value="20.000000"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" value="5"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" value="15"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" value="IOPLL"/>
+            <user_parameter name="CONFIG.PSU__CRL_APB__USB3__ENABLE" value="0"/>
+         </user_parameters>
+      </ip>
+   </ip_preset>
+   <ip_preset preset_proc_name="click_reset_pl_preset">
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_GPIO_WIDTH"  value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS"  value="0"/>
+         </user_parameters>
+     </ip>
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_IS_DUAL"       value="1"/> 
+           <user_parameter name="CONFIG.C_GPIO2_WIDTH"   value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS_2"  value="0"/>
+         </user_parameters>
+     </ip>
+   </ip_preset>
+   <ip_preset preset_proc_name="click_spi_pl_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+        <user_parameters>
+            <user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+            <user_parameter name="CONFIG.C_SCK_RATIO" value="16"/>
+            <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+            <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+            <user_parameter name="CONFIG.C_NUM_SS_BITS" value="2"/>
+        </user_parameters>
+    </ip>
+   </ip_preset>
+   <ip_preset preset_proc_name="rgb1_led_3bits_preset">
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_GPIO_WIDTH"  value="3"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS"  value="0"/>
+         </user_parameters>
+     </ip>
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_IS_DUAL"       value="1"/> 
+           <user_parameter name="CONFIG.C_GPIO2_WIDTH"   value="3"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS_2"  value="0"/>
+         </user_parameters>
+     </ip>
+   </ip_preset>
+   <ip_preset preset_proc_name="rgb2_led_3bits_preset">
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_GPIO_WIDTH"  value="3"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS"  value="0"/>
+         </user_parameters>
+     </ip>
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_IS_DUAL"       value="1"/> 
+           <user_parameter name="CONFIG.C_GPIO2_WIDTH"   value="3"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS_2"  value="0"/>
+         </user_parameters>
+     </ip>
+   </ip_preset>
+   <ip_preset preset_proc_name="push_button_1bit_preset">
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+         </user_parameters>
+     </ip>
+     <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+         <user_parameters>
+           <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+           <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+           <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+         </user_parameters>
+     </ip>
+   </ip_preset>
+</ip_presets>
diff --git a/HDL/boards/zub1cg/brd/1.2/xitem.json b/HDL/boards/zub1cg/brd/1.2/xitem.json
new file mode 100644
index 00000000..a18f39a7
--- /dev/null
+++ b/HDL/boards/zub1cg/brd/1.2/xitem.json
@@ -0,0 +1,40 @@
+{
+  "config": {
+    "items": [
+      {
+        "infra": {
+          "name": "ZUBoard_1CG", 
+          "display": "ZUBoard 1CG Development Board", 
+          "revision": "1.2", 
+          "description": "ZUBoard 1CG Development Board", 
+
+          "company": "Tria (an Avnet Company)", 
+          "company_display": "Tria (an Avnet Company)", 
+          "author": "Avnet", 
+          "contributors": [
+            {
+              "group": "Avnet", 
+              "url": "avnet.me/ZUBoard-1CG"
+            }
+          ],
+          "category": "Evaluation Boards", 
+          "website": "avnet.me/ZUBoard-1CG", 
+          "search-keywords": [
+            "zuboard", 
+            "zu1", 
+            "1cg", 
+            "devkit", 
+            "avnet",
+            "tria",     
+            "avnet.com", 
+            "tria-technologies.com",
+            "board", 
+            "Evaluation Boards"
+          ]
+        }
+      }
+    ]
+  }, 
+  "_major": 1, 
+  "_minor": 0
+}
diff --git a/HDL/boards/zub1cg/brd/1.2/zub1cg_top.png b/HDL/boards/zub1cg/brd/1.2/zub1cg_top.png
new file mode 100644
index 00000000..2cf64161
Binary files /dev/null and b/HDL/boards/zub1cg/brd/1.2/zub1cg_top.png differ
diff --git a/HDL/cores/axi_bidrectional_spi_v1_0/axi_bidirectional_spi.v b/HDL/cores/axi_bidrectional_spi_v1_0/axi_bidirectional_spi.v
new file mode 100644
index 00000000..8b2225d6
--- /dev/null
+++ b/HDL/cores/axi_bidrectional_spi_v1_0/axi_bidirectional_spi.v
@@ -0,0 +1,431 @@
+
+`timescale 1 ns / 1 ps
+
+// This core is for driving a sinlge lane SPI device with a bidirectional data line
+// In the first version of this core, there are only 4 registers
+// 0x00 32 bit register for the data to be sent
+// 0x04 32 bit register for the R/W mask
+// 0x08 32 bit register for the data bit-length in the bottom 8 bits and the status of the SPI interface in the top 24bits
+// 0x12 32 bit register for the data read
+module axi_bidirectional_spi #
+(
+ parameter integer C_S_AXI_DATA_WIDTH = 32,
+ parameter integer C_S_AXI_ADDR_WIDTH = 2
+)
+(
+  // Control Signals for the SPI interface
+  inout wire 				    spi_sdio,
+  output wire 				  spi_sclk,
+  output wire 				  spi_cs_n,
+
+ // Do not modify the ports beyond this line
+ 
+ // Global Clock Signal
+  input wire 				    S_AXI_ACLK,
+ // Global Reset Signal. This Signal is Active LOW
+  input wire 				    S_AXI_ARESETN,
+ // Write address (issued by master, acceped by Slave)
+  input wire [C_S_AXI_ADDR_WIDTH-1 : 0]     S_AXI_AWADDR,
+ // Write channel Protection type. This signal indicates the
+ // privilege and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+  input wire [2 : 0] 			    S_AXI_AWPROT,
+ // Write address valid. This signal indicates that the master signaling
+ // valid write address and control information.
+  input wire 				    S_AXI_AWVALID,
+ // Write address ready. This signal indicates that the slave is ready
+ // to accept an address and associated control signals.
+  output wire 				    S_AXI_AWREADY,
+ // Write data (issued by master, acceped by Slave) 
+  input wire [C_S_AXI_DATA_WIDTH-1 : 0]     S_AXI_WDATA,
+ // Write strobes. This signal indicates which byte lanes hold
+ // valid data. There is one write strobe bit for each eight
+ // bits of the write data bus.    
+  input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available.
+  input wire 				    S_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+  output wire 				    S_AXI_WREADY,
+ // Write response. This signal indicates the status
+ // of the write transaction.
+  output wire [1 : 0] 			    S_AXI_BRESP,
+ // Write response valid. This signal indicates that the channel
+ // is signaling a valid write response.
+  output wire 				    S_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+  input wire 				    S_AXI_BREADY,
+ // Read address (issued by master, acceped by Slave)
+  input wire [C_S_AXI_ADDR_WIDTH-1 : 0]     S_AXI_ARADDR,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether the
+ // transaction is a data access or an instruction access.
+  input wire [2 : 0] 			    S_AXI_ARPROT,
+ // Read address valid. This signal indicates that the channel
+ // is signaling valid read address and control information.
+  input wire 				    S_AXI_ARVALID,
+ // Read address ready. This signal indicates that the slave is
+ // ready to accept an address and associated control signals.
+  output wire 				    S_AXI_ARREADY,
+    // Read data (issued by slave)
+  output wire [C_S_AXI_DATA_WIDTH-1 : 0]    S_AXI_RDATA,
+ // Read response. This signal indicates the status of the
+ // read transfer.
+  output wire [1 : 0] 			    S_AXI_RRESP,
+ // Read valid. This signal indicates that the channel is
+ // signaling the required read data.
+  output wire 				    S_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+  input wire 				    S_AXI_RREADY
+);
+
+   //    
+   // AXI4LITE signals
+   reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+   reg 				  axi_awready;
+   reg 				  axi_wready;
+   reg [1 : 0] 			  axi_bresp;
+   reg 				  axi_bvalid;
+   reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+   reg 				  axi_arready;
+   reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
+   reg [1 : 0] 			  axi_rresp;
+   reg 				  axi_rvalid;
+   
+   // Example-specific design signals
+   // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+   // ADDR_LSB is used for addressing 32/64 bit registers/memories
+   // ADDR_LSB = 2 for 32 bits (n downto 2)
+   // ADDR_LSB = 3 for 64 bits (n downto 3)
+   localparam integer 		  ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+   localparam integer 		  OPT_MEM_ADDR_BITS = 3;
+   //----------------------------------------------
+   //-- Signals for user logic register space example
+   //------------------------------------------------
+   //-- Number of Slave Registers 4
+   reg [C_S_AXI_DATA_WIDTH-1:0]   slv_reg0;
+   reg [C_S_AXI_DATA_WIDTH-1:0]   slv_reg1;
+   reg [C_S_AXI_DATA_WIDTH-1:0]   slv_reg2;
+   reg [C_S_AXI_DATA_WIDTH-1:0]   slv_reg3;
+  
+   
+   wire 			  slv_reg_rden;
+   wire 			  slv_reg_wren;
+   reg [C_S_AXI_DATA_WIDTH-1:0]   reg_data_out;
+   integer 			  byte_index;
+   
+   // I/O Connections assignments
+   
+   assign S_AXI_AWREADY    = axi_awready;
+   assign S_AXI_WREADY    = axi_wready;
+   assign S_AXI_BRESP    = axi_bresp;
+   assign S_AXI_BVALID    = axi_bvalid;
+   assign S_AXI_ARREADY    = axi_arready;
+   assign S_AXI_RDATA    = axi_rdata;
+   assign S_AXI_RRESP    = axi_rresp;
+   assign S_AXI_RVALID    = axi_rvalid;
+   // Implement axi_awready generation
+   // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+   // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+   // de-asserted when reset is low.
+   
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_awready <= 1'b0;
+	  end 
+	else
+	  begin    
+	     if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
+               begin
+		  // slave is ready to accept write address when 
+		  // there is a valid write address and write data
+		  // on the write address and data bus. This design 
+		  // expects no outstanding transactions. 
+		  axi_awready <= 1'b1;
+               end
+	     else           
+               begin
+		  axi_awready <= 1'b0;
+               end
+	  end 
+     end       
+   
+   // Implement axi_awaddr latching
+   // This process is used to latch the address when both 
+   // S_AXI_AWVALID and S_AXI_WVALID are valid. 
+   
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_awaddr <= 0;
+	  end 
+	else
+	  begin    
+	     if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
+               begin
+		  // Write Address latching 
+		  axi_awaddr <= S_AXI_AWADDR;
+               end
+	  end 
+     end       
+   
+   // Implement axi_wready generation
+   // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+   // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+   // de-asserted when reset is low. 
+   
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_wready <= 1'b0;
+	  end 
+	else
+	  begin    
+	     if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
+               begin
+		  // slave is ready to accept write data when 
+		  // there is a valid write address and write data
+		  // on the write address and data bus. This design 
+		  // expects no outstanding transactions. 
+		  axi_wready <= 1'b1;
+               end
+	     else
+               begin
+		  axi_wready <= 1'b0;
+               end
+	  end 
+     end       
+   
+   // Implement memory mapped register select and write logic generation
+   // The write data is accepted and written to memory mapped registers when
+   // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+   // select byte enables of slave registers while writing.
+   // These registers are cleared when reset (active low) is applied.
+   // Slave register write enable is asserted when valid address and data are available
+   // and the slave is ready to accept the write address and write data.
+   assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+   
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     slv_reg0 <= 8'h00;
+	     //slv_reg1 <= 8'h10;
+	     //slv_reg2 <= 8'h20;
+	     //slv_reg3 <= 8'h30;
+	     //slv_reg4 <= 8'h40;
+	     //slv_reg5 <= 8'h50;
+	     //slv_reg6 <= 8'h60;
+	     //slv_reg7 <= 8'h70;
+	     //slv_reg8 <= 8'h80;
+	     //slv_reg9 <= 8'h90;
+	     //slv_reg10 <= 8'h77;
+	  end 
+	else begin
+	   if (slv_reg_wren)
+	     begin
+		case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+		  4'h0:
+		    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+		      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+			 // Respective byte enables are asserted as per write strobes 
+			 // Slave register 0
+			 slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+		      end  
+		  4'h1:
+		    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+		      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+			 // Respective byte enables are asserted as per write strobes 
+			 // Slave register 1
+			 slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+		      end  
+		  4'h2:
+		    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+		      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+			 // Respective byte enables are asserted as per write strobes 
+			 // Slave register 2
+			 slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+		      end  
+		  4'h3:
+		    for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+		      if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+			 // Respective byte enables are asserted as per write strobes 
+			 // Slave register 3
+			 slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+		      end  
+		  default : begin
+                     //slv_reg0 <= slv_reg0;
+                     //slv_reg1 <= slv_reg1;
+                     //slv_reg2 <= slv_reg2;
+                     //slv_reg3 <= slv_reg3;
+                  end
+		endcase
+	     end
+	end
+     end    
+   
+   // Implement write response logic generation
+   // The write response and response valid signals are asserted by the slave 
+   // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+   // This marks the acceptance of address and indicates the status of 
+   // write transaction.
+   
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_bvalid  <= 0;
+	     axi_bresp   <= 2'b0;
+	  end 
+	else
+	  begin    
+	     if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+               begin
+		  // indicates a valid write response is available
+		  axi_bvalid <= 1'b1;
+		  axi_bresp  <= 2'b0; // 'OKAY' response 
+               end                   // work error responses in future
+	     else
+               begin
+		  if (S_AXI_BREADY && axi_bvalid) 
+		    //check if bready is asserted while bvalid is high) 
+		    //(there is a possibility that bready is always asserted high)   
+		    begin
+		       axi_bvalid <= 1'b0; 
+		    end  
+               end
+	  end
+     end   
+   
+   // Implement axi_arready generation
+   // axi_arready is asserted for one S_AXI_ACLK clock cycle when
+   // S_AXI_ARVALID is asserted. axi_awready is 
+   // de-asserted when reset (active low) is asserted. 
+   // The read address is also latched when S_AXI_ARVALID is 
+   // asserted. axi_araddr is reset to zero on reset assertion.
+   
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_arready <= 1'b0;
+	     axi_araddr  <= 32'b0;
+	  end 
+	else
+	  begin    
+	     if (~axi_arready && S_AXI_ARVALID)
+               begin
+		  // indicates that the slave has acceped the valid read address
+		  axi_arready <= 1'b1;
+		  // Read address latching
+		  axi_araddr  <= S_AXI_ARADDR;
+               end
+	     else
+               begin
+		  axi_arready <= 1'b0;
+               end
+	  end 
+     end       
+   
+   // Implement axi_arvalid generation
+   // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+   // S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+   // data are available on the axi_rdata bus at this instance. The 
+   // assertion of axi_rvalid marks the validity of read data on the 
+   // bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+   // is deasserted on reset (active low). axi_rresp and axi_rdata are 
+   // cleared to zero on reset (active low).  
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_rvalid <= 0;
+	     axi_rresp  <= 0;
+	  end 
+	else
+	  begin    
+	     if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+               begin
+		  // Valid read data is available at the read data bus
+		  axi_rvalid <= 1'b1;
+		  axi_rresp  <= 2'b0; // 'OKAY' response
+               end   
+	     else if (axi_rvalid && S_AXI_RREADY)
+               begin
+		  // Read data is accepted by the master
+		  axi_rvalid <= 1'b0;
+               end                
+	  end
+     end    
+   
+   // Implement memory mapped register select and read logic generation
+   // Slave register read enable is asserted when valid address is available
+   // and the slave is ready to accept the read address.
+   assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+   always @(*)
+     begin
+	// Address decoding for reading registers
+	case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+          4'h0   : reg_data_out <= slv_reg0;
+          4'h1   : reg_data_out <= slv_reg1;
+          4'h2   : reg_data_out <= slv_reg2;
+          4'h3   : reg_data_out <= slv_reg3;
+	  4'h4   : reg_data_out <= slv_reg4;
+	  4'h5   : reg_data_out <= slv_reg5;
+	  
+          default : reg_data_out <= 0;
+	endcase
+     end
+   
+   // Output register or memory read data
+   always @( posedge S_AXI_ACLK )
+     begin
+	if ( S_AXI_ARESETN == 1'b0 )
+	  begin
+	     axi_rdata  <= 0;
+	  end 
+	else
+	  begin    
+	     // When there is a valid read address (S_AXI_ARVALID) with 
+	     // acceptance of read address by the slave (axi_arready), 
+	     // output the read dada 
+	     if (slv_reg_rden)
+               begin
+		  axi_rdata <= reg_data_out;     // register read data
+               end   
+	  end
+     end    
+   
+   // Add user logic here
+  reg spi_dir;           // Direction control for the SPI interface (1 for write, 0 for read)
+  reg [31:0] shift_out;  // SPI Data to be shifted out
+  reg [31:0] shift_in;   // SPI Data to be shifted in
+  assign spi_sdio = spi_dir ? shift_out[31] : 1'bz;
+
+   
+  // State Machine to Control the SPI Interface
+  always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
+    if (~S_AXI_ARESETN) begin
+      spi_sclk <= 0;    // keep the spi clock low
+      spi_cs_n <= 1;    // deassert the chip select line
+      spi_dir <= 1;     // start in write mode
+      shift_out <= 0;   // clear the shift out register
+      shift_in <= 0;    // clear the shift in register
+    end else begin
+      case (slv_reg2[7:0])
+        8'h00: begin
+          spi_sclk <= 0;
+          spi_cs_n <= 1;
+          spi_dir <= 1;
+          shift_out <= 0;
+        end
+        8'h01: begin
+          spi_sclk <=
+endmodule
diff --git a/HDL/cores/axi_bidrectional_spi_v1_0/core_config.tcl b/HDL/cores/axi_bidrectional_spi_v1_0/core_config.tcl
new file mode 100644
index 00000000..00c5f5c5
--- /dev/null
+++ b/HDL/cores/axi_bidrectional_spi_v1_0/core_config.tcl
@@ -0,0 +1,17 @@
+set display_name {AXI-4 Lite Bi-directional SPI Master}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter C_S_AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
+core_parameter C_S_AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core S_AXI]
+set_property NAME S_AXI $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces S_AXI_ACLK]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE S_AXI $parameter
diff --git a/HDL/cores/axis_red_pitaya_dac_v1_1/axis_red_pitaya_dac.v b/HDL/cores/axis_red_pitaya_dac_v1_1/axis_red_pitaya_dac.v
new file mode 100644
index 00000000..6d3f6d02
--- /dev/null
+++ b/HDL/cores/axis_red_pitaya_dac_v1_1/axis_red_pitaya_dac.v
@@ -0,0 +1,80 @@
+
+`timescale 1 ns / 1 ps
+
+module axis_red_pitaya_dac #
+(
+  parameter integer DAC_DATA_WIDTH = 14,
+  parameter integer AXIS_TDATA_WIDTH = 32
+)
+(
+  // PLL signals
+  input  wire                        aclk,
+  input  wire                        ddr_clk,
+  input  wire                        locked,
+
+  // DAC signals
+  output wire                        dac_clk,
+  output wire                        dac_rst,
+  output wire                        dac_sel,
+  output wire                        dac_wrt,
+  output wire [DAC_DATA_WIDTH-1:0]   dac_dat,
+
+  // Slave side
+  output wire                        s_axis_tready,
+  input  wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
+  input  wire                        s_axis_tvalid
+);
+
+  reg [DAC_DATA_WIDTH-1:0] int_dat_a_reg;
+  reg [DAC_DATA_WIDTH-1:0] int_dat_b_reg;
+  reg int_rst_reg;
+
+  wire [DAC_DATA_WIDTH-1:0] int_dat_a_wire;
+  wire [DAC_DATA_WIDTH-1:0] int_dat_b_wire;
+
+   localparam		    PAD = AXIS_TDATA_WIDTH/2 - DAC_DATA_WIDTH;
+
+  // Make sure we take the 14 MSB, not LSB 
+  assign int_dat_a_wire = s_axis_tdata[AXIS_TDATA_WIDTH/2-1:PAD];
+  assign int_dat_b_wire = s_axis_tdata[AXIS_TDATA_WIDTH-1:AXIS_TDATA_WIDTH/2+PAD];
+
+  genvar j;
+
+  always @(posedge aclk)
+  begin
+    if(~locked | ~s_axis_tvalid)
+    begin
+      int_dat_a_reg <= {(DAC_DATA_WIDTH){1'b0}};
+      int_dat_b_reg <= {(DAC_DATA_WIDTH){1'b0}};
+    end
+    else
+    begin
+      int_dat_a_reg <= {int_dat_a_wire[DAC_DATA_WIDTH-1], ~int_dat_a_wire[DAC_DATA_WIDTH-2:0]};
+      int_dat_b_reg <= {int_dat_b_wire[DAC_DATA_WIDTH-1], ~int_dat_b_wire[DAC_DATA_WIDTH-2:0]};
+    end
+    int_rst_reg <= ~locked | ~s_axis_tvalid;
+  end
+
+  ODDR ODDR_rst(.Q(dac_rst), .D1(int_rst_reg), .D2(int_rst_reg), .C(aclk), .CE(1'b1), .R(1'b0), .S(1'b0));
+  ODDR ODDR_sel(.Q(dac_sel), .D1(1'b0), .D2(1'b1), .C(aclk), .CE(1'b1), .R(1'b0), .S(1'b0));
+  ODDR ODDR_wrt(.Q(dac_wrt), .D1(1'b0), .D2(1'b1), .C(ddr_clk), .CE(1'b1), .R(1'b0), .S(1'b0));
+  ODDR ODDR_clk(.Q(dac_clk), .D1(1'b0), .D2(1'b1), .C(ddr_clk), .CE(1'b1), .R(1'b0), .S(1'b0));
+
+  generate
+    for(j = 0; j < DAC_DATA_WIDTH; j = j + 1)
+    begin : DAC_DAT
+      ODDR ODDR_inst(
+        .Q(dac_dat[j]),
+        .D1(int_dat_a_reg[j]),
+        .D2(int_dat_b_reg[j]),
+        .C(aclk),
+        .CE(1'b1),
+        .R(1'b0),
+        .S(1'b0)
+      );
+    end
+  endgenerate
+
+  assign s_axis_tready = 1'b1;
+
+endmodule
diff --git a/HDL/cores/axis_red_pitaya_dac_v1_1/core_config.tcl b/HDL/cores/axis_red_pitaya_dac_v1_1/core_config.tcl
new file mode 100644
index 00000000..d6bf45ff
--- /dev/null
+++ b/HDL/cores/axis_red_pitaya_dac_v1_1/core_config.tcl
@@ -0,0 +1,17 @@
+set display_name {AXI4-Stream Red Pitaya DAC}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the S_AXIS data bus.}
+core_parameter DAC_DATA_WIDTH {DAC DATA WIDTH} {Width of the DAC data bus.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE S_AXIS $parameter
diff --git a/HDL/projects/README.md b/HDL/projects/README.md
new file mode 100644
index 00000000..a33b9c48
--- /dev/null
+++ b/HDL/projects/README.md
@@ -0,0 +1,24 @@
+# HDL Projects
+
+This folder contains projects written in SystemVerilog and other Hardware Description Languages (HDL). Each project is organized with separate directories for simulations and testbenches.
+
+## Structure
+
+- `src/`: Source files for the HDL projects.
+- `sim/`: Simulation files and scripts.
+- `tb/`: Testbenches for verifying the HDL designs.
+
+## Getting Started
+
+1. Navigate to the project directory.
+2. Run the simulation scripts located in the `sim/` directory.
+3. Verify the design using the testbenches in the `tb/` directory.
+
+## Requirements
+
+- SystemVerilog or other HDL tools.
+- Simulation software compatible with the HDL used.
+
+## Contributing
+
+Feel free to contribute by adding new projects, improving existing ones, or updating documentation.
diff --git a/HDL/projects/async_fifo/Makefile b/HDL/projects/async_fifo/Makefile
new file mode 100644
index 00000000..cbf10209
--- /dev/null
+++ b/HDL/projects/async_fifo/Makefile
@@ -0,0 +1,21 @@
+VERILATOR = verilator
+TOP_MODULE = async_fifo
+VERILATED = obj_dir/V$(TOP_MODULE)
+
+SRC_FILES = async_fifo.sv
+CPP_FILES = main.cpp
+
+all: sim
+
+sim: $(VERILATED)
+	./$(VERILATED)
+
+$(VERILATED): $(SRC_FILES) $(CPP_FILES)
+	$(VERILATOR) -Wall --cc $(SRC_FILES) --exe $(CPP_FILES) --top-module $(TOP_MODULE) --trace --timing
+	make -C obj_dir -f V$(TOP_MODULE).mk V$(TOP_MODULE)
+
+clean:
+	rm -rf obj_dir
+	rm -f sim.vcd
+
+.PHONY: all sim clean
diff --git a/HDL/projects/async_fifo/README.md b/HDL/projects/async_fifo/README.md
new file mode 100644
index 00000000..71f154ab
--- /dev/null
+++ b/HDL/projects/async_fifo/README.md
@@ -0,0 +1,10 @@
+# async_fifo
+
+This project is to build and understand asynchronous FIFOs for clock-domain crossing. 
+
+At the same time this is also a testbed on how to leverage both verilator and Vivado techniques to generate simulations and reports on
+clock-domain crossing issues.
+
+## Requirements
+
+This project requires verilator and a tool to display the simulations. There are either gtkwave or surfer project that I would recommend.
\ No newline at end of file
diff --git a/HDL/projects/async_fifo/async_fifo.sv b/HDL/projects/async_fifo/async_fifo.sv
new file mode 100644
index 00000000..e5e02d19
--- /dev/null
+++ b/HDL/projects/async_fifo/async_fifo.sv
@@ -0,0 +1,122 @@
+module async_fifo #(
+    parameter DATA_WIDTH = 16,
+    parameter ADDR_WIDTH = 4,  // FIFO depth = 2^ADDR_WIDTH
+    parameter ALMOST_FULL_THRESHOLD = 2, // Adjust as needed
+    parameter ALMOST_EMPTY_THRESHOLD = 2 // Adjust as needed
+)(
+    input  wire                   wr_clk,
+    input  wire                   wr_rst_n,
+    input  wire [DATA_WIDTH-1:0]  wr_data,
+    input  wire                   wr_en,
+    output wire                   full,
+    output wire                   almost_full,
+
+    input  wire                   rd_clk,
+    input  wire                   rd_rst_n,
+    output wire [DATA_WIDTH-1:0]  rd_data,
+    input  wire                   rd_en,
+    output wire                   empty,
+    output wire                   almost_empty
+);
+
+    // Function to convert binary to Gray code
+    function [ADDR_WIDTH:0] binary_to_gray(input [ADDR_WIDTH:0] bin);
+        binary_to_gray = (bin >> 1) ^ bin;
+    endfunction
+
+
+    // Function to convert Gray code to binary
+    function [ADDR_WIDTH:0] gray_to_binary(input [ADDR_WIDTH:0] gray);
+        integer i;
+        begin
+            gray_to_binary[ADDR_WIDTH] = gray[ADDR_WIDTH];
+            for (i = ADDR_WIDTH-1; i >= 0; i = i - 1)
+                gray_to_binary[i] = gray[i] ^ gray_to_binary[i+1];
+        end
+    endfunction
+
+    // FIFO memory
+    reg [DATA_WIDTH-1:0] mem [0:(1<<ADDR_WIDTH)-1];
+
+    // Write and read pointers
+    reg [ADDR_WIDTH:0] wr_ptr_bin;
+    reg [ADDR_WIDTH:0] wr_ptr_gray; // the gray code version of the pointer is used for synchronization
+
+    reg [ADDR_WIDTH:0] rd_ptr_bin;
+    reg [ADDR_WIDTH:0] rd_ptr_gray; // the gray code version of the pointer is used for synchronization
+
+    // Write logic
+    always @(posedge wr_clk or negedge wr_rst_n) begin
+        if (~wr_rst_n) begin
+            wr_ptr_bin <= 0;
+            wr_ptr_gray <= 0;
+        end else if (wr_en && ~full) begin
+            mem[wr_ptr_bin[ADDR_WIDTH-1:0]] <= wr_data;
+            wr_ptr_bin <= wr_ptr_bin + 1;
+            wr_ptr_gray <= binary_to_gray(wr_ptr_bin + 1);
+        end
+    end
+
+    // Read logic
+    always @(posedge rd_clk or negedge rd_rst_n) begin
+        if (~rd_rst_n) begin
+            rd_ptr_bin <= 0;
+            rd_ptr_gray <= 0;
+        end else if (rd_en && ~empty) begin
+            rd_ptr_bin <= rd_ptr_bin + 1;
+            rd_ptr_gray <= binary_to_gray(rd_ptr_bin + 1);
+        end
+    end
+
+    assign rd_data = mem[rd_ptr_bin[ADDR_WIDTH-1:0]];
+
+    // Synchronize pointers across clock domains
+    // Use double-flop synchronizers for wr_ptr in read clock domain
+    reg [ADDR_WIDTH:0] wr_ptr_gray_rd_clk_sync1, wr_ptr_gray_rd_clk_sync2;
+    always @(posedge rd_clk or negedge rd_rst_n) begin
+        if (~rd_rst_n) begin
+            wr_ptr_gray_rd_clk_sync1 <= 0;
+            wr_ptr_gray_rd_clk_sync2 <= 0;
+        end else begin
+            wr_ptr_gray_rd_clk_sync1 <= wr_ptr_gray;
+            wr_ptr_gray_rd_clk_sync2 <= wr_ptr_gray_rd_clk_sync1;
+        end
+    end
+    wire [ADDR_WIDTH:0] wr_ptr_bin_rd_clk;
+    assign wr_ptr_bin_rd_clk = gray_to_binary(wr_ptr_gray_rd_clk_sync2);
+
+
+    // Use double-flop synchronizers for rd_ptr in write clock domain
+    reg [ADDR_WIDTH:0] rd_ptr_gray_wr_clk_sync1, rd_ptr_gray_wr_clk_sync2;
+    always @(posedge wr_clk or negedge wr_rst_n) begin
+        if (~wr_rst_n) begin
+            rd_ptr_gray_wr_clk_sync1 <= 0;
+            rd_ptr_gray_wr_clk_sync2 <= 0;
+        end else begin
+            rd_ptr_gray_wr_clk_sync1 <= rd_ptr_gray;
+            rd_ptr_gray_wr_clk_sync2 <= rd_ptr_gray_wr_clk_sync1;
+        end
+    end
+    wire [ADDR_WIDTH:0] rd_ptr_bin_wr_clk;
+    assign rd_ptr_bin_wr_clk = gray_to_binary(rd_ptr_gray_wr_clk_sync2);
+
+    // Generate full and empty flags
+    assign full = ( (wr_ptr_bin[ADDR_WIDTH] != rd_ptr_bin_wr_clk[ADDR_WIDTH]) &&
+                (wr_ptr_bin[ADDR_WIDTH-1:0] == rd_ptr_bin_wr_clk[ADDR_WIDTH-1:0]) );
+
+    assign empty = (rd_ptr_bin == wr_ptr_bin_rd_clk);
+
+    // ALMOST FULL calculation is done in write clock domain
+    wire [ADDR_WIDTH:0] fifo_count_wr_clk;
+    assign fifo_count_wr_clk = wr_ptr_bin - rd_ptr_bin_wr_clk;
+
+    // since the ptrs wrap circularily we need to be very careful with the subtractions. Best to have a test
+    assign almost_full = (fifo_count_wr_clk >= ((1 << ADDR_WIDTH) - ALMOST_FULL_THRESHOLD));
+
+    // ALMOST EMPTY calculation is done in read clock domain
+    wire [ADDR_WIDTH:0] fifo_count_rd_clk;
+    assign fifo_count_rd_clk = wr_ptr_bin_rd_clk - rd_ptr_bin;
+
+    assign almost_empty = (fifo_count_rd_clk <= ALMOST_EMPTY_THRESHOLD);
+
+endmodule
diff --git a/HDL/projects/async_fifo/main.cpp b/HDL/projects/async_fifo/main.cpp
new file mode 100644
index 00000000..c0b40f8f
--- /dev/null
+++ b/HDL/projects/async_fifo/main.cpp
@@ -0,0 +1,131 @@
+// main.cpp
+#include "Vasync_fifo.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include <iostream>
+#include <fstream>
+
+int main(int argc, char **argv)
+{
+    Verilated::commandArgs(argc, argv);
+
+    // Instantiate the top module
+    Vasync_fifo *top = new Vasync_fifo;
+
+    // Initialize simulation inputs
+    top->wr_clk = 0;
+    top->rd_clk = 0;
+    top->wr_rst_n = 0;
+    top->rd_rst_n = 0;
+    top->wr_en = 0;
+    top->rd_en = 0;
+
+    // Variables for simulation
+    vluint64_t main_time = 0;           // Current simulation time
+    const vluint64_t sim_time = 4000000; // Adjust as needed
+
+    // Open VCD dump file
+    Verilated::traceEverOn(true);
+    VerilatedVcdC *tfp = new VerilatedVcdC;
+    top->trace(tfp, 99); // Trace 99 levels of hierarchy
+    tfp->open("sim.vcd");
+
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->wr_clk = !top->wr_clk;
+        top->rd_clk = !top->rd_clk;
+        top->eval();
+        tfp->dump(main_time);
+        main_time++;
+    }
+    top->wr_rst_n = 1;
+    top->rd_rst_n = 1;
+
+    uint16_t write_count = 0;
+    uint16_t read_count = 0;
+    uint16_t expected_data = 0;
+    uint16_t wr_data = 0;
+    bool prev_wr_clk = 0;
+    bool prev_rd_clk = 0;
+
+    while (main_time < sim_time)
+    {
+        // Toggle clocks
+        if ((main_time % 5) == 0)
+        {
+            top->wr_clk = !top->wr_clk;
+        }
+        if ((main_time % 7) == 0)
+        {
+            top->rd_clk = !top->rd_clk;
+        }
+
+        // Write process
+        if (top->wr_clk && !prev_wr_clk)
+        { // Rising edge of wr_clk
+            if (main_time > 20)
+            { // After reset
+                if (!top->full)
+                {
+                    top->wr_en = 1;
+                    top->wr_data = wr_data;
+                    wr_data++;
+                    write_count++;
+                }
+                else
+                {
+                    top->wr_en = 0;
+                }
+            }
+        }
+        prev_wr_clk = top->wr_clk;
+
+        // Read process
+        if (top->rd_clk && !prev_rd_clk)
+        { // Rising edge of rd_clk
+            if (main_time > 20)
+            { // After reset
+                if (!top->empty)
+                {
+                    top->rd_en = 1;
+                }
+                else
+                {
+                    top->rd_en = 0;
+                }
+
+                // Data integrity check
+                if (top->rd_en && !top->empty)
+                {
+                    if (top->rd_data != expected_data)
+                    {
+                        std::cout << "ERROR: Data Mismatch at time " << main_time
+                                  << ": Expected " << expected_data << ", Got " << top->rd_data << std::endl;
+                        exit(1);
+                    }
+                    expected_data++;
+                    read_count++;
+                }
+            }
+        }
+        prev_rd_clk = top->rd_clk;
+
+        // Check for simulation end
+        if (write_count >= 500 && read_count >= 500)
+        {
+            std::cout << "Simulation completed successfully at time " << main_time << std::endl;
+            break;
+        }
+
+        top->eval();          // Evaluate model
+        tfp->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+
+    // Cleanup
+    tfp->close();
+    delete top;
+    return 0;
+}
diff --git a/HDL/projects/async_fifo/tb_async_fifo.sv b/HDL/projects/async_fifo/tb_async_fifo.sv
new file mode 100644
index 00000000..409a537b
--- /dev/null
+++ b/HDL/projects/async_fifo/tb_async_fifo.sv
@@ -0,0 +1,137 @@
+module tb_async_fifo;
+
+    // Parameters
+    parameter DATA_WIDTH = 16;
+    parameter ADDR_WIDTH = 4; // FIFO depth = 2^ADDR_WIDTH
+
+    // Signals
+    reg                    wr_clk;
+    reg                    wr_rst_n;
+    reg [DATA_WIDTH-1:0]   wr_data;
+    reg                    wr_en;
+    wire                   full;
+
+    reg                    rd_clk;
+    reg                    rd_rst_n;
+    wire [DATA_WIDTH-1:0]  rd_data;
+    reg                    rd_en;
+    wire                   empty;
+
+    integer                write_count;
+    integer                read_count;
+    reg [DATA_WIDTH-1:0]   expected_data;
+
+    // Instantiate the FIFO
+    async_fifo  #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .ADDR_WIDTH(ADDR_WIDTH)
+    ) fifo_inst (
+        .wr_clk     (wr_clk),
+        .wr_rst_n   (wr_rst_n),
+        .wr_data    (wr_data),
+        .wr_en      (wr_en),
+        .full       (full),
+        .rd_clk     (rd_clk),
+        .rd_rst_n   (rd_rst_n),
+        .rd_data    (rd_data),
+        .rd_en      (rd_en),
+        .empty      (empty)
+    );
+
+    // Clock generation
+    initial begin
+        wr_clk = 0;
+        forever #5 wr_clk = ~wr_clk; // 100 MHz clock
+    end
+
+    initial begin
+        rd_clk = 0;
+        forever #7 rd_clk = ~rd_clk; // Approximately 71.4 MHz clock
+    end
+
+    // Reset generation
+    initial begin
+        wr_rst_n = 0;
+        rd_rst_n = 0;
+        #20;
+        wr_rst_n = 1;
+        rd_rst_n = 1;
+    end
+
+    // Write process
+    initial begin
+        wr_en = 0;
+        wr_data = 0;
+        write_count = 0;
+        @(posedge wr_rst_n);
+        @(posedge wr_clk);
+
+        // Write data until a certain count
+        while (write_count < 50) begin
+            @(posedge wr_clk);
+            if (!full) begin
+                wr_en = 1;
+                wr_data = write_count[DATA_WIDTH-1:0];
+                write_count = write_count + 1;
+            end else begin
+                wr_en = 0;
+            end
+        end
+        wr_en = 0;
+    end
+
+    // Read process
+    initial begin
+        rd_en = 0;
+        expected_data = 0;
+        read_count = 0;
+        @(posedge rd_rst_n);
+        @(posedge rd_clk);
+
+        // Read data until all written data is read
+        while (read_count < 50) begin
+            @(posedge rd_clk);
+            if (!empty) begin
+                rd_en = 1;
+            end else begin
+                rd_en = 0;
+            end
+        end
+        rd_en = 0;
+    end
+
+    // Data integrity check
+    always @(posedge rd_clk) begin
+        if (rd_en && !empty) begin
+            if (rd_data !== expected_data) begin
+                $display("ERROR: Data Mismatch at time %t: Expected %0d, Got %0d", $time, expected_data, rd_data);
+                $stop;
+            end else begin
+                expected_data <= expected_data + 1;
+                read_count <= read_count + 1;
+            end
+        end
+    end
+
+    // Monitor full and empty flags
+    always @(posedge wr_clk) begin
+        if (full && wr_en) begin
+            $display("INFO: FIFO is full at time %t", $time);
+        end
+    end
+
+    always @(posedge rd_clk) begin
+        if (empty && rd_en) begin
+            $display("INFO: FIFO is empty at time %t", $time);
+        end
+    end
+
+    // Terminate simulation
+    initial begin
+        wait (write_count == 50 && read_count == 50);
+        #100; // Wait for any remaining activity
+        $display("Simulation completed successfully at time %t", $time);
+        $stop;
+    end
+
+endmodule
diff --git a/HDL/projects/half_duplex_spi_master/Makefile b/HDL/projects/half_duplex_spi_master/Makefile
new file mode 100644
index 00000000..b10d6ad5
--- /dev/null
+++ b/HDL/projects/half_duplex_spi_master/Makefile
@@ -0,0 +1,38 @@
+VERILATOR = verilator
+TOP_MODULE = half_duplex_spi_master_clkdiv
+VERILATED = obj_dir/V$(TOP_MODULE)
+
+SRC_FILES = half_duplex_spi_master_clkdiv.sv half_duplex_spi_master.sv ../async_fifo/async_fifo.sv ../reset_synchronizer/reset_synchronizer.sv ../quadrature_clock_divider/quadrature_clock_divider.sv
+CPP_FILES = half_duplex_spi_master_tb.cpp
+
+all: sim
+
+sim: $(VERILATED)
+	./$(VERILATED)
+
+$(VERILATED): $(SRC_FILES) $(CPP_FILES)
+	$(VERILATOR) -Wall --cc $(SRC_FILES) --exe $(CPP_FILES) --top-module $(TOP_MODULE) --trace --timing
+	make -C obj_dir -f V$(TOP_MODULE).mk V$(TOP_MODULE)
+
+clean:
+	rm -rf obj_dir
+	rm -f sim.vcd
+	rm -f sim_reset_n_clock.vcd
+	rm -f sim_load_value_32w_mode0.vcd
+	rm -f sim_load_value_32w_mode1.vcd
+	rm -f sim_load_value_32w_mode2.vcd
+	rm -f sim_load_value_32w_mode3.vcd
+	rm -f sim_load_value_mode0.vcd
+	rm -f sim_load_value_mode1.vcd
+	rm -f sim_load_value_mode2.vcd
+	rm -f sim_load_value_mode3.vcd
+	rm -f sim_load_value_24w_8r_mode0.vcd
+	rm -f sim_load_value_24w_8r_mode1.vcd
+	rm -f sim_load_value_24w_8r_mode2.vcd
+	rm -f sim_load_value_24w_8r_mode3.vcd
+	rm -f sim_load_value_24r_8w_mode0.vcd
+	rm -f sim_load_value_24r_8w_mode1.vcd
+	rm -f sim_load_value_24r_8w_mode2.vcd
+	rm -f sim_load_value_24r_8w_mode3.vcd
+
+.PHONY: all sim clean
diff --git a/HDL/projects/half_duplex_spi_master/TODO.md b/HDL/projects/half_duplex_spi_master/TODO.md
new file mode 100644
index 00000000..b45e5e92
--- /dev/null
+++ b/HDL/projects/half_duplex_spi_master/TODO.md
@@ -0,0 +1,17 @@
+Important issues remaining on this core
+- [x] Reading doesn't shift into correct bits (off by one) (done)
+- [x] To fabric FIFO transfer does not finish due to possible reset (done)
+- [ ] Asserts in test bench (not done)
+- [x] correct bit-lengths for transaction length and bit counters (done)
+- [x] remove dual clock approach and replace with simple single clock (done)
+- [x] make a separate module with built-in clock-divider for the verilator tests (done)
+- [ ] check all the reset conditions (not done)
+- [x] fix the input shift register shifts when writing out (done)
+- [x] make sure SPI modes cannot be changed in the middle of transactions etc (done)
+- [ ] remove unnecessary registers (not done)
+- [ ] check for unnecessary priority encoders (not done)
+- [ ] change the state machine to follow standard pattern (not done)
+- [ ] implement and test error detection (not done)
+- [ ] bring a busy flag to the fabric domain using a double flop synchronizer (not done)
+- [x] rewrite to use a FSM running on double clock speed to only have positive edge sensitivity (not done)
+- [ ] rewrite logic so that for sure only 1 read value is written to the fabric fifo (not done)
\ No newline at end of file
diff --git a/HDL/projects/half_duplex_spi_master/half_duplex_spi_master.sv b/HDL/projects/half_duplex_spi_master/half_duplex_spi_master.sv
new file mode 100644
index 00000000..ff8094f7
--- /dev/null
+++ b/HDL/projects/half_duplex_spi_master/half_duplex_spi_master.sv
@@ -0,0 +1,385 @@
+// half_duplex_spi_master module
+// This module implements a half-duplex (bidirectional) SPI master interface with the following features:
+// - uses a mask to determine which bits are written or read
+// - supports all four SPI modes (CPOL=0, CPHA=0; CPOL=0, CPHA=1; CPOL=1, CPHA=0; CPOL=1, CPHA=1)
+// - supports configurable data width
+// - supports input of an arbitary spi clock
+// - raise an error flag if invalid parameters are used
+// Half-duplex SPI is an interface where the data can be written and read using a single wire.
+module half_duplex_spi_master #(
+  parameter DATA_WIDTH = 32,
+  parameter TRANSACTION_LEN_WIDTH = 6
+)(
+    input wire [TRANSACTION_LEN_WIDTH-1:0]  transaction_length,
+    input wire [DATA_WIDTH-1:0] transaction_data,
+    input wire [DATA_WIDTH-1:0] transaction_rw_mask,
+    output reg [DATA_WIDTH-1:0] transaction_read_data,
+
+    input wire reset_n,
+    input wire fabric_clk,
+    input wire spi_clk_in,
+
+    // SPI Mode control
+    input wire spi_cpol,   // Clock polarity
+    input wire spi_cpha,   // Clock phase
+
+    // The 3-wire output
+    inout wire spi_sdio,
+    output reg spi_sclk,
+    output reg spi_cs_n
+);
+
+  reg spi_dir;           // Direction control for the SPI interface (1 for write, 0 for read)
+  reg shift_out;  // SPI Data to be shifted out
+  reg r_spi_cpol, r_spi_cpha, spi_cpol_sc, spi_cpha_sc;
+
+  localparam BIT_COUNT_WIDTH = $clog2(DATA_WIDTH);
+
+  // Some of our data in the spi_clk domain
+  reg [TRANSACTION_LEN_WIDTH-1:0] r_transaction_length;
+  reg [BIT_COUNT_WIDTH:0] bitcounter_sc, read_bitcounter_sc;
+
+  //reg [DATA_WIDTH-1:0] transaction_rw_mask_sc
+  reg [DATA_WIDTH-1:0] r_transaction_rw_mask;
+  //reg [DATA_WIDTH-1:0] transaction_data_sc, 
+  reg [DATA_WIDTH-1:0] r_transaction_data;
+  reg [DATA_WIDTH-1:0] r_transaction_read_data, f_transaction_read_data;
+
+  reg [2+TRANSACTION_LEN_WIDTH+DATA_WIDTH+DATA_WIDTH-1:0] sc_data, fc_data;
+
+  reg [DATA_WIDTH-1:0] transaction_read_data_sc;
+  
+  assign fc_data = {r_spi_cpol, r_spi_cpha, r_transaction_length, r_transaction_rw_mask, r_transaction_data};
+
+  assign spi_sdio = spi_dir ? shift_out : 1'bz;
+
+  assign transaction_read_data = r_transaction_read_data;
+
+  wire spi_clk;
+
+  reg to_spi_fifo_empty;
+
+  // fabric side state machine states
+  typedef enum logic [1:0] {
+    F_IDLE,     
+    F_WRITE,
+    F_READ,
+    F_DONE
+  } fstate_t;
+
+  fstate_t fabric_state;
+
+  // Fabric side state machine
+  always @(posedge fabric_clk or negedge reset_n) begin
+    if (~reset_n) begin
+      to_spi_fifo_wr_en <= 1'b0;
+      to_fabric_fifo_rd_en <= 1'b0;
+      fabric_state <= F_IDLE;
+      r_transaction_length <= 0;
+      r_transaction_rw_mask <= 0;
+      r_transaction_data <= 0;
+      r_spi_cpol <= 0;
+      r_spi_cpha <= 0;
+    end else if (fabric_state == F_IDLE) begin
+      if (transaction_length > 0) begin
+        fabric_state <= F_WRITE;
+        to_spi_fifo_wr_en <= 1'b1;
+        r_transaction_length <= transaction_length;
+        r_transaction_rw_mask <= transaction_rw_mask;
+        r_transaction_data <= transaction_data;
+        r_spi_cpol <= spi_cpol;
+        r_spi_cpha <=  spi_cpha;
+      end else begin
+        fabric_state <= F_IDLE;
+      end
+      // check if there is something to read
+      if (~to_fabric_fifo_empty) begin
+        to_fabric_fifo_rd_en <= 1'b1;
+        fabric_state <= F_READ;
+      end else begin
+        to_fabric_fifo_rd_en <= 1'b0;
+      end
+    end else if (fabric_state == F_WRITE) begin
+      fabric_state <= F_IDLE;
+      to_spi_fifo_wr_en <= 1'b0;
+    end else if (fabric_state == F_READ) begin
+      to_fabric_fifo_rd_en <= 1'b0;
+      fabric_state <= F_IDLE;
+      // should also copy the data from the FIFO
+      r_transaction_read_data <= f_transaction_read_data;
+    end
+  end
+
+  // Reset synchronizer
+  wire reset_n_sc;
+
+  reset_synchronizer reset_sync (
+    .reset_n(reset_n),
+    .clk(spi_clk),
+    .sync_reset_n(reset_n_sc)
+  );
+  
+  // I know this is super hacky, but it allows the logic below to look cleaner
+  assign spi_clk = spi_cpol_sc ? ~spi_clk_in : spi_clk_in;
+
+  reg to_spi_fifo_rd_en, to_spi_fifo_wr_en;
+  // Instantiate the asynchronous FIFO for the data going to the SPI side
+  async_fifo #(
+    .DATA_WIDTH(2+TRANSACTION_LEN_WIDTH+2*DATA_WIDTH),
+    .ADDR_WIDTH(3)
+  ) to_spi_fifo (
+    .wr_clk(fabric_clk),
+    .wr_rst_n(reset_n),
+    .wr_data(fc_data),
+    .wr_en(to_spi_fifo_wr_en),
+    .rd_clk(spi_clk),
+    .rd_rst_n(reset_n),
+    .rd_data(sc_data),
+    .rd_en(to_spi_fifo_rd_en),
+    .empty(to_spi_fifo_empty),
+    /* verilator lint_off PINCONNECTEMPTY */
+    .almost_empty(),
+    .full(),
+    .almost_full()
+    /* verilator lint_on PINCONNECTEMPTY */ 
+  );
+
+  reg to_fabric_fifo_full, to_fabric_fifo_empty, to_fabric_fifo_wr_en, to_fabric_fifo_rd_en;
+
+  // Instantiate the asynchronous FIFO for the data coming from the SPI side
+  async_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(3)
+  ) to_fabric_fifo (
+    .wr_clk(spi_clk),
+    .wr_rst_n(reset_n),
+    .wr_data(transaction_read_data_sc),
+    .wr_en(to_fabric_fifo_wr_en),
+    .rd_clk(fabric_clk),
+    .rd_rst_n(reset_n),
+    .rd_data(f_transaction_read_data),
+    .rd_en(to_fabric_fifo_rd_en),
+    .full(to_fabric_fifo_full),
+    .empty(to_fabric_fifo_empty),
+    /* verilator lint_off PINCONNECTEMPTY */
+    .almost_empty(),
+    .almost_full()
+    /* verilator lint_on PINCONNECTEMPTY */ 
+  );
+
+  // SPI state machine stuff
+  typedef enum logic [2:0] {
+    IDLE,
+    FIFO_READ,     
+    CS_ASSERT,
+    READ,
+    WRITE,
+    DONE,
+    FIFO_WRITE
+  } state_t;
+
+  /* verilator lint_off UNUSEDSIGNAL */
+  state_t spi_state, next_spi_state;
+  /* verilator lint_on UNUSEDSIGNAL */
+
+  // combinatorial logic to assign the SPI clock
+  assign spi_sclk = spi_clock_hot ? (spi_cpol_sc ? ~odd_strobe : odd_strobe) : spi_cpol_sc;
+
+  reg spi_clock_hot;
+  reg [DATA_WIDTH-1:0] shiftout_register, rw_shift_register, shiftin_register;
+
+  assign transaction_read_data_sc = shiftin_register;
+
+  // the even-odd strobe 
+  reg eotoggle;
+  wire even_strobe, odd_strobe;
+  assign even_strobe = ~eotoggle;
+  assign odd_strobe = eotoggle;
+
+  always @(posedge spi_clk or negedge reset_n_sc) begin
+    if (~reset_n_sc) begin
+      eotoggle <= 1'b0;
+    end else begin
+      eotoggle <= ~eotoggle;
+    end
+  end
+
+  // traditional FSM pattern
+
+  always_comb begin
+    next_spi_state = spi_state;
+
+    case (spi_state)
+      IDLE: begin
+        if(~to_spi_fifo_empty) next_spi_state = FIFO_READ;
+      end
+
+      FIFO_READ: begin
+        next_spi_state = CS_ASSERT;
+      end
+
+      CS_ASSERT: begin
+        if (rw_shift_register[DATA_WIDTH-1]) begin
+          next_spi_state = WRITE;
+        end else begin
+          next_spi_state = READ;
+        end
+      end
+
+      WRITE: begin
+        if (bitcounter_sc == 0) begin
+          next_spi_state = DONE;
+        end else if (~rw_shift_register[DATA_WIDTH-1]) begin
+          next_spi_state = READ;
+        end
+      end
+
+      READ: begin
+        if (bitcounter_sc == 0) begin
+          next_spi_state = DONE;
+        end else if (rw_shift_register[DATA_WIDTH-1]) begin
+          next_spi_state = WRITE;
+        end
+      end
+
+      DONE: begin
+        if (read_bitcounter_sc == 0 || to_fabric_fifo_full) begin
+          next_spi_state = IDLE;
+        end else begin
+          next_spi_state = FIFO_WRITE;
+        end
+      end
+
+      FIFO_WRITE: next_spi_state = IDLE;
+
+      default: next_spi_state = IDLE;
+    endcase
+  end
+
+  always_ff @(posedge spi_clk or negedge reset_n_sc) begin
+    if (~reset_n_sc) begin
+      spi_dir <= 1'b1;
+      shift_out <= 1'b0;
+      spi_cs_n <= 1'b1;
+      to_spi_fifo_rd_en <= 1'b0;
+      to_fabric_fifo_wr_en <= 1'b0;
+      spi_state <= IDLE;
+      spi_clock_hot <= 1'b0;
+      read_bitcounter_sc <= 0;
+      shiftin_register <= 0;
+      // pickup the mode on reset
+      spi_cpol_sc <= spi_cpol;
+      spi_cpha_sc <= spi_cpha;
+    end else begin
+      if (spi_state == IDLE) begin
+        to_fabric_fifo_wr_en <= 1'b0;
+        shift_out <= 1'b0;
+        spi_cs_n <= 1'b1;
+        read_bitcounter_sc <= 0;
+        shiftin_register <= 0;
+        if(~to_spi_fifo_empty) begin
+          spi_state <= FIFO_READ;
+          to_spi_fifo_rd_en <= 1'b1; // assert the read enable
+         end else begin
+          spi_state <= IDLE;
+         end
+      end else if (spi_state == FIFO_READ) begin
+        spi_state <= CS_ASSERT;
+        to_spi_fifo_rd_en <= 1'b0; // deassert the read enable
+        // copy the data from the fifo
+        spi_cpol_sc <= sc_data[TRANSACTION_LEN_WIDTH+DATA_WIDTH+DATA_WIDTH+1];
+        spi_cpha_sc <= sc_data[TRANSACTION_LEN_WIDTH+DATA_WIDTH+DATA_WIDTH];
+        bitcounter_sc <= sc_data[TRANSACTION_LEN_WIDTH+DATA_WIDTH+DATA_WIDTH-1:DATA_WIDTH+DATA_WIDTH];
+        shiftout_register <= sc_data[DATA_WIDTH-1:0];
+        rw_shift_register <= sc_data[DATA_WIDTH+DATA_WIDTH-1:DATA_WIDTH];
+      end else if (spi_state == CS_ASSERT) begin
+        if (rw_shift_register[DATA_WIDTH-1]) begin
+          spi_state <= WRITE;
+        end else begin
+          spi_state <= READ;
+        end
+        spi_cs_n <= 1'b0;
+        spi_clock_hot <= 1'b1;
+
+        // deal with the write case for Mode 0 & 2, I doubt there is a read case here
+        // at all directly after CS is asserted
+        if (odd_strobe && ~spi_cpha_sc && spi_dir) begin
+          spi_dir <= rw_shift_register[DATA_WIDTH-1];
+          rw_shift_register <= {rw_shift_register[DATA_WIDTH-2:0], 1'b0};
+
+          shift_out <= shiftout_register[DATA_WIDTH-1];
+          shiftout_register <= {shiftout_register[DATA_WIDTH-2:0],1'b0};
+          shiftin_register <= {shiftin_register[DATA_WIDTH-2:0],1'b0};
+          if (spi_dir == rw_shift_register[DATA_WIDTH-1]) begin
+            bitcounter_sc <= bitcounter_sc - 1;
+          end
+        end
+
+      end else if (spi_state == WRITE) begin
+        if (bitcounter_sc == 0) begin
+          spi_state <= DONE;
+        end else begin
+          spi_state <= WRITE;
+        end
+
+        // all valid transitions that advance the state machine
+        if ((even_strobe && spi_cpha_sc) || (odd_strobe && ~spi_cpha_sc)) begin
+          spi_dir <= rw_shift_register[DATA_WIDTH-1];
+          rw_shift_register <= {rw_shift_register[DATA_WIDTH-2:0], 1'b0};
+          if (rw_shift_register[DATA_WIDTH-1]) begin
+            // only decrement when direction stays the same
+            bitcounter_sc <= bitcounter_sc - 1;
+          end else begin
+            spi_state <= READ;
+          end
+        end
+
+        if (((even_strobe && spi_cpha_sc) || (odd_strobe && ~spi_cpha_sc)) && rw_shift_register[DATA_WIDTH-1]) begin  
+          shift_out <= shiftout_register[DATA_WIDTH-1];
+          shiftout_register <= {shiftout_register[DATA_WIDTH-2:0],1'b0};
+          shiftin_register <= {shiftin_register[DATA_WIDTH-2:0],1'b0};
+        end 
+
+      end else if (spi_state == READ) begin
+        if (bitcounter_sc == 0) begin
+          spi_state <= DONE;
+        end else begin
+          spi_state <= READ;
+        end
+
+        if ((even_strobe && ~spi_cpha_sc) || (odd_strobe && spi_cpha_sc)) begin
+          read_bitcounter_sc <= read_bitcounter_sc + 1;
+          shiftin_register <= {shiftin_register[DATA_WIDTH-2:0],1'b1};
+          bitcounter_sc <= bitcounter_sc - 1;
+          if (~rw_shift_register[DATA_WIDTH-1]) begin
+            spi_dir <= rw_shift_register[DATA_WIDTH-1];
+            rw_shift_register <= {rw_shift_register[DATA_WIDTH-2:0], 1'b0};
+          end else begin
+            spi_state <= WRITE;
+          end
+        end
+
+      end else if (spi_state == DONE) begin
+        if (even_strobe) begin
+          shift_out <= 1'b0;
+          spi_clock_hot <= 1'b0;
+          spi_dir <= 1'b1;
+          spi_cs_n <= 1'b1;
+          if (read_bitcounter_sc == 0 || to_fabric_fifo_full) begin
+            spi_state <= IDLE;
+            to_fabric_fifo_wr_en <= 1'b0;
+          end else begin
+            spi_state <= FIFO_WRITE;
+            to_fabric_fifo_wr_en <= 1'b1;
+          end          
+        end
+      end else if (spi_state == FIFO_WRITE) begin
+        if (even_strobe) begin
+          spi_state <= IDLE;
+          to_fabric_fifo_wr_en <= 1'b0;
+        end
+      end
+    end
+  end
+
+  endmodule
diff --git a/HDL/projects/half_duplex_spi_master/half_duplex_spi_master_clkdiv.sv b/HDL/projects/half_duplex_spi_master/half_duplex_spi_master_clkdiv.sv
new file mode 100644
index 00000000..128e2a10
--- /dev/null
+++ b/HDL/projects/half_duplex_spi_master/half_duplex_spi_master_clkdiv.sv
@@ -0,0 +1,56 @@
+/* a top level module with built-in clock divider */
+module half_duplex_spi_master_clkdiv #(
+  parameter DATA_WIDTH = 32,
+  parameter TRANSACTION_LEN_WIDTH = 6,
+  parameter CLOCK_DIVIDER = 1
+)(
+    input wire [TRANSACTION_LEN_WIDTH-1:0]  transaction_length,
+    input wire [DATA_WIDTH-1:0] transaction_data,
+    input wire [DATA_WIDTH-1:0] transaction_rw_mask,
+    output reg [DATA_WIDTH-1:0] transaction_read_data,
+
+    input wire reset_n,
+    input wire fabric_clk,
+
+    // SPI Mode control
+    input wire spi_cpol,   // Clock polarity
+    input wire spi_cpha,   // Clock phase
+
+    inout wire spi_sdio,
+    output reg spi_sclk,
+    output reg spi_cs_n
+);
+
+wire spi_clk_gen;
+
+// Generate the clocks
+quadrature_clock_divider clock_div (
+  .reset_n(reset_n),
+  .clk_in(fabric_clk),
+  .div_factor_4(CLOCK_DIVIDER),
+  .sck_0(spi_clk_gen),
+  /* verilator lint_off PINCONNECTEMPTY */
+  .sck_90()
+  /* verilator lint_on PINCONNECTEMPTY */
+  );
+
+// Instantiate the spi_master core
+half_duplex_spi_master #(
+  .DATA_WIDTH(DATA_WIDTH), .TRANSACTION_LEN_WIDTH(TRANSACTION_LEN_WIDTH)
+) hdsm (
+  .transaction_length(transaction_length),
+  .transaction_data(transaction_data),
+  .transaction_rw_mask(transaction_rw_mask),
+  .transaction_read_data(transaction_read_data),
+  .reset_n(reset_n),
+  .fabric_clk(fabric_clk),
+  .spi_clk_in(spi_clk_gen),
+  .spi_cpol(spi_cpol),
+  .spi_cpha(spi_cpha), 
+
+  .spi_sdio(spi_sdio),
+  .spi_sclk(spi_sclk),
+  .spi_cs_n(spi_cs_n)
+);
+
+endmodule
diff --git a/HDL/projects/half_duplex_spi_master/half_duplex_spi_master_tb.cpp b/HDL/projects/half_duplex_spi_master/half_duplex_spi_master_tb.cpp
new file mode 100644
index 00000000..72e68b2c
--- /dev/null
+++ b/HDL/projects/half_duplex_spi_master/half_duplex_spi_master_tb.cpp
@@ -0,0 +1,833 @@
+// main.cpp
+#include "Vhalf_duplex_spi_master_clkdiv.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include <iostream>
+#include <fstream>
+
+int main(int argc, char **argv)
+{
+    Verilated::commandArgs(argc, argv);
+
+    // Instantiate the top module
+    Vhalf_duplex_spi_master_clkdiv *top = new Vhalf_duplex_spi_master_clkdiv;
+
+    // Initialize simulation inputs
+    top->transaction_length = 0;
+    top->transaction_data = 0;
+    top->transaction_rw_mask = 0;
+    top->transaction_read_data = 0;
+    top->reset_n = 0;
+    top->fabric_clk = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    top->spi_sdio = 0;
+
+    // Variables for simulation
+    vluint64_t main_time = 0;                      // Current simulation time
+    const vluint64_t sim_time_reset_n_clock = 100; // Adjust as needed
+    const vluint64_t sim_load_value_fifo = 600;    // Adjust as needed
+    const vluint64_t sim_load_value_fifo_32 = 700; // Adjust as needed
+
+    // Open VCD dump file
+    Verilated::traceEverOn(true);
+    VerilatedVcdC *tfp = new VerilatedVcdC;
+    VerilatedVcdC *tfp2 = new VerilatedVcdC;
+    VerilatedVcdC *tfp3 = new VerilatedVcdC;
+    VerilatedVcdC *tfp4 = new VerilatedVcdC;
+    VerilatedVcdC *tfp5 = new VerilatedVcdC;
+    VerilatedVcdC *tfp6 = new VerilatedVcdC;
+    VerilatedVcdC *tfp7 = new VerilatedVcdC;
+    VerilatedVcdC *tfp8 = new VerilatedVcdC;
+    VerilatedVcdC *tfp9 = new VerilatedVcdC;
+    VerilatedVcdC *tfp10 = new VerilatedVcdC;
+    VerilatedVcdC *tfp11 = new VerilatedVcdC;
+    VerilatedVcdC *tfp12 = new VerilatedVcdC;
+    VerilatedVcdC *tfp13 = new VerilatedVcdC;
+    VerilatedVcdC *tfp14 = new VerilatedVcdC;
+    VerilatedVcdC *tfp15 = new VerilatedVcdC;
+    VerilatedVcdC *tfp16 = new VerilatedVcdC;
+    VerilatedVcdC *tfp17 = new VerilatedVcdC;
+    VerilatedVcdC *tfp18 = new VerilatedVcdC;
+    VerilatedVcdC *tfp19 = new VerilatedVcdC;
+    VerilatedVcdC *tfp20 = new VerilatedVcdC;
+    
+    top->trace(tfp, 99); // Trace 99 levels of hierarchy
+    tfp->open("sim_reset_n_clock.vcd");
+    top->reset_n = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_time_reset_n_clock)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();          // Evaluate model
+        tfp->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+
+    // Cleanup sim file
+    tfp->close();
+
+    top->trace(tfp2, 99); // Trace 99 levels of hierarchy
+    tfp2->open("sim_load_value_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp2->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 24;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x00FFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp2->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp2->close();
+
+    top->trace(tfp3, 99); // Trace 99 levels of hierarchy
+    tfp3->open("sim_load_value_mode1.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp3->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 24;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x00FFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp3->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp3->close();
+
+    top->trace(tfp4, 99); // Trace 99 levels of hierarchy
+    tfp4->open("sim_load_value_mode2.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 0;
+
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp4->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 24;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x00FFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp4->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp4->close();
+
+    top->trace(tfp5, 99); // Trace 99 levels of hierarchy
+    tfp5->open("sim_load_value_mode3.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp5->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 24;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x00FFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp5->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp5->close();
+
+    top->trace(tfp6, 99); // Trace 99 levels of hierarchy
+    tfp6->open("sim_load_value_32w_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp6->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp6->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp6->close();
+
+    top->trace(tfp7, 99); // Trace 99 levels of hierarchy
+    tfp7->open("sim_load_value_24w_8r_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp7->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFF00;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp7->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp7->close();
+
+    top->trace(tfp8, 99); // Trace 99 levels of hierarchy
+    tfp8->open("sim_load_value_24w_8r_mode1.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp8->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFF00;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp8->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp8->close();
+
+    top->trace(tfp9, 99); // Trace 99 levels of hierarchy
+    tfp9->open("sim_load_value_24w_8r_mode2.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp9->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFF00;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp9->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp9->close();
+
+    top->trace(tfp10, 99); // Trace 99 levels of hierarchy
+    tfp10->open("sim_load_value_24w_8r_mode3.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp10->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFF00;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp10->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp10->close();
+
+    /* this test case is unrealistic, as reading before writing doesn't make any
+       sense in most practical scenarios, nevertheless it should work */
+    top->trace(tfp11, 99); // Trace 99 levels of hierarchy
+    tfp11->open("sim_load_value_24r_8w_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp11->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x000000FF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp11->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp11->close();
+
+    top->trace(tfp15, 99); // Trace 99 levels of hierarchy
+    tfp15->open("sim_load_value_24r_8w_mode1.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp15->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x000000FF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp15->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp15->close();
+
+    top->trace(tfp16, 99); // Trace 99 levels of hierarchy
+    tfp16->open("sim_load_value_24r_8w_mode2.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp16->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x000000FF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp16->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp16->close();
+
+    top->trace(tfp17, 99); // Trace 99 levels of hierarchy
+    tfp17->open("sim_load_value_24r_8w_mode3.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp17->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0x000000FF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp17->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp17->close();
+
+    top->trace(tfp12, 99); // Trace 99 levels of hierarchy
+    tfp12->open("sim_load_value_32w_mode1.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp12->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp12->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp12->close();
+
+    top->trace(tfp13, 99); // Trace 99 levels of hierarchy
+    tfp13->open("sim_load_value_32w_mode2.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp13->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp13->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp13->close();
+
+    top->trace(tfp14, 99); // Trace 99 levels of hierarchy
+    tfp14->open("sim_load_value_32w_mode3.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 1;
+    top->spi_cpha = 1;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp14->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFFFF;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp14->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp14->close();
+
+    /* this test case is unrealistic, as reading before writing doesn't make any
+       sense in most practical scenarios, nevertheless it should work */
+    top->trace(tfp18, 99); // Trace 99 levels of hierarchy
+    tfp18->open("sim_load_value_32inter_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp18->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xFFFFFFFF;
+            top->transaction_rw_mask = 0xAAAAAAAA;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp18->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp18->close();
+
+    /* this test case is unrealistic, as reading before writing doesn't make any
+       sense in most practical scenarios, nevertheless it should work */
+    top->trace(tfp19, 99); // Trace 99 levels of hierarchy
+    tfp19->open("sim_load_value_32interb_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp19->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 20)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xFFFFFFFF;
+            top->transaction_rw_mask = 0x55555555;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();            // Evaluate model
+        tfp19->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp19->close();
+
+    top->trace(tfp20, 99); // Trace 99 levels of hierarchy
+    tfp20->open("sim_load_value_24w_8r_21reset_mode0.vcd");
+    main_time = 0; // Reset time
+    top->reset_n = 0;
+    top->spi_cpol = 0;
+    top->spi_cpha = 0;
+    // Reset sequence
+    while (main_time < 22)
+    {
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();
+        tfp20->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_load_value_fifo_32)
+    {
+        if (main_time == 22)
+        {
+            top->transaction_length = 32;
+            top->transaction_data = 0xAAA00F0F;
+            top->transaction_rw_mask = 0xFFFFFF00;
+        }
+        else
+        {
+            top->transaction_length = 0;
+            top->transaction_data = 0x00000000;
+            top->transaction_rw_mask = 0x00000000;
+        }
+
+        top->fabric_clk = !top->fabric_clk;
+        top->eval();           // Evaluate model
+        tfp20->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+    // cleanup sim file
+    tfp20->close();
+
+    delete top;
+    return 0;
+}
diff --git a/HDL/projects/half_duplex_spi_master/surfer_load_data_rw.ron b/HDL/projects/half_duplex_spi_master/surfer_load_data_rw.ron
new file mode 100644
index 00000000..26dbc901
--- /dev/null
+++ b/HDL/projects/half_duplex_spi_master/surfer_load_data_rw.ron
@@ -0,0 +1,454 @@
+(
+    show_hierarchy: None,
+    show_menu: None,
+    show_ticks: None,
+    show_toolbar: None,
+    show_tooltip: None,
+    show_overview: None,
+    show_statusbar: None,
+    align_names_right: None,
+    show_variable_indices: None,
+    show_variable_direction: None,
+    show_empty_scopes: None,
+    show_parameters_in_scopes: None,
+    waves: Some((
+        source: File("sim_load_value_24w_8rbit_mode0.vcd"),
+        format: Vcd,
+        active_scope: Some(WaveScope((
+            strs: [
+                "TOP",
+                "half_duplex_spi_master_clkdiv",
+                "hdsm",
+            ],
+        ))),
+        displayed_items_order: [
+            (1),
+            (2),
+            (5),
+            (6),
+            (7),
+            (9),
+            (10),
+            (12),
+            (14),
+            (13),
+            (15),
+            (16),
+            (17),
+            (18),
+            (19),
+            (20),
+            (21),
+            (22),
+            (23),
+        ],
+        displayed_items: {
+            (10): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "to_spi_fifo_rd_en",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "to_spi_fifo_rd_en",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (7): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "to_spi_fifo_empty",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "to_spi_fifo_empty",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (2): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                        ],
+                    ),
+                    name: "fabric_clk",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "fabric_clk",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (13): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "spi_sdio",
+                ),
+                color: Some("blue"),
+                background_color: None,
+                display_name: "spi_sdio",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (9): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "spi_clk",
+                ),
+                color: Some("yellow"),
+                background_color: None,
+                display_name: "spi_clk",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (5): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "to_spi_fifo_wr_en",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "to_spi_fifo_wr_en",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (19): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "transaction_read_data_sc",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "transaction_read_data_sc [31:0]",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (21): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "to_fabric_fifo_empty",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "to_fabric_fifo_empty",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (1): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                        ],
+                    ),
+                    name: "reset_n",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "reset_n",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (16): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "spi_state",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "spi_state [2:0]",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (23): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "transaction_read_data",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "transaction_read_data [31:0]",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (18): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "read_bitcounter_sc",
+                ),
+                color: Some("violet"),
+                background_color: None,
+                display_name: "read_bitcounter_sc [5:0]",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (6): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                            "to_spi_fifo",
+                            "mem",
+                        ],
+                    ),
+                    name: "[0]",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "[0] [69:0]",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (15): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "spi_dir",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "spi_dir",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (14): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "spi_sclk",
+                ),
+                color: Some("red"),
+                background_color: None,
+                display_name: "spi_sclk",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (20): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "to_fabric_fifo_wr_en",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "to_fabric_fifo_wr_en",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (22): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "to_fabric_fifo_rd_en",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "to_fabric_fifo_rd_en",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+            (17): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "bitcounter_sc",
+                ),
+                color: None,
+                background_color: None,
+                display_name: "bitcounter_sc [5:0]",
+                display_name_type: Unique,
+                manual_name: None,
+                format: Some("Unsigned"),
+                field_formats: [],
+            )),
+            (12): Variable((
+                variable_ref: (
+                    path: (
+                        strs: [
+                            "TOP",
+                            "half_duplex_spi_master_clkdiv",
+                            "hdsm",
+                        ],
+                    ),
+                    name: "spi_cs_n",
+                ),
+                color: Some("red"),
+                background_color: None,
+                display_name: "spi_cs_n",
+                display_name_type: Unique,
+                manual_name: None,
+                format: None,
+                field_formats: [],
+            )),
+        },
+        display_item_ref_counter: 23,
+        viewports: [
+            (
+                curr_left: (0.22314915249669653),
+                curr_right: (1.3251333489443518),
+                target_left: (0.0),
+                target_right: (1.0),
+                move_start_left: (0.0),
+                move_start_right: (1.0),
+                move_duration: None,
+                move_strategy: Instant,
+            ),
+        ],
+        cursor: Some((1, [
+            406,
+        ])),
+        markers: {},
+        focused_item: Some((2)),
+        focused_transaction: (None, None),
+        selected_items: [],
+        default_variable_name_type: Unique,
+        scroll_offset: 0.0,
+        display_variable_indices: true,
+        graphics: {},
+    )),
+    drag_started: false,
+    drag_source_idx: None,
+    drag_target_idx: None,
+    previous_waves: None,
+    count: None,
+    blacklisted_translators: [],
+    show_about: false,
+    show_keys: false,
+    show_gestures: false,
+    show_quick_start: false,
+    show_license: false,
+    show_performance: false,
+    show_logs: false,
+    show_cursor_window: false,
+    wanted_timeunit: PicoSeconds,
+    time_string_format: None,
+    show_url_entry: false,
+    variable_name_filter_focused: false,
+    variable_name_filter_type: Fuzzy,
+    variable_name_filter_case_insensitive: true,
+    rename_target: None,
+    sidepanel_width: Some(300.0),
+    ui_zoom_factor: None,
+)
\ No newline at end of file
diff --git a/HDL/projects/quadrature_clock_divider/Makefile b/HDL/projects/quadrature_clock_divider/Makefile
new file mode 100644
index 00000000..414a75a8
--- /dev/null
+++ b/HDL/projects/quadrature_clock_divider/Makefile
@@ -0,0 +1,21 @@
+VERILATOR = verilator
+TOP_MODULE = quadrature_clock_divider
+VERILATED = obj_dir/V$(TOP_MODULE)
+
+SRC_FILES = quadrature_clock_divider.sv
+CPP_FILES = quadrature_clock_divider_tb.cpp
+
+all: sim
+
+sim: $(VERILATED)
+	./$(VERILATED)
+
+$(VERILATED): $(SRC_FILES) $(CPP_FILES)
+	$(VERILATOR) -Wall --cc $(SRC_FILES) --exe $(CPP_FILES) --top-module $(TOP_MODULE) --trace --timing
+	make -C obj_dir -f V$(TOP_MODULE).mk V$(TOP_MODULE)
+
+clean:
+	rm -rf obj_dir
+	rm -f sim.vcd
+
+.PHONY: all sim clean
diff --git a/HDL/projects/quadrature_clock_divider/quadrature_clock_divider.sv b/HDL/projects/quadrature_clock_divider/quadrature_clock_divider.sv
new file mode 100644
index 00000000..ec37ee96
--- /dev/null
+++ b/HDL/projects/quadrature_clock_divider/quadrature_clock_divider.sv
@@ -0,0 +1,58 @@
+// this divider uses the counts per quarter cycle to ensure the division is always valid
+// the application for this simple module is the generation of quadrature clocks that are
+// divided from a fast input clock.
+// The bit-width of the division factor is configurable for this module and refers to the
+// number of bits in the quarter cycle count 
+// Common applications are SPI buses for example.
+module quadrature_clock_divider #(
+    parameter DIVIDER_WIDTH = 8
+)(
+    input wire clk_in,                 // Fast input clock
+    input wire reset_n,                // Reset signal
+    input wire [DIVIDER_WIDTH-1:0] div_factor_4,     // Division factor as multiplier to 4
+                                       // or "counts per quarter cycle"
+    output reg sck_0,                  // 0-degree phase clock
+    output reg sck_90                  // 90-degree phase-shifted clock
+);
+
+    reg [DIVIDER_WIDTH+1:0] counter;                 // Counter for clock division
+    reg [DIVIDER_WIDTH+1:0] half_cycle;              // Half-cycle count for 50% duty cycle
+    reg [DIVIDER_WIDTH+1:0] quarter_cycle;           // Quarter-cycle count for 90-degree shift
+    reg [DIVIDER_WIDTH+1:0] zero;
+
+    always @(posedge clk_in or negedge reset_n) begin
+        if (~reset_n) begin
+            counter <= 0;
+            sck_0 <= 0;
+            sck_90 <= 0;
+            zero <= 0;
+            half_cycle <= {1'b0, div_factor_4, 1'b0};          // 50% duty cycle
+            quarter_cycle <= {2'b00, div_factor_4};            // 90-degree phase shift
+        end else begin
+            // Calculate half and quarter cycles based on the division factor
+            half_cycle <= {1'b0, div_factor_4, 1'b0};          // 50% duty cycle
+            quarter_cycle <= {2'b00, div_factor_4};            // 90-degree phase shift
+
+            // Counter logic to generate sck_0 and sck_90
+            if (counter >= {div_factor_4, 2'b00} - 1) begin
+                counter <= 0;  // Reset counter at the end of the cycle
+            end else begin
+                counter <= counter + 1;
+            end
+
+            // Generate sck_0 and sck_90 based on counter values
+            if (counter >= zero && counter < half_cycle) begin
+                sck_0 <= 1;
+            end else  begin
+                sck_0 <= 0;
+            end
+
+            if (counter >= quarter_cycle && counter < half_cycle + quarter_cycle) begin
+                sck_90 <= 1;
+            end else begin
+                sck_90 <= 0;
+            end
+        end
+    end
+endmodule
+
diff --git a/HDL/projects/quadrature_clock_divider/quadrature_clock_divider_tb.cpp b/HDL/projects/quadrature_clock_divider/quadrature_clock_divider_tb.cpp
new file mode 100644
index 00000000..bd1752a6
--- /dev/null
+++ b/HDL/projects/quadrature_clock_divider/quadrature_clock_divider_tb.cpp
@@ -0,0 +1,56 @@
+// main.cpp
+#include "Vquadrature_clock_divider.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+#include <iostream>
+#include <fstream>
+
+int main(int argc, char **argv)
+{
+    Verilated::commandArgs(argc, argv);
+
+    // Instantiate the top module
+    Vquadrature_clock_divider *top = new Vquadrature_clock_divider;
+
+    // Initialize simulation inputs
+    top->reset_n = 0;
+    top->div_factor_4 = 1;
+    // Variables for simulation
+    vluint64_t main_time = 0;            // Current simulation time
+    const vluint64_t sim_time = 4000000; // Adjust as needed
+
+    // Open VCD dump file
+    Verilated::traceEverOn(true);
+    VerilatedVcdC *tfp = new VerilatedVcdC;
+    top->trace(tfp, 99); // Trace 99 levels of hierarchy
+    tfp->open("sim.vcd");
+
+    // Reset sequence
+    while (main_time < 20)
+    {
+        top->clk_in = !top->clk_in;
+        top->eval();
+        tfp->dump(main_time);
+        main_time++;
+    }
+    top->reset_n = 1;
+
+    while (main_time < sim_time)
+    {
+        // Toggle clocks
+        if ((main_time % 5) == 0)
+        {
+            top->clk_in = !top->clk_in;
+        }
+
+        top->eval();          // Evaluate model
+        tfp->dump(main_time); // Dump signals to VCD file
+
+        main_time++;
+    }
+
+    // Cleanup
+    tfp->close();
+    delete top;
+    return 0;
+}
diff --git a/HDL/projects/reset_synchronizer/reset_synchronizer.sv b/HDL/projects/reset_synchronizer/reset_synchronizer.sv
new file mode 100644
index 00000000..b87ce198
--- /dev/null
+++ b/HDL/projects/reset_synchronizer/reset_synchronizer.sv
@@ -0,0 +1,19 @@
+// A reset synchronizer synchronizes the deassertion of reset with respect to the clock domain. 
+// In other words, a reset synchronizer manipulates the asynchronous reset to have synchronous deassertion.
+
+module reset_synchronizer (
+    input wire reset_n,
+    input wire clk,
+    output reg sync_reset_n
+);
+    reg Q1;
+    always @ (posedge clk or negedge reset_n) begin
+        if(~reset_n) begin
+            Q1 <= 1'b0;
+            sync_reset_n <= 1'b0;
+        end else begin
+            Q1 <= 1'b1;
+            sync_reset_n <= Q1;
+        end
+    end
+endmodule
diff --git a/HDL/projects/spi_clock_generator/Makefile b/HDL/projects/spi_clock_generator/Makefile
new file mode 100644
index 00000000..9b96c193
--- /dev/null
+++ b/HDL/projects/spi_clock_generator/Makefile
@@ -0,0 +1,21 @@
+VERILATOR = verilator
+TOP_MODULE = spi_clock_generator
+VERILATED = obj_dir/V$(TOP_MODULE)
+
+SRC_FILES = spi_clock_generator.sv
+CPP_FILES = spi_clock_generator_tb.cpp
+
+all: sim
+
+sim: $(VERILATED)
+	./$(VERILATED)
+
+$(VERILATED): $(SRC_FILES) $(CPP_FILES)
+	$(VERILATOR) -Wall --cc $(SRC_FILES) --exe $(CPP_FILES) --top-module $(TOP_MODULE) --trace --timing
+	make -C obj_dir -f V$(TOP_MODULE).mk V$(TOP_MODULE)
+
+clean:
+	rm -rf obj_dir
+	rm -f sim.vcd
+
+.PHONY: all sim clean
diff --git a/HDL/projects/spi_clock_generator/spi_clock_generator.sv b/HDL/projects/spi_clock_generator/spi_clock_generator.sv
new file mode 100644
index 00000000..39d3e2b7
--- /dev/null
+++ b/HDL/projects/spi_clock_generator/spi_clock_generator.sv
@@ -0,0 +1,31 @@
+module spi_clock_generator (
+    input  wire clk_0,             // External clock (0° phase)
+    input  wire clk_90,            // External clock (90° phase)
+    input  wire cpol,              // Clock Polarity
+    input  wire cpha,              // Clock Phase
+    output logic spi_clk,          // Generated SPI clock
+    output logic shift_clk         // Data shift clock
+);
+
+    // Generate spi_clk based on cpol
+    always_comb begin
+        if (cpol == 0) begin
+            if (cpha == 0) begin
+                spi_clk = clk_90;   // SPI mode 0
+                shift_clk = clk_0;  
+            end else begin
+                spi_clk = clk_0;  // SPI mode 1
+                shift_clk = clk_90;
+            end
+        end else begin
+            if (cpha == 0) begin
+                spi_clk = ~clk_90;   // SPI mode 2
+                shift_clk = clk_0;
+            end else begin
+                spi_clk = ~clk_0;  // SPI mode 3
+                shift_clk = clk_90;
+            end
+        end
+    end
+
+endmodule
diff --git a/HDL/projects/spi_clock_generator/spi_clock_generator_tb.cpp b/HDL/projects/spi_clock_generator/spi_clock_generator_tb.cpp
new file mode 100644
index 00000000..3043882b
--- /dev/null
+++ b/HDL/projects/spi_clock_generator/spi_clock_generator_tb.cpp
@@ -0,0 +1,76 @@
+#include <iostream>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include "Vspi_clock_generator.h" // Include the generated Verilator header
+
+// Define clock signal generation helper
+void toggle_clock(bool &clk)
+{
+    clk = !clk;
+}
+
+int main(int argc, char **argv)
+{
+    Verilated::commandArgs(argc, argv);
+    Verilated::traceEverOn(true);
+
+    // Instantiate the DUT (Device Under Test)
+    Vspi_clock_generator *dut = new Vspi_clock_generator;
+
+    // Initialize trace file
+    VerilatedVcdC *vcd = new VerilatedVcdC;
+    dut->trace(vcd, 10);
+    vcd->open("spi_clock_generator.vcd");
+
+    // Simulation variables
+    bool clk_0 = 0;  // Clock signal (0° phase)
+    bool clk_90 = 0; // Clock signal (90° phase)
+    int clk_0_count = 0;
+
+    // Test CPOL and CPHA configurations
+    // The way of doing these tests is causing ugly glitches in the cpol=1 case
+    for (int cpol = 0; cpol <= 1; ++cpol)
+    {
+        for (int cpha = 0; cpha <= 1; ++cpha)
+        {
+            // Initialize DUT inputs
+            dut->cpol = cpol;
+            dut->cpha = cpha;
+
+            // Run simulation for a few clock cycles
+            for (int i = 0; i < 20; ++i)
+            {
+                // Toggle clocks
+                if (clk_0_count % 2 == 0)
+                    toggle_clock(clk_0);
+                if (clk_0_count % 2 == 1)
+                    toggle_clock(clk_90); // 90° phase assumes clk_90 toggles half as often
+
+                // Drive inputs
+                dut->clk_0 = clk_0;
+                dut->clk_90 = clk_90;
+
+                // Evaluate the DUT
+                dut->eval();
+                vcd->dump(clk_0_count);
+                // Print results
+                std::cout << "CPOL: " << cpol
+                          << " CPHA: " << cpha
+                          << " clk_0: " << clk_0
+                          << " clk_90: " << clk_90
+                          << " spi_clk: " << (dut->spi_clk ? "1" : "0")
+                          << " shift_clk: " << (dut->shift_clk ? "1" : "0")
+                          << std::endl;
+
+                // Increment clock cycle count
+                clk_0_count++;
+            }
+        }
+    }
+
+    // Cleanup
+    dut->final();
+    vcd->close();
+    delete dut;
+    return 0;
+}
\ No newline at end of file
diff --git a/HDL/scripts/Vivado_ocra_init.tcl b/HDL/scripts/Vivado_ocra_init.tcl
index 29c658d2..7fb736f1 100644
--- a/HDL/scripts/Vivado_ocra_init.tcl
+++ b/HDL/scripts/Vivado_ocra_init.tcl
@@ -1,4 +1,4 @@
 
 # source this from your Vivado_init.tcl
 set ocra_dir $::env(OCRA_DIR)
-set_param board.repoPaths [list ${ocra_dir}/HDL/boards/snickerdoodle_black/brd/1.0/ ${ocra_dir}/HDL/boards/stemlab_125_14/brd/1.1/ ${ocra_dir}/HDL/boards/stemlab_122_16/brd/1.0/ ]
+set_param board.repoPaths [list ${ocra_dir}/HDL/boards/snickerdoodle_black/brd/1.0/ ${ocra_dir}/HDL/boards/stemlab_125_14/brd/1.1/ ${ocra_dir}/HDL/boards/stemlab_122_16/brd/1.0/ ${ocra_dir}/HDL/boards/eclypse_z7/brd/A.0/ ${ocra_dir}/HDL/boards/eclypse_z7/brd/B.0/ ${ocra_dir}/HDL/boards/zub1cg/brd/1.2/]
diff --git a/HDL/scripts/app_cpu1.tcl b/HDL/scripts/app_cpu1.tcl
deleted file mode 100644
index 8fda3259..00000000
--- a/HDL/scripts/app_cpu1.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-
-set project_name [lindex $argv 0]
-
-set proc_name ps7_cortexa9_1
-
-set hard_path tmp/$project_name.hard
-set cpu1_path tmp/$project_name.cpu1
-
-file mkdir $hard_path
-file copy -force tmp/$project_name.hwdef $hard_path/$project_name.hdf
-
-open_hw_design $hard_path/$project_name.hdf
-create_sw_design -proc $proc_name -os standalone system
-
-set_property CONFIG.stdin {none} [get_os]
-set_property CONFIG.stdout {none} [get_os]
-
-set_property CONFIG.extra_compiler_flags { -g -DUSE_AMP=1 -DSTDOUT_REDIR=1} [get_sw_processor]
-
-generate_bsp -proc $proc_name -dir $cpu1_path/app_cpu1_bsp
-
-close_hw_design [current_hw_design]
diff --git a/HDL/scripts/debian-ecosystem.sh b/HDL/scripts/debian-ecosystem.sh
deleted file mode 100644
index 82a00453..00000000
--- a/HDL/scripts/debian-ecosystem.sh
+++ /dev/null
@@ -1,338 +0,0 @@
-device=$1
-
-boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
-root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-
-ecosystem_tar=red-pitaya-ecosystem-0.95-20160526.tgz
-ecosystem_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AADrueq0P1OJFy9z6AaJ72nWa/red-pitaya-ecosystem/red-pitaya-ecosystem-0.95-20160526.tgz?dl=1
-
-# Choose mirror automatically, depending the geographic and network location
-mirror=http://httpredir.debian.org/debian
-
-distro=jessie
-arch=armhf
-
-hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
-
-passwd=changeme
-timezone=Europe/Brussels
-
-# Create partitions
-
-parted -s $device mklabel msdos
-parted -s $device mkpart primary fat16 4MB 16MB
-parted -s $device mkpart primary ext4 16MB 100%
-
-boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
-
-# Create file systems
-
-mkfs.vfat -v $boot_dev
-mkfs.ext4 -F -j $root_dev
-
-# Mount file systems
-
-mount $boot_dev $boot_dir
-mount $root_dev $root_dir
-
-# Copy files to the boot file system
-
-cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
-
-# Install Debian base system to the root file system
-
-debootstrap --foreign --arch $arch $distro $root_dir $mirror
-
-# Add missing configuration files and packages
-
-cp /etc/resolv.conf $root_dir/etc/
-cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
-
-cp patches/fw_env.config $root_dir/etc/
-
-mkdir -p $root_dir/usr/local/bin
-cp fw_printenv $root_dir/usr/local/bin/fw_printenv
-cp fw_printenv $root_dir/usr/local/bin/fw_setenv
-
-mkdir -p $root_dir/usr/local/sbin
-curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
-chmod +x $root_dir/usr/local/sbin/hostapd
-
-test -f $ecosystem_tar || curl -L $ecosystem_url -o $ecosystem_tar
-
-mkdir -p $root_dir/var/log/nginx
-mkdir -p $root_dir/var/log/redpitaya_nginx
-mkdir -p $root_dir/opt
-tar -zxf $ecosystem_tar --directory=$root_dir/opt
-
-chroot $root_dir <<- EOF_CHROOT
-export LANG=C
-export LC_ALL=C
-
-# Add missing paths
-
-echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
-echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
-echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
-echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
-
-/debootstrap/debootstrap --second-stage
-
-cat <<- EOF_CAT > /etc/apt/sources.list
-deb $mirror $distro main contrib non-free
-deb-src $mirror $distro main contrib non-free
-deb $mirror $distro-updates main contrib non-free
-deb-src $mirror $distro-updates main contrib non-free
-deb http://security.debian.org/debian-security $distro/updates main contrib non-free
-deb-src http://security.debian.org/debian-security $distro/updates main contrib non-free
-EOF_CAT
-
-cat <<- EOF_CAT > etc/apt/apt.conf.d/99norecommends
-APT::Install-Recommends "0";
-APT::Install-Suggests "0";
-EOF_CAT
-
-cat <<- EOF_CAT > etc/fstab
-# /etc/fstab: static file system information.
-# <file system> <mount point>   <type>  <options>           <dump>  <pass>
-/dev/mmcblk0p2  /               ext4    errors=remount-ro   0       1
-/dev/mmcblk0p1  /boot           vfat    defaults            0       2
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/securetty
-
-# Serial Console for Xilinx Zynq-7000
-ttyPS0
-EOF_CAT
-
-echo red-pitaya > etc/hostname
-
-apt-get update
-apt-get -y upgrade
-
-apt-get -y install locales
-
-sed -i "/^# en_US.UTF-8 UTF-8$/s/^# //" etc/locale.gen
-locale-gen
-update-locale LANG=en_US.UTF-8
-
-echo $timezone > etc/timezone
-dpkg-reconfigure --frontend=noninteractive tzdata
-
-apt-get -y install openssh-server ca-certificates ntp ntpdate fake-hwclock \
-  usbutils psmisc lsof parted curl vim wpasupplicant hostapd isc-dhcp-server \
-  iw firmware-realtek firmware-ralink firmware-atheros firmware-brcm80211 \
-  build-essential libconfig-dev libpcre3-dev libluajit-5.1-dev libssl-dev \
-  libboost-regex1.55-dev libboost-system1.55-dev libboost-thread1.55-dev \
-  libcurl4-openssl-dev libcrypto++-dev libfftw3-dev libasound2-dev zlib1g-dev \
-  unzip ifplugd ntfs-3g alsa-utils lua-cjson parallel subversion git
-
-sed -i 's/^PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
-
-cat <<- EOF_CAT > etc/systemd/system/redpitaya_nginx.service
-[Unit]
-Description=Customized Nginx web server for Red Pitaya applications
-After=network.target
-
-[Service]
-Type=forking
-PIDFile=/run/redpitaya_nginx.pid
-Environment=PATH_REDPITAYA=/opt/redpitaya
-Environment=LD_LIBRARY_PATH=/opt/redpitaya/lib
-Environment=PATH=/usr/sbin:/usr/bin:/sbin:/bin:/opt/redpitaya/sbin:/opt/redpitaya/bin
-ExecStart=/opt/redpitaya/sbin/nginx -p \\\${PATH_REDPITAYA}/www
-ExecReload=/opt/redpitaya/sbin/nginx -p \\\${PATH_REDPITAYA}/www -s reload
-ExecStop=/opt/redpitaya/sbin/nginx -p \\\${PATH_REDPITAYA}/www -s quit
-
-[Install]
-WantedBy=multi-user.target
-EOF_CAT
-
-cat <<- EOF_CAT > etc/systemd/system/redpitaya_scpi.service
-[Unit]
-Description=SCPI server for Red Pitaya
-After=network.target
-
-[Service]
-Type=simple
-Restart=always
-Environment=PATH_REDPITAYA=/opt/redpitaya
-Environment=LD_LIBRARY_PATH=/opt/redpitaya/lib
-Environment=PATH=/usr/sbin:/usr/bin:/sbin:/bin:/opt/redpitaya/sbin:/opt/redpitaya/bin
-ExecStart=/opt/redpitaya/bin/scpi-server
-ExecStop=/bin/kill -15 \\\${MAINPID}
-
-[Install]
-WantedBy=multi-user.target
-EOF_CAT
-
-systemctl enable redpitaya_nginx
-
-cat <<- EOF_CAT > etc/profile.d/red-pitaya.sh
-export PATH=\\\$PATH:/opt/redpitaya/bin
-export LD_LIBRARY_PATH=\\\$LD_LIBRARY_PATH:/opt/redpitaya/lib
-EOF_CAT
-
-touch etc/udev/rules.d/75-persistent-net-generator.rules
-
-cat <<- EOF_CAT > etc/network/interfaces.d/eth0
-iface eth0 inet dhcp
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/ifplugd
-INTERFACES="eth0"
-HOTPLUG_INTERFACES=""
-ARGS="-q -f -u0 -d10 -w -I"
-SUSPEND_ACTION="stop"
-EOF_CAT
-
-cat <<- EOF_CAT > etc/network/interfaces.d/wlan0
-allow-hotplug wlan0
-iface wlan0 inet static
-  address 192.168.42.1
-  netmask 255.255.255.0
-  post-up service hostapd restart
-  post-up service isc-dhcp-server restart
-  post-up iptables-restore < /etc/iptables.ipv4.nat
-  pre-down iptables-restore < /etc/iptables.ipv4.nonat
-  pre-down service isc-dhcp-server stop
-  pre-down service hostapd stop
-EOF_CAT
-
-cat <<- EOF_CAT > etc/hostapd/hostapd.conf
-interface=wlan0
-ssid=RedPitaya
-driver=nl80211
-hw_mode=g
-channel=6
-macaddr_acl=0
-auth_algs=1
-ignore_broadcast_ssid=0
-wpa=2
-wpa_passphrase=RedPitaya
-wpa_key_mgmt=WPA-PSK
-wpa_pairwise=CCMP
-rsn_pairwise=CCMP
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/hostapd
-DAEMON_CONF=/etc/hostapd/hostapd.conf
-
-if [ "\\\$1" = "start" ]
-then
-  iw wlan0 info > /dev/null 2>&1
-  if [ \\\$? -eq 0 ]
-  then
-    sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/sbin/hostapd
-  else
-    sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/local/sbin/hostapd
-  fi
-  echo \\\$DAEMON_SBIN > /run/hostapd.which
-elif [ "\\\$1" = "stop" ]
-then
-  DAEMON_SBIN=\\\$(cat /run/hostapd.which)
-fi
-EOF_CAT
-
-cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
-ddns-update-style none;
-default-lease-time 600;
-max-lease-time 7200;
-authoritative;
-log-facility local7;
-subnet 192.168.42.0 netmask 255.255.255.0 {
-  range 192.168.42.10 192.168.42.50;
-  option broadcast-address 192.168.42.255;
-  option routers 192.168.42.1;
-  default-lease-time 600;
-  max-lease-time 7200;
-  option domain-name "local";
-  option domain-name-servers 8.8.8.8, 8.8.4.4;
-}
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/dhcp/dhclient.conf
-timeout 20;
-
-lease {
-  interface "eth0";
-  fixed-address 192.168.1.100;
-  option subnet-mask 255.255.255.0;
-  renew 2 2030/1/1 00:00:01;
-  rebind 2 2030/1/1 00:00:01;
-  expire 2 2030/1/1 00:00:01;
-}
-EOF_CAT
-
-sed -i '/^#net.ipv4.ip_forward=1$/s/^#//' etc/sysctl.conf
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
--A POSTROUTING -o eth0 -j MASQUERADE
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
--A FORWARD -i eth0 -o wlan0 -m state --state RELATED,ESTABLISHED -j ACCEPT
--A FORWARD -i wlan0 -o eth0 -j ACCEPT
-COMMIT
-EOF_CAT
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nonat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-COMMIT
-EOF_CAT
-
-apt-get clean
-
-echo root:$passwd | chpasswd
-
-service ntp stop
-service ssh stop
-
-history -c
-
-sync
-EOF_CHROOT
-
-rm $root_dir/etc/resolv.conf
-rm $root_dir/usr/bin/qemu-arm-static
-
-# Unmount file systems
-
-umount $boot_dir $root_dir
-
-rmdir $boot_dir $root_dir
-
-zerofree $root_dev
diff --git a/HDL/scripts/debian-gnuradio.sh b/HDL/scripts/debian-gnuradio.sh
deleted file mode 100644
index 44334006..00000000
--- a/HDL/scripts/debian-gnuradio.sh
+++ /dev/null
@@ -1,286 +0,0 @@
-device=$1
-
-boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
-root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-
-# Choose mirror automatically, depending the geographic and network location
-mirror=http://httpredir.debian.org/debian
-
-distro=jessie
-arch=armhf
-
-hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
-
-passwd=changeme
-timezone=Europe/Brussels
-
-# Create partitions
-
-parted -s $device mklabel msdos
-parted -s $device mkpart primary fat16 4MB 16MB
-parted -s $device mkpart primary ext4 16MB 100%
-
-boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
-
-# Create file systems
-
-mkfs.vfat -v $boot_dev
-mkfs.ext4 -F -j $root_dev
-
-# Mount file systems
-
-mount $boot_dev $boot_dir
-mount $root_dev $root_dir
-
-# Copy files to the boot file system
-
-cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
-
-# Install Debian base system to the root file system
-
-debootstrap --foreign --arch $arch $distro $root_dir $mirror
-
-# Add missing configuration files and packages
-
-cp /etc/resolv.conf $root_dir/etc/
-cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
-
-cp patches/fw_env.config $root_dir/etc/
-
-mkdir -p $root_dir/usr/local/bin
-cp fw_printenv $root_dir/usr/local/bin/fw_printenv
-cp fw_printenv $root_dir/usr/local/bin/fw_setenv
-
-mkdir -p $root_dir/usr/local/sbin
-curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
-chmod +x $root_dir/usr/local/sbin/hostapd
-
-mkdir -p $root_dir/root/gnuradio
-cp projects/sdr_transceiver_emb/gnuradio/* $root_dir/root/gnuradio/
-
-chroot $root_dir <<- EOF_CHROOT
-export LANG=C
-export LC_ALL=C
-
-# Add missing paths
-
-echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
-echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
-echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
-echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
-
-/debootstrap/debootstrap --second-stage
-
-cat <<- EOF_CAT > /etc/apt/sources.list
-deb $mirror $distro main contrib non-free
-deb-src $mirror $distro main contrib non-free
-deb $mirror $distro-updates main contrib non-free
-deb-src $mirror $distro-updates main contrib non-free
-deb http://security.debian.org/debian-security $distro/updates main contrib non-free
-deb-src http://security.debian.org/debian-security $distro/updates main contrib non-free
-EOF_CAT
-
-cat <<- EOF_CAT > etc/apt/apt.conf.d/99norecommends
-APT::Install-Recommends "0";
-APT::Install-Suggests "0";
-EOF_CAT
-
-cat <<- EOF_CAT > etc/fstab
-# /etc/fstab: static file system information.
-# <file system> <mount point>   <type>  <options>           <dump>  <pass>
-/dev/mmcblk0p2  /               ext4    errors=remount-ro   0       1
-/dev/mmcblk0p1  /boot           vfat    defaults            0       2
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/securetty
-
-# Serial Console for Xilinx Zynq-7000
-ttyPS0
-EOF_CAT
-
-echo red-pitaya > etc/hostname
-
-apt-get update
-apt-get -y upgrade
-
-apt-get -y install locales
-
-sed -i "/^# en_US.UTF-8 UTF-8$/s/^# //" etc/locale.gen
-locale-gen
-update-locale LANG=en_US.UTF-8
-
-echo $timezone > etc/timezone
-dpkg-reconfigure --frontend=noninteractive tzdata
-
-apt-get -y install openssh-server ca-certificates ntp ntpdate fake-hwclock \
-  usbutils psmisc lsof parted curl vim wpasupplicant hostapd isc-dhcp-server \
-  iw firmware-realtek firmware-ralink firmware-atheros firmware-brcm80211 \
-  build-essential libasound2-dev libconfig-dev libfftw3-dev subversion git \
-  alsa-utils gnuradio python-numpy python-gtk2 python-urwid python-serial \
-  python-alsaaudio xauth xterm parallel ifplugd ntfs-3g
-
-sed -i 's/^PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
-
-touch etc/udev/rules.d/75-persistent-net-generator.rules
-
-cat <<- EOF_CAT > etc/network/interfaces.d/eth0
-iface eth0 inet dhcp
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/ifplugd
-INTERFACES="eth0"
-HOTPLUG_INTERFACES=""
-ARGS="-q -f -u0 -d10 -w -I"
-SUSPEND_ACTION="stop"
-EOF_CAT
-
-cat <<- EOF_CAT > etc/network/interfaces.d/wlan0
-allow-hotplug wlan0
-iface wlan0 inet static
-  address 192.168.42.1
-  netmask 255.255.255.0
-  post-up service hostapd restart
-  post-up service isc-dhcp-server restart
-  post-up iptables-restore < /etc/iptables.ipv4.nat
-  pre-down iptables-restore < /etc/iptables.ipv4.nonat
-  pre-down service isc-dhcp-server stop
-  pre-down service hostapd stop
-EOF_CAT
-
-cat <<- EOF_CAT > etc/hostapd/hostapd.conf
-interface=wlan0
-ssid=RedPitaya
-driver=nl80211
-hw_mode=g
-channel=6
-macaddr_acl=0
-auth_algs=1
-ignore_broadcast_ssid=0
-wpa=2
-wpa_passphrase=RedPitaya
-wpa_key_mgmt=WPA-PSK
-wpa_pairwise=CCMP
-rsn_pairwise=CCMP
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/hostapd
-DAEMON_CONF=/etc/hostapd/hostapd.conf
-
-if [ "\\\$1" = "start" ]
-then
-  iw wlan0 info > /dev/null 2>&1
-  if [ \\\$? -eq 0 ]
-  then
-    sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/sbin/hostapd
-  else
-    sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/local/sbin/hostapd
-  fi
-  echo \\\$DAEMON_SBIN > /run/hostapd.which
-elif [ "\\\$1" = "stop" ]
-then
-  DAEMON_SBIN=\\\$(cat /run/hostapd.which)
-fi
-EOF_CAT
-
-cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
-ddns-update-style none;
-default-lease-time 600;
-max-lease-time 7200;
-authoritative;
-log-facility local7;
-subnet 192.168.42.0 netmask 255.255.255.0 {
-  range 192.168.42.10 192.168.42.50;
-  option broadcast-address 192.168.42.255;
-  option routers 192.168.42.1;
-  default-lease-time 600;
-  max-lease-time 7200;
-  option domain-name "local";
-  option domain-name-servers 8.8.8.8, 8.8.4.4;
-}
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/dhcp/dhclient.conf
-timeout 20;
-
-lease {
-  interface "eth0";
-  fixed-address 192.168.1.100;
-  option subnet-mask 255.255.255.0;
-  renew 2 2030/1/1 00:00:01;
-  rebind 2 2030/1/1 00:00:01;
-  expire 2 2030/1/1 00:00:01;
-}
-EOF_CAT
-
-sed -i '/^#net.ipv4.ip_forward=1$/s/^#//' etc/sysctl.conf
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
--A POSTROUTING -o eth0 -j MASQUERADE
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
--A FORWARD -i eth0 -o wlan0 -m state --state RELATED,ESTABLISHED -j ACCEPT
--A FORWARD -i wlan0 -o eth0 -j ACCEPT
-COMMIT
-EOF_CAT
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nonat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-COMMIT
-EOF_CAT
-
-apt-get clean
-
-echo root:$passwd | chpasswd
-
-service ntp stop
-service ssh stop
-
-history -c
-
-sync
-EOF_CHROOT
-
-rm $root_dir/etc/resolv.conf
-rm $root_dir/usr/bin/qemu-arm-static
-
-# Unmount file systems
-
-umount $boot_dir $root_dir
-
-rmdir $boot_dir $root_dir
-
-zerofree $root_dev
diff --git a/HDL/scripts/debian-wspr.sh b/HDL/scripts/debian-wspr.sh
deleted file mode 100644
index bc876ca2..00000000
--- a/HDL/scripts/debian-wspr.sh
+++ /dev/null
@@ -1,301 +0,0 @@
-device=$1
-
-boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
-root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-
-# Choose mirror automatically, depending the geographic and network location
-mirror=http://httpredir.debian.org/debian
-
-distro=jessie
-arch=armhf
-
-hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
-
-passwd=changeme
-timezone=Europe/Brussels
-
-# Create partitions
-
-parted -s $device mklabel msdos
-parted -s $device mkpart primary fat16 4MB 16MB
-parted -s $device mkpart primary ext4 16MB 100%
-
-boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
-
-# Create file systems
-
-mkfs.vfat -v $boot_dev
-mkfs.ext4 -F -j $root_dev
-
-# Mount file systems
-
-mount $boot_dev $boot_dir
-mount $root_dev $root_dir
-
-# Copy files to the boot file system
-
-cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
-
-# Install Debian base system to the root file system
-
-debootstrap --foreign --arch $arch $distro $root_dir $mirror
-
-# Add missing configuration files and packages
-
-cp /etc/resolv.conf $root_dir/etc/
-cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
-
-cp patches/fw_env.config $root_dir/etc/
-
-mkdir -p $root_dir/usr/local/bin
-cp fw_printenv $root_dir/usr/local/bin/fw_printenv
-cp fw_printenv $root_dir/usr/local/bin/fw_setenv
-
-mkdir -p $root_dir/usr/local/sbin
-curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
-chmod +x $root_dir/usr/local/sbin/hostapd
-
-mkdir -p $root_dir/root
-cp projects/sdr_transceiver_wspr/transmit-wspr-message.c $root_dir/root/
-cp projects/sdr_transceiver_wspr/transmit-wspr-message.cfg $root_dir/root/
-cp projects/sdr_transceiver_wspr/transmit-wspr.sh $root_dir/root/
-cp projects/sdr_transceiver_wspr/write-c2-files.c $root_dir/root/
-cp projects/sdr_transceiver_wspr/write-c2-files.cfg $root_dir/root/
-cp projects/sdr_transceiver_wspr/decode-wspr.sh $root_dir/root/
-cp projects/sdr_transceiver_wspr/gpio-output.c $root_dir/root/
-cp projects/sdr_transceiver_wspr/wspr.cron $root_dir/root/
-cp projects/sdr_transceiver_wspr/README $root_dir/root/
-cp projects/sdr_transceiver_wspr/Makefile $root_dir/root/
-
-chroot $root_dir <<- EOF_CHROOT
-export LANG=C
-export LC_ALL=C
-
-# Add missing paths
-
-echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
-echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
-echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
-echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
-
-/debootstrap/debootstrap --second-stage
-
-cat <<- EOF_CAT > /etc/apt/sources.list
-deb $mirror $distro main contrib non-free
-deb-src $mirror $distro main contrib non-free
-deb $mirror $distro-updates main contrib non-free
-deb-src $mirror $distro-updates main contrib non-free
-deb http://security.debian.org/debian-security $distro/updates main contrib non-free
-deb-src http://security.debian.org/debian-security $distro/updates main contrib non-free
-EOF_CAT
-
-cat <<- EOF_CAT > etc/apt/apt.conf.d/99norecommends
-APT::Install-Recommends "0";
-APT::Install-Suggests "0";
-EOF_CAT
-
-cat <<- EOF_CAT > etc/fstab
-# /etc/fstab: static file system information.
-# <file system> <mount point>   <type>  <options>           <dump>  <pass>
-/dev/mmcblk0p2  /               ext4    errors=remount-ro   0       1
-/dev/mmcblk0p1  /boot           vfat    defaults            0       2
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/securetty
-
-# Serial Console for Xilinx Zynq-7000
-ttyPS0
-EOF_CAT
-
-echo red-pitaya > etc/hostname
-
-apt-get update
-apt-get -y upgrade
-
-apt-get -y install locales
-
-sed -i "/^# en_US.UTF-8 UTF-8$/s/^# //" etc/locale.gen
-locale-gen
-update-locale LANG=en_US.UTF-8
-
-echo $timezone > etc/timezone
-dpkg-reconfigure --frontend=noninteractive tzdata
-
-apt-get -y install openssh-server ca-certificates ntp ntpdate fake-hwclock \
-  usbutils psmisc lsof parted curl vim wpasupplicant hostapd isc-dhcp-server \
-  iw firmware-realtek firmware-ralink firmware-atheros firmware-brcm80211 \
-  build-essential subversion libfftw3-dev libconfig-dev parallel ifplugd ntfs-3g
-
-cd root
-svn co svn://svn.code.sf.net/p/wsjt/wsjt/branches/wsjtx/lib/wsprd
-make -C wsprd CFLAGS='-O3 -march=armv7-a -mcpu=cortex-a9 -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard -ffast-math -fsingle-precision-constant -mvectorize-with-neon-quad' wsprd
-make
-cd ..
-
-ln -sf /root/wspr.cron etc/cron.d/wspr
-
-sed -i 's/^PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
-
-touch etc/udev/rules.d/75-persistent-net-generator.rules
-
-cat <<- EOF_CAT > etc/network/interfaces.d/eth0
-iface eth0 inet dhcp
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/ifplugd
-INTERFACES="eth0"
-HOTPLUG_INTERFACES=""
-ARGS="-q -f -u0 -d10 -w -I"
-SUSPEND_ACTION="stop"
-EOF_CAT
-
-cat <<- EOF_CAT > etc/network/interfaces.d/wlan0
-allow-hotplug wlan0
-iface wlan0 inet static
-  address 192.168.42.1
-  netmask 255.255.255.0
-  post-up service hostapd restart
-  post-up service isc-dhcp-server restart
-  post-up iptables-restore < /etc/iptables.ipv4.nat
-  pre-down iptables-restore < /etc/iptables.ipv4.nonat
-  pre-down service isc-dhcp-server stop
-  pre-down service hostapd stop
-EOF_CAT
-
-cat <<- EOF_CAT > etc/hostapd/hostapd.conf
-interface=wlan0
-ssid=RedPitaya
-driver=nl80211
-hw_mode=g
-channel=6
-macaddr_acl=0
-auth_algs=1
-ignore_broadcast_ssid=0
-wpa=2
-wpa_passphrase=RedPitaya
-wpa_key_mgmt=WPA-PSK
-wpa_pairwise=CCMP
-rsn_pairwise=CCMP
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/hostapd
-DAEMON_CONF=/etc/hostapd/hostapd.conf
-
-if [ "\\\$1" = "start" ]
-then
-  iw wlan0 info > /dev/null 2>&1
-  if [ \\\$? -eq 0 ]
-  then
-    sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/sbin/hostapd
-  else
-    sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/local/sbin/hostapd
-  fi
-  echo \\\$DAEMON_SBIN > /run/hostapd.which
-elif [ "\\\$1" = "stop" ]
-then
-  DAEMON_SBIN=\\\$(cat /run/hostapd.which)
-fi
-EOF_CAT
-
-cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
-ddns-update-style none;
-default-lease-time 600;
-max-lease-time 7200;
-authoritative;
-log-facility local7;
-subnet 192.168.42.0 netmask 255.255.255.0 {
-  range 192.168.42.10 192.168.42.50;
-  option broadcast-address 192.168.42.255;
-  option routers 192.168.42.1;
-  default-lease-time 600;
-  max-lease-time 7200;
-  option domain-name "local";
-  option domain-name-servers 8.8.8.8, 8.8.4.4;
-}
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/dhcp/dhclient.conf
-timeout 20;
-
-lease {
-  interface "eth0";
-  fixed-address 192.168.1.100;
-  option subnet-mask 255.255.255.0;
-  renew 2 2030/1/1 00:00:01;
-  rebind 2 2030/1/1 00:00:01;
-  expire 2 2030/1/1 00:00:01;
-}
-EOF_CAT
-
-sed -i '/^#net.ipv4.ip_forward=1$/s/^#//' etc/sysctl.conf
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
--A POSTROUTING -o eth0 -j MASQUERADE
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
--A FORWARD -i eth0 -o wlan0 -m state --state RELATED,ESTABLISHED -j ACCEPT
--A FORWARD -i wlan0 -o eth0 -j ACCEPT
-COMMIT
-EOF_CAT
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nonat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-COMMIT
-EOF_CAT
-
-apt-get clean
-
-echo root:$passwd | chpasswd
-
-service ntp stop
-service ssh stop
-
-history -c
-
-sync
-EOF_CHROOT
-
-rm $root_dir/etc/resolv.conf
-rm $root_dir/usr/bin/qemu-arm-static
-
-# Unmount file systems
-
-umount $boot_dir $root_dir
-
-rmdir $boot_dir $root_dir
-
-zerofree $root_dev
diff --git a/HDL/scripts/debian.sh b/HDL/scripts/debian.sh
deleted file mode 100644
index 781d9a99..00000000
--- a/HDL/scripts/debian.sh
+++ /dev/null
@@ -1,281 +0,0 @@
-device=$1
-
-boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
-root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-
-# Choose mirror automatically, depending the geographic and network location
-mirror=http://httpredir.debian.org/debian
-
-distro=jessie
-arch=armhf
-
-hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
-
-passwd=changeme
-timezone=Europe/Brussels
-
-# Create partitions
-
-parted -s $device mklabel msdos
-parted -s $device mkpart primary fat16 4MB 16MB
-parted -s $device mkpart primary ext4 16MB 100%
-
-boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
-
-# Create file systems
-
-mkfs.vfat -v $boot_dev
-mkfs.ext4 -F -j $root_dev
-
-# Mount file systems
-
-mount $boot_dev $boot_dir
-mount $root_dev $root_dir
-
-# Copy files to the boot file system
-
-cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
-
-# Install Debian base system to the root file system
-
-debootstrap --foreign --arch $arch $distro $root_dir $mirror
-
-# Add missing configuration files and packages
-
-cp /etc/resolv.conf $root_dir/etc/
-cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
-
-cp patches/fw_env.config $root_dir/etc/
-
-mkdir -p $root_dir/usr/local/bin
-cp fw_printenv $root_dir/usr/local/bin/fw_printenv
-cp fw_printenv $root_dir/usr/local/bin/fw_setenv
-
-mkdir -p $root_dir/usr/local/sbin
-curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
-chmod +x $root_dir/usr/local/sbin/hostapd
-
-chroot $root_dir <<- EOF_CHROOT
-export LANG=C
-export LC_ALL=C
-
-# Add missing paths
-
-echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
-echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
-echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
-echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
-
-/debootstrap/debootstrap --second-stage
-
-cat <<- EOF_CAT > /etc/apt/sources.list
-deb $mirror $distro main contrib non-free
-deb-src $mirror $distro main contrib non-free
-deb $mirror $distro-updates main contrib non-free
-deb-src $mirror $distro-updates main contrib non-free
-deb http://security.debian.org/debian-security $distro/updates main contrib non-free
-deb-src http://security.debian.org/debian-security $distro/updates main contrib non-free
-EOF_CAT
-
-cat <<- EOF_CAT > etc/apt/apt.conf.d/99norecommends
-APT::Install-Recommends "0";
-APT::Install-Suggests "0";
-EOF_CAT
-
-cat <<- EOF_CAT > etc/fstab
-# /etc/fstab: static file system information.
-# <file system> <mount point>   <type>  <options>           <dump>  <pass>
-/dev/mmcblk0p2  /               ext4    errors=remount-ro   0       1
-/dev/mmcblk0p1  /boot           vfat    defaults            0       2
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/securetty
-
-# Serial Console for Xilinx Zynq-7000
-ttyPS0
-EOF_CAT
-
-echo red-pitaya > etc/hostname
-
-apt-get update
-apt-get -y upgrade
-
-apt-get -y install locales
-
-sed -i "/^# en_US.UTF-8 UTF-8$/s/^# //" etc/locale.gen
-locale-gen
-update-locale LANG=en_US.UTF-8
-
-echo $timezone > etc/timezone
-dpkg-reconfigure --frontend=noninteractive tzdata
-
-apt-get -y install openssh-server ca-certificates ntp ntpdate fake-hwclock \
-  usbutils psmisc lsof parted curl vim wpasupplicant hostapd isc-dhcp-server \
-  iw firmware-realtek firmware-ralink firmware-atheros firmware-brcm80211 \
-  ifplugd ntfs-3g
-
-sed -i 's/^PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
-
-touch etc/udev/rules.d/75-persistent-net-generator.rules
-
-cat <<- EOF_CAT > etc/network/interfaces.d/eth0
-iface eth0 inet dhcp
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/ifplugd
-INTERFACES="eth0"
-HOTPLUG_INTERFACES=""
-ARGS="-q -f -u0 -d10 -w -I"
-SUSPEND_ACTION="stop"
-EOF_CAT
-
-cat <<- EOF_CAT > etc/network/interfaces.d/wlan0
-allow-hotplug wlan0
-iface wlan0 inet static
-  address 192.168.42.1
-  netmask 255.255.255.0
-  post-up service hostapd restart
-  post-up service isc-dhcp-server restart
-  post-up iptables-restore < /etc/iptables.ipv4.nat
-  pre-down iptables-restore < /etc/iptables.ipv4.nonat
-  pre-down service isc-dhcp-server stop
-  pre-down service hostapd stop
-EOF_CAT
-
-cat <<- EOF_CAT > etc/hostapd/hostapd.conf
-interface=wlan0
-ssid=RedPitaya
-driver=nl80211
-hw_mode=g
-channel=6
-macaddr_acl=0
-auth_algs=1
-ignore_broadcast_ssid=0
-wpa=2
-wpa_passphrase=RedPitaya
-wpa_key_mgmt=WPA-PSK
-wpa_pairwise=CCMP
-rsn_pairwise=CCMP
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/hostapd
-DAEMON_CONF=/etc/hostapd/hostapd.conf
-
-if [ "\\\$1" = "start" ]
-then
-  iw wlan0 info > /dev/null 2>&1
-  if [ \\\$? -eq 0 ]
-  then
-    sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/sbin/hostapd
-  else
-    sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/local/sbin/hostapd
-  fi
-  echo \\\$DAEMON_SBIN > /run/hostapd.which
-elif [ "\\\$1" = "stop" ]
-then
-  DAEMON_SBIN=\\\$(cat /run/hostapd.which)
-fi
-EOF_CAT
-
-cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
-ddns-update-style none;
-default-lease-time 600;
-max-lease-time 7200;
-authoritative;
-log-facility local7;
-subnet 192.168.42.0 netmask 255.255.255.0 {
-  range 192.168.42.10 192.168.42.50;
-  option broadcast-address 192.168.42.255;
-  option routers 192.168.42.1;
-  default-lease-time 600;
-  max-lease-time 7200;
-  option domain-name "local";
-  option domain-name-servers 8.8.8.8, 8.8.4.4;
-}
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/dhcp/dhclient.conf
-timeout 20;
-
-lease {
-  interface "eth0";
-  fixed-address 192.168.1.100;
-  option subnet-mask 255.255.255.0;
-  renew 2 2030/1/1 00:00:01;
-  rebind 2 2030/1/1 00:00:01;
-  expire 2 2030/1/1 00:00:01;
-}
-EOF_CAT
-
-sed -i '/^#net.ipv4.ip_forward=1$/s/^#//' etc/sysctl.conf
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
--A POSTROUTING -o eth0 -j MASQUERADE
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
--A FORWARD -i eth0 -o wlan0 -m state --state RELATED,ESTABLISHED -j ACCEPT
--A FORWARD -i wlan0 -o eth0 -j ACCEPT
-COMMIT
-EOF_CAT
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nonat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-COMMIT
-EOF_CAT
-
-apt-get clean
-
-echo root:$passwd | chpasswd
-
-service ntp stop
-service ssh stop
-
-history -c
-
-sync
-EOF_CHROOT
-
-rm $root_dir/etc/resolv.conf
-rm $root_dir/usr/bin/qemu-arm-static
-
-# Unmount file systems
-
-umount $boot_dir $root_dir
-
-rmdir $boot_dir $root_dir
-
-zerofree $root_dev
diff --git a/HDL/scripts/project.tcl b/HDL/scripts/project.tcl
index a3fff02c..6fbfb86f 100644
--- a/HDL/scripts/project.tcl
+++ b/HDL/scripts/project.tcl
@@ -104,7 +104,7 @@ proc get_slice_pin {pin_name from to {cell_name ""}} {
 }
 
 
-source projects/$project_name/block_design.tcl
+source blockdesign-projects/$project_name/block_design.tcl
 
 rename cell {}
 rename module {}
@@ -118,7 +118,7 @@ make_wrapper -files [get_files $bd_path/system.bd] -top
 
 add_files -norecurse $bd_path/hdl/system_wrapper.v
 
-set files [glob -nocomplain projects/$project_name/*.v projects/$project_name/*.sv]
+set files [glob -nocomplain blockdesign-projects/$project_name/*.v blockdesign-projects/$project_name/*.sv]
 if {[llength $files] > 0} {
   add_files -norecurse $files
 }
diff --git a/HDL/scripts/ubuntu.sh b/HDL/scripts/ubuntu.sh
deleted file mode 100644
index 37cacc30..00000000
--- a/HDL/scripts/ubuntu.sh
+++ /dev/null
@@ -1,266 +0,0 @@
-device=$1
-
-boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
-root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-
-root_tar=ubuntu-base-14.04.5-core-armhf.tar.gz
-root_url=http://cdimage.ubuntu.com/ubuntu-base/releases/14.04/release/$root_tar
-
-hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
-
-passwd=changeme
-timezone=Europe/Brussels
-
-# Create partitions
-
-parted -s $device mklabel msdos
-parted -s $device mkpart primary fat16 4MB 16MB
-parted -s $device mkpart primary ext4 16MB 100%
-
-boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
-
-# Create file systems
-
-mkfs.vfat -v $boot_dev
-mkfs.ext4 -F -j $root_dev
-
-# Mount file systems
-
-mount $boot_dev $boot_dir
-mount $root_dev $root_dir
-
-# Copy files to the boot file system
-
-cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
-
-# Copy Ubuntu Core to the root file system
-
-test -f $root_tar || curl -L $root_url -o $root_tar
-
-tar -zxf $root_tar --directory=$root_dir
-
-# Add missing configuration files and packages
-
-cp /etc/resolv.conf $root_dir/etc/
-cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
-
-cp patches/fw_env.config $root_dir/etc/
-
-cp fw_printenv $root_dir/usr/local/bin/fw_printenv
-cp fw_printenv $root_dir/usr/local/bin/fw_setenv
-
-curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
-chmod +x $root_dir/usr/local/sbin/hostapd
-
-chroot $root_dir <<- EOF_CHROOT
-export LANG=C
-export LC_ALL=C
-
-# Add missing paths
-
-echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
-echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
-echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
-echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
-
-cat <<- EOF_CAT > etc/apt/apt.conf.d/99norecommends
-APT::Install-Recommends "0";
-APT::Install-Suggests "0";
-EOF_CAT
-
-cat <<- EOF_CAT > etc/fstab
-# /etc/fstab: static file system information.
-# <file system> <mount point>   <type>  <options>           <dump>  <pass>
-/dev/mmcblk0p2  /               ext4    errors=remount-ro   0       1
-/dev/mmcblk0p1  /boot           vfat    defaults            0       2
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/securetty
-
-# Serial Console for Xilinx Zynq-7000
-ttyPS0
-EOF_CAT
-
-sed 's/tty1/ttyPS0/g; s/38400/115200/' etc/init/tty1.conf > etc/init/ttyPS0.conf
-
-echo red-pitaya > etc/hostname
-
-sed -i '/^# deb .* universe$/s/^# //' etc/apt/sources.list
-
-sed -i '/### END INIT INFO/aexit 0' /etc/init.d/udev
-apt-get update
-apt-get -y upgrade
-sed -i '/### END INIT INFO/{n;d}' /etc/init.d/udev
-
-apt-get -y install locales
-
-locale-gen en_US.UTF-8
-update-locale LANG=en_US.UTF-8
-
-echo $timezone > etc/timezone
-dpkg-reconfigure --frontend=noninteractive tzdata
-
-apt-get -y install openssh-server ca-certificates ntp usbutils psmisc lsof \
-  parted curl less vim man-db iw wpasupplicant linux-firmware ntfs-3g
-
-sed -i 's/^PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
-
-apt-get -y install hostapd isc-dhcp-server iptables
-
-touch etc/udev/rules.d/75-persistent-net-generator.rules
-
-cat <<- EOF_CAT >> etc/network/interfaces.d/eth0
-allow-hotplug eth0
-iface eth0 inet dhcp
-EOF_CAT
-
-cat <<- EOF_CAT > etc/network/interfaces.d/wlan0
-allow-hotplug wlan0
-iface wlan0 inet static
-  address 192.168.42.1
-  netmask 255.255.255.0
-  post-up service hostapd restart
-  post-up service isc-dhcp-server restart
-  post-up iptables-restore < /etc/iptables.ipv4.nat
-  pre-down iptables-restore < /etc/iptables.ipv4.nonat
-  pre-down service isc-dhcp-server stop
-  pre-down service hostapd stop
-EOF_CAT
-
-cat <<- EOF_CAT > etc/hostapd/hostapd.conf
-interface=wlan0
-ssid=RedPitaya
-driver=nl80211
-hw_mode=g
-channel=6
-macaddr_acl=0
-auth_algs=1
-ignore_broadcast_ssid=0
-wpa=2
-wpa_passphrase=RedPitaya
-wpa_key_mgmt=WPA-PSK
-wpa_pairwise=CCMP
-rsn_pairwise=CCMP
-EOF_CAT
-
-cat <<- EOF_CAT > etc/default/hostapd
-DAEMON_CONF=/etc/hostapd/hostapd.conf
-
-if [ "\\\$1" = "start" ]
-then
-  iw wlan0 info > /dev/null 2>&1
-  if [ \\\$? -eq 0 ]
-  then
-    sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/sbin/hostapd
-  else
-    sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
-    DAEMON_SBIN=/usr/local/sbin/hostapd
-  fi
-  echo \\\$DAEMON_SBIN > /run/hostapd.which
-elif [ "\\\$1" = "stop" ]
-then
-  DAEMON_SBIN=\\\$(cat /run/hostapd.which)
-fi
-EOF_CAT
-
-cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
-ddns-update-style none;
-default-lease-time 600;
-max-lease-time 7200;
-authoritative;
-log-facility local7;
-subnet 192.168.42.0 netmask 255.255.255.0 {
-  range 192.168.42.10 192.168.42.50;
-  option broadcast-address 192.168.42.255;
-  option routers 192.168.42.1;
-  default-lease-time 600;
-  max-lease-time 7200;
-  option domain-name "local";
-  option domain-name-servers 8.8.8.8, 8.8.4.4;
-}
-EOF_CAT
-
-cat <<- EOF_CAT >> etc/dhcp/dhclient.conf
-timeout 20;
-
-lease {
-  interface "eth0";
-  fixed-address 192.168.1.100;
-  option subnet-mask 255.255.255.0;
-  renew 2 2030/1/1 00:00:01;
-  rebind 2 2030/1/1 00:00:01;
-  expire 2 2030/1/1 00:00:01;
-}
-EOF_CAT
-
-sed -i '/^#net.ipv4.ip_forward=1$/s/^#//' etc/sysctl.conf
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
--A POSTROUTING -o eth0 -j MASQUERADE
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
--A FORWARD -i eth0 -o wlan0 -m state --state RELATED,ESTABLISHED -j ACCEPT
--A FORWARD -i wlan0 -o eth0 -j ACCEPT
-COMMIT
-EOF_CAT
-
-cat <<- EOF_CAT > etc/iptables.ipv4.nonat
-*nat
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*mangle
-:PREROUTING ACCEPT [0:0]
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-:POSTROUTING ACCEPT [0:0]
-COMMIT
-*filter
-:INPUT ACCEPT [0:0]
-:FORWARD ACCEPT [0:0]
-:OUTPUT ACCEPT [0:0]
-COMMIT
-EOF_CAT
-
-apt-get clean
-
-echo root:$passwd | chpasswd
-
-service ntp stop
-service ssh stop
-
-history -c
-
-sync
-EOF_CHROOT
-
-rm $root_dir/etc/resolv.conf
-rm $root_dir/usr/bin/qemu-arm-static
-
-# Unmount file systems
-
-umount $boot_dir $root_dir
-
-rmdir $boot_dir $root_dir
-
-zerofree $root_dev