diff --git a/groovy/preInit/HV/hvcircuits.groovy b/groovy/preInit/HV/hvcircuits.groovy new file mode 100644 index 0000000..b3e26a7 --- /dev/null +++ b/groovy/preInit/HV/hvcircuits.groovy @@ -0,0 +1,118 @@ +package cbt.hvcircuits + +// pre 8-bit +def hv_circuit_4bit_operator_design_1 = content.createItem('hv_circuit_4bit_operator_design_1') +hv_circuit_4bit_operator_design_1.register() + +def hv_circuit_4bit_operator_design_2 = content.createItem('hv_circuit_4bit_operator_design_2') +hv_circuit_4bit_operator_design_2.register() + +def hv_circuit_4bit_operator_design_3 = content.createItem('hv_circuit_4bit_operator_design_3') +hv_circuit_4bit_operator_design_3.register() + +def hv_circuit_4bit_operator_design_4 = content.createItem('hv_circuit_4bit_operator_design_4') +hv_circuit_4bit_operator_design_4.register() + +def hv_circuit_4bit_operator_design_5 = content.createItem('hv_circuit_4bit_operator_design_5') +hv_circuit_4bit_operator_design_5.register() + +def hv_circuit_1bit_storage_circuit = content.createItem('hv_circuit_1bit_storage_circuit') +hv_circuit_1bit_storage_circuit.register() + +def hv_circuit_4bit_circuit_timings = content.createItem('hv_circuit_4bit_circuit_timings') +hv_circuit_4bit_circuit_timings.register() + +def hv_circuit_4bit_storage_circuit = content.createItem('hv_circuit_4bit_storage_circuit') +hv_circuit_4bit_storage_circuit.register() + +def hv_circuit_4bit_controller_chip_operations_center = content.createItem('hv_circuit_4bit_controller_chip_operations_center') +hv_circuit_4bit_controller_chip_operations_center.register() + +def hv_circuit_4bit_accelerator_configuration_chip = content.createItem('hv_circuit_4bit_accelerator_configuration_chip') +hv_circuit_4bit_accelerator_configuration_chip.register() + +def hv_circuit_4bit_hss_circuit_high_speed_speciality = content.createItem('hv_circuit_4bit_hss_circuit_high_speed_speciality') +hv_circuit_4bit_hss_circuit_high_speed_speciality.register() + +def hv_circuit_hub_4bit = content.createItem('hv_circuit_hub_4bit') +hv_circuit_hub_4bit.register() + +def hv_circuit_4bit_sensor_circuit = content.createItem('hv_circuit_4bit_sensor_circuit') +hv_circuit_4bit_sensor_circuit.register() + +def hv_circuit_4bit_sensor_io = content.createItem('hv_circuit_4bit_sensor_io') +hv_circuit_4bit_sensor_io.register() + +def hv_circuit_4bit_sensor_chip = content.createItem('hv_circuit_4bit_sensor_chip') +hv_circuit_4bit_sensor_chip.register() + +def hv_circuit_4bit_8bit_storage_compatibility_module = content.createItem('hv_circuit_4bit_8bit_storage_compatibility_module') +hv_circuit_4bit_8bit_storage_compatibility_module.register() + +def hv_circuit_ddssc4_circuit_timings = content.createItem('hv_circuit_ddssc4_circuit_timings') +hv_circuit_ddssc4_circuit_timings.register() + +def hv_circuit_4bit_refined_circuit_timings = content.createItem('hv_circuit_4bit_refined_circuit_timings') +hv_circuit_4bit_refined_circuit_timings.register() + +def hv_circuit_4bit_memory_component = content.createItem('hv_circuit_4bit_memory_component') +hv_circuit_4bit_memory_component.register() + +def hv_circuit_4bit_memory_bus = content.createItem('hv_circuit_4bit_memory_bus') +hv_circuit_4bit_memory_bus.register() + +def hv_circuit_4bit_cpu = content.createItem('hv_circuit_4bit_cpu') +hv_circuit_4bit_cpu.register() + +def hv_circuit_4bit_ultraspeedifier = content.createItem('hv_circuit_4bit_ultraspeedifier') +hv_circuit_4bit_ultraspeedifier.register() + +def hv_circuit_4bit_computer = content.createItem('hv_circuit_4bit_computer') +hv_circuit_4bit_computer.register() + +def hv_circuit_4bit_8bit_parallelizer_1 = content.createItem('hv_circuit_4bit_8bit_parallelizer_1') +hv_circuit_4bit_8bit_parallelizer_1.register() + +def hv_circuit_4bit_8bit_binary_extender = content.createItem('hv_circuit_4bit_8bit_binary_extender') +hv_circuit_4bit_8bit_binary_extender.register() + +def hv_circuit_4bit_gpu = content.createItem('hv_circuit_4bit_gpu') +hv_circuit_4bit_gpu.register() + +def hv_circuit_4bit_parallelizer_circuit_design_1 = content.createItem('hv_circuit_4bit_parallelizer_circuit_design_1') +hv_circuit_4bit_parallelizer_circuit_design_1.register() + +def hv_circuit_4bit_parallelizer_circuit_design_2 = content.createItem('hv_circuit_4bit_parallelizer_circuit_design_2') +hv_circuit_4bit_parallelizer_circuit_design_2.register() + +def hv_circuit_4bit_extended_memory_bus_lane = content.createItem('hv_circuit_4bit_extended_memory_bus_lane') +hv_circuit_4bit_extended_memory_bus_lane.register() + +def hv_circuit_4bit_refined_cpu = content.createItem('hv_circuit_4bit_refined_cpu') +hv_circuit_4bit_refined_cpu.register() + +def hv_circuit_super4bit_parax = content.createItem('hv_circuit_super4bit_parax') +hv_circuit_super4bit_parax.register() + +def hv_circuit_extended_4bit_sensor_chip = content.createItem('hv_circuit_extended_4bit_sensor_chip') +hv_circuit_extended_4bit_sensor_chip.register() + +def hv_circuit_4bit_8bit_compatibility_layer_module = content.createItem('hv_circuit_4bit_8bit_compatibility_layer_module') +hv_circuit_4bit_8bit_compatibility_layer_module.register() + +def hv_circuit_4bit_8bit_translation_module = content.createItem('hv_circuit_4bit_8bit_translation_module') +hv_circuit_4bit_8bit_translation_module.register() + +def hv_circuit_4bit_8bit_quackity_module = content.createItem('hv_circuit_4bit_8bit_quackity_module') +hv_circuit_4bit_8bit_quackity_module.register() + +def hv_circuit_8bit_support_layer_module = content.createItem('hv_circuit_8bit_support_layer_module') +hv_circuit_8bit_support_layer_module.register() + +def hv_circuit_4bit_megacruncher = content.createItem('hv_circuit_4bit_megacruncher') +hv_circuit_4bit_megacruncher.register() + +// full 8bit processing + + + diff --git a/groovy/preInit/LV/lvcircuits.groovy b/groovy/preInit/LV/lvcircuits.groovy new file mode 100644 index 0000000..bc1bd5c --- /dev/null +++ b/groovy/preInit/LV/lvcircuits.groovy @@ -0,0 +1,118 @@ +package cbt.lvcircuits + +// pre 8-bit +def lv_circuit_4bit_operator_design_1 = content.createItem('lv_circuit_4bit_operator_design_1') +lv_circuit_4bit_operator_design_1.register() + +def lv_circuit_4bit_operator_design_2 = content.createItem('lv_circuit_4bit_operator_design_2') +lv_circuit_4bit_operator_design_2.register() + +def lv_circuit_4bit_operator_design_3 = content.createItem('lv_circuit_4bit_operator_design_3') +lv_circuit_4bit_operator_design_3.register() + +def lv_circuit_4bit_operator_design_4 = content.createItem('lv_circuit_4bit_operator_design_4') +lv_circuit_4bit_operator_design_4.register() + +def lv_circuit_4bit_operator_design_5 = content.createItem('lv_circuit_4bit_operator_design_5') +lv_circuit_4bit_operator_design_5.register() + +def lv_circuit_1bit_storage_circuit = content.createItem('lv_circuit_1bit_storage_circuit') +lv_circuit_1bit_storage_circuit.register() + +def lv_circuit_4bit_circuit_timings = content.createItem('lv_circuit_4bit_circuit_timings') +lv_circuit_4bit_circuit_timings.register() + +def lv_circuit_4bit_storage_circuit = content.createItem('lv_circuit_4bit_storage_circuit') +lv_circuit_4bit_storage_circuit.register() + +def lv_circuit_4bit_controller_chip_operations_center = content.createItem('lv_circuit_4bit_controller_chip_operations_center') +lv_circuit_4bit_controller_chip_operations_center.register() + +def lv_circuit_4bit_accelerator_configuration_chip = content.createItem('lv_circuit_4bit_accelerator_configuration_chip') +lv_circuit_4bit_accelerator_configuration_chip.register() + +def lv_circuit_4bit_hss_circuit_high_speed_speciality = content.createItem('lv_circuit_4bit_hss_circuit_high_speed_speciality') +lv_circuit_4bit_hss_circuit_high_speed_speciality.register() + +def lv_circuit_hub_4bit = content.createItem('lv_circuit_hub_4bit') +lv_circuit_hub_4bit.register() + +def lv_circuit_4bit_sensor_circuit = content.createItem('lv_circuit_4bit_sensor_circuit') +lv_circuit_4bit_sensor_circuit.register() + +def lv_circuit_4bit_sensor_io = content.createItem('lv_circuit_4bit_sensor_io') +lv_circuit_4bit_sensor_io.register() + +def lv_circuit_4bit_sensor_chip = content.createItem('lv_circuit_4bit_sensor_chip') +lv_circuit_4bit_sensor_chip.register() + +def lv_circuit_4bit_8bit_storage_compatibility_module = content.createItem('lv_circuit_4bit_8bit_storage_compatibility_module') +lv_circuit_4bit_8bit_storage_compatibility_module.register() + +def lv_circuit_ddssc4_circuit_timings = content.createItem('lv_circuit_ddssc4_circuit_timings') +lv_circuit_ddssc4_circuit_timings.register() + +def lv_circuit_4bit_refined_circuit_timings = content.createItem('lv_circuit_4bit_refined_circuit_timings') +lv_circuit_4bit_refined_circuit_timings.register() + +def lv_circuit_4bit_memory_component = content.createItem('lv_circuit_4bit_memory_component') +lv_circuit_4bit_memory_component.register() + +def lv_circuit_4bit_memory_bus = content.createItem('lv_circuit_4bit_memory_bus') +lv_circuit_4bit_memory_bus.register() + +def lv_circuit_4bit_cpu = content.createItem('lv_circuit_4bit_cpu') +lv_circuit_4bit_cpu.register() + +def lv_circuit_4bit_ultraspeedifier = content.createItem('lv_circuit_4bit_ultraspeedifier') +lv_circuit_4bit_ultraspeedifier.register() + +def lv_circuit_4bit_computer = content.createItem('lv_circuit_4bit_computer') +lv_circuit_4bit_computer.register() + +def lv_circuit_4bit_8bit_parallelizer_1 = content.createItem('lv_circuit_4bit_8bit_parallelizer_1') +lv_circuit_4bit_8bit_parallelizer_1.register() + +def lv_circuit_4bit_8bit_binary_extender = content.createItem('lv_circuit_4bit_8bit_binary_extender') +lv_circuit_4bit_8bit_binary_extender.register() + +def lv_circuit_4bit_gpu = content.createItem('lv_circuit_4bit_gpu') +lv_circuit_4bit_gpu.register() + +def lv_circuit_4bit_parallelizer_circuit_design_1 = content.createItem('lv_circuit_4bit_parallelizer_circuit_design_1') +lv_circuit_4bit_parallelizer_circuit_design_1.register() + +def lv_circuit_4bit_parallelizer_circuit_design_2 = content.createItem('lv_circuit_4bit_parallelizer_circuit_design_2') +lv_circuit_4bit_parallelizer_circuit_design_2.register() + +def lv_circuit_4bit_extended_memory_bus_lane = content.createItem('lv_circuit_4bit_extended_memory_bus_lane') +lv_circuit_4bit_extended_memory_bus_lane.register() + +def lv_circuit_4bit_refined_cpu = content.createItem('lv_circuit_4bit_refined_cpu') +lv_circuit_4bit_refined_cpu.register() + +def lv_circuit_super4bit_parax = content.createItem('lv_circuit_super4bit_parax') +lv_circuit_super4bit_parax.register() + +def lv_circuit_extended_4bit_sensor_chip = content.createItem('lv_circuit_extended_4bit_sensor_chip') +lv_circuit_extended_4bit_sensor_chip.register() + +def lv_circuit_4bit_8bit_compatibility_layer_module = content.createItem('lv_circuit_4bit_8bit_compatibility_layer_module') +lv_circuit_4bit_8bit_compatibility_layer_module.register() + +def lv_circuit_4bit_8bit_translation_module = content.createItem('lv_circuit_4bit_8bit_translation_module') +lv_circuit_4bit_8bit_translation_module.register() + +def lv_circuit_4bit_8bit_quackity_module = content.createItem('lv_circuit_4bit_8bit_quackity_module') +lv_circuit_4bit_8bit_quackity_module.register() + +def lv_circuit_8bit_support_layer_module = content.createItem('lv_circuit_8bit_support_layer_module') +lv_circuit_8bit_support_layer_module.register() + +def lv_circuit_4bit_megacruncher = content.createItem('lv_circuit_4bit_megacruncher') +lv_circuit_4bit_megacruncher.register() + +// full 8bit processing + + + diff --git a/groovy/preInit/MV/mvcircuits.groovy b/groovy/preInit/MV/mvcircuits.groovy new file mode 100644 index 0000000..406ea17 --- /dev/null +++ b/groovy/preInit/MV/mvcircuits.groovy @@ -0,0 +1,118 @@ +package cbt.mvcircuits + +// pre 8-bit +def mv_circuit_4bit_operator_design_1 = content.createItem('mv_circuit_4bit_operator_design_1') +mv_circuit_4bit_operator_design_1.register() + +def mv_circuit_4bit_operator_design_2 = content.createItem('mv_circuit_4bit_operator_design_2') +mv_circuit_4bit_operator_design_2.register() + +def mv_circuit_4bit_operator_design_3 = content.createItem('mv_circuit_4bit_operator_design_3') +mv_circuit_4bit_operator_design_3.register() + +def mv_circuit_4bit_operator_design_4 = content.createItem('mv_circuit_4bit_operator_design_4') +mv_circuit_4bit_operator_design_4.register() + +def mv_circuit_4bit_operator_design_5 = content.createItem('mv_circuit_4bit_operator_design_5') +mv_circuit_4bit_operator_design_5.register() + +def mv_circuit_1bit_storage_circuit = content.createItem('mv_circuit_1bit_storage_circuit') +mv_circuit_1bit_storage_circuit.register() + +def mv_circuit_4bit_circuit_timings = content.createItem('mv_circuit_4bit_circuit_timings') +mv_circuit_4bit_circuit_timings.register() + +def mv_circuit_4bit_storage_circuit = content.createItem('mv_circuit_4bit_storage_circuit') +mv_circuit_4bit_storage_circuit.register() + +def mv_circuit_4bit_controller_chip_operations_center = content.createItem('mv_circuit_4bit_controller_chip_operations_center') +mv_circuit_4bit_controller_chip_operations_center.register() + +def mv_circuit_4bit_accelerator_configuration_chip = content.createItem('mv_circuit_4bit_accelerator_configuration_chip') +mv_circuit_4bit_accelerator_configuration_chip.register() + +def mv_circuit_4bit_hss_circuit_high_speed_speciality = content.createItem('mv_circuit_4bit_hss_circuit_high_speed_speciality') +mv_circuit_4bit_hss_circuit_high_speed_speciality.register() + +def mv_circuit_hub_4bit = content.createItem('mv_circuit_hub_4bit') +mv_circuit_hub_4bit.register() + +def mv_circuit_4bit_sensor_circuit = content.createItem('mv_circuit_4bit_sensor_circuit') +mv_circuit_4bit_sensor_circuit.register() + +def mv_circuit_4bit_sensor_io = content.createItem('mv_circuit_4bit_sensor_io') +mv_circuit_4bit_sensor_io.register() + +def mv_circuit_4bit_sensor_chip = content.createItem('mv_circuit_4bit_sensor_chip') +mv_circuit_4bit_sensor_chip.register() + +def mv_circuit_4bit_8bit_storage_compatibility_module = content.createItem('mv_circuit_4bit_8bit_storage_compatibility_module') +mv_circuit_4bit_8bit_storage_compatibility_module.register() + +def mv_circuit_ddssc4_circuit_timings = content.createItem('mv_circuit_ddssc4_circuit_timings') +mv_circuit_ddssc4_circuit_timings.register() + +def mv_circuit_4bit_refined_circuit_timings = content.createItem('mv_circuit_4bit_refined_circuit_timings') +mv_circuit_4bit_refined_circuit_timings.register() + +def mv_circuit_4bit_memory_component = content.createItem('mv_circuit_4bit_memory_component') +mv_circuit_4bit_memory_component.register() + +def mv_circuit_4bit_memory_bus = content.createItem('mv_circuit_4bit_memory_bus') +mv_circuit_4bit_memory_bus.register() + +def mv_circuit_4bit_cpu = content.createItem('mv_circuit_4bit_cpu') +mv_circuit_4bit_cpu.register() + +def mv_circuit_4bit_ultraspeedifier = content.createItem('mv_circuit_4bit_ultraspeedifier') +mv_circuit_4bit_ultraspeedifier.register() + +def mv_circuit_4bit_computer = content.createItem('mv_circuit_4bit_computer') +mv_circuit_4bit_computer.register() + +def mv_circuit_4bit_8bit_parallelizer_1 = content.createItem('mv_circuit_4bit_8bit_parallelizer_1') +mv_circuit_4bit_8bit_parallelizer_1.register() + +def mv_circuit_4bit_8bit_binary_extender = content.createItem('mv_circuit_4bit_8bit_binary_extender') +mv_circuit_4bit_8bit_binary_extender.register() + +def mv_circuit_4bit_gpu = content.createItem('mv_circuit_4bit_gpu') +mv_circuit_4bit_gpu.register() + +def mv_circuit_4bit_parallelizer_circuit_design_1 = content.createItem('mv_circuit_4bit_parallelizer_circuit_design_1') +mv_circuit_4bit_parallelizer_circuit_design_1.register() + +def mv_circuit_4bit_parallelizer_circuit_design_2 = content.createItem('mv_circuit_4bit_parallelizer_circuit_design_2') +mv_circuit_4bit_parallelizer_circuit_design_2.register() + +def mv_circuit_4bit_extended_memory_bus_lane = content.createItem('mv_circuit_4bit_extended_memory_bus_lane') +mv_circuit_4bit_extended_memory_bus_lane.register() + +def mv_circuit_4bit_refined_cpu = content.createItem('mv_circuit_4bit_refined_cpu') +mv_circuit_4bit_refined_cpu.register() + +def mv_circuit_super4bit_parax = content.createItem('mv_circuit_super4bit_parax') +mv_circuit_super4bit_parax.register() + +def mv_circuit_extended_4bit_sensor_chip = content.createItem('mv_circuit_extended_4bit_sensor_chip') +mv_circuit_extended_4bit_sensor_chip.register() + +def mv_circuit_4bit_8bit_compatibility_layer_module = content.createItem('mv_circuit_4bit_8bit_compatibility_layer_module') +mv_circuit_4bit_8bit_compatibility_layer_module.register() + +def mv_circuit_4bit_8bit_translation_module = content.createItem('mv_circuit_4bit_8bit_translation_module') +mv_circuit_4bit_8bit_translation_module.register() + +def mv_circuit_4bit_8bit_quackity_module = content.createItem('mv_circuit_4bit_8bit_quackity_module') +mv_circuit_4bit_8bit_quackity_module.register() + +def mv_circuit_8bit_support_layer_module = content.createItem('mv_circuit_8bit_support_layer_module') +mv_circuit_8bit_support_layer_module.register() + +def mv_circuit_4bit_megacruncher = content.createItem('mv_circuit_4bit_megacruncher') +mv_circuit_4bit_megacruncher.register() + +// full 8bit processing + + + diff --git a/groovy/preInit/MetaItems/metacircuits.groovy b/groovy/preInit/MetaItems/metacircuits.groovy index 6ecbbae..4cb6d3e 100644 --- a/groovy/preInit/MetaItems/metacircuits.groovy +++ b/groovy/preInit/MetaItems/metacircuits.groovy @@ -78,7 +78,7 @@ projectcbtcircuitslv.addItem(52, "circuit.lv.eg_plasma_generator"); projectcbtcircuitslv.addItem(53, "circuit.lv.eg_semi_fluid_generator"); projectcbtcircuitslv.addItem(54, "circuit.lv.eg_steam_turbine"); -log.infoMC("Project CBT: Admit LV Circuits: Stage Components") +log.infoMC("Project CBT: Admit LV Circuits: Stage Machine-Specific Circuits") projectcbtcircuitslv.addItem(55, "circuit.lv.component.sus"); projectcbtcircuitslv.addItem(56, "circuit.lv.component.gyroscope"); @@ -112,7 +112,7 @@ log.infoMC("Project CBT: Admit LV Circuits - Done") StandardMetaItem projectcbtcircuitsmv = new StandardMetaItem((short)2); projectcbtcircuitsmv.setRegistryName("projectcbt_circuits_mv") -log.infoMC("Project CBT: Admit MV Circuits") +log.infoMC("Project CBT: Admit MV Circuits: Stage Machine-Specific Components") projectcbtcircuitsmv.addItem(0, "circuit.mv.motherboard_plating"); projectcbtcircuitsmv.addItem(1, "circuit.mv.alloy_smelter"); @@ -170,6 +170,35 @@ projectcbtcircuitsmv.addItem(52, "circuit.mv.eg_plasma_generator"); projectcbtcircuitsmv.addItem(53, "circuit.mv.eg_semi_fluid_generator"); projectcbtcircuitsmv.addItem(54, "circuit.mv.eg_steam_turbine"); +log.infoMC("Project CBT: Admit MV Circuits: Stage Components") + +projectcbtcircuitsmv.addItem(55, "circuit.mv.component.sus"); +projectcbtcircuitsmv.addItem(56, "circuit.mv.component.gyroscope"); +projectcbtcircuitsmv.addItem(57, "circuit.mv.component.led"); +projectcbtcircuitsmv.addItem(58, "circuit.mv.component.oscillator"); +projectcbtcircuitsmv.addItem(59, "circuit.mv.component.sound"); +projectcbtcircuitsmv.addItem(60, "circuit.mv.component.voltage_regulator"); +projectcbtcircuitsmv.addItem(61, "circuit.mv.component.diode"); +projectcbtcircuitsmv.addItem(62, "circuit.mv.component.capacitor"); +projectcbtcircuitsmv.addItem(63, "circuit.mv.component.resistor"); +projectcbtcircuitsmv.addItem(64, "circuit.mv.component.voltage_regulator"); +projectcbtcircuitsmv.addItem(65, "circuit.mv.component.configuration_chip"); +projectcbtcircuitsmv.addItem(66, "circuit.mv.component.sound_chip"); +projectcbtcircuitsmv.addItem(67, "circuit.mv.component.bus_chip"); +projectcbtcircuitsmv.addItem(68, "circuit.mv.component.memory"); +projectcbtcircuitsmv.addItem(69, "circuit.mv.component.motor"); +projectcbtcircuitsmv.addItem(70, "circuit.mv.component.bios"); +projectcbtcircuitsmv.addItem(71, "circuit.mv.component.piston"); +projectcbtcircuitsmv.addItem(72, "circuit.mv.component.heating_coil"); +projectcbtcircuitsmv.addItem(73, "circuit.mv.component.cooling_coil"); +projectcbtcircuitsmv.addItem(74, "circuit.mv.component.voltage_regulator"); +projectcbtcircuitsmv.addItem(75, "circuit.mv.component.configuration_chip"); +projectcbtcircuitsmv.addItem(76, "circuit.mv.component.backlight"); +projectcbtcircuitsmv.addItem(77, "circuit.mv.component.storage"); +projectcbtcircuitsmv.addItem(78, "circuit.mv.component.processor_socket"); +projectcbtcircuitsmv.addItem(79, "circuit.mv.component.interface"); +projectcbtcircuitsmv.addItem(80, "circuit.mv.component.filter_chip"); + log.infoMC("Project CBT: Admit MV Circuits - Done") StandardMetaItem projectcbtcircuitshv = new StandardMetaItem((short)2); diff --git a/groovy/preInit/UHV/uhvcircuits.groovy b/groovy/preInit/UHV/uhvcircuits.groovy index 4267901..e063edd 100644 --- a/groovy/preInit/UHV/uhvcircuits.groovy +++ b/groovy/preInit/UHV/uhvcircuits.groovy @@ -1,3 +1,5 @@ +package cbt.uhvcircuits + // pre 8-bit def uhv_circuit_4bit_operator_design_1 = content.createItem('uhv_circuit_4bit_operator_design_1') uhv_circuit_4bit_operator_design_1.register() diff --git a/groovy/preInit/UHV/uhvmaterials.groovy b/groovy/preInit/UHV/uhvmaterials.groovy index e69de29..6e5a8e1 100644 --- a/groovy/preInit/UHV/uhvmaterials.groovy +++ b/groovy/preInit/UHV/uhvmaterials.groovy @@ -0,0 +1,17 @@ +package cbt.uhvmaterials + +// tetraschrabadic_trinaquadium items and bullshit - conductor + +def schrabidium_naquadah_4_3_alloy = content.createItem('tetraschrabadic_trinaquadium') +schrabidium_naquadah_4_3_alloy.register() + +// urephittium - insulator +// euphemium uranium nitan blend + +def urephittium_alloy = content.createItem('urephittium') +urephittium_alloy.register() + +// thorassium is a new material + +def thorassium_alloy = content.createItem('thorassium') +thorassium_alloy.register() \ No newline at end of file diff --git a/groovy/preInit/UHV/uhvmaterialsoretip.groovy b/groovy/preInit/UHV/uhvmaterialsoretip.groovy new file mode 100644 index 0000000..b231053 --- /dev/null +++ b/groovy/preInit/UHV/uhvmaterialsoretip.groovy @@ -0,0 +1,14 @@ +import net.minecraftforge.event.entity.player.ItemTooltipEvent + +event_manager.listen { ItemTooltipEvent event -> + if (ItemStack.areItemsEqual(event.getItemStack(), item('cbt:tetraschrabadic_trinaquadium'))) { + event.getToolTip().add('UHV tier alloy, now go fuck yourselves in the toilet.') + event.getToolTip().add('Contains 4-Schrabidium, 3-Naquandah') + } +} + +event_manager.listen { ItemTooltipEvent event -> + if (ItemStack.areItemsEqual(event.getItemStack(), item('cbt:urephittium'))) { + event.getToolTip().add('Euphemium-Unobtanium Alloy, because fuck you.') + } +} diff --git a/groovy/preInit/UHV/uhvwireshapes.groovy b/groovy/preInit/UHV/uhvwireshapes.groovy new file mode 100644 index 0000000..534b913 --- /dev/null +++ b/groovy/preInit/UHV/uhvwireshapes.groovy @@ -0,0 +1,279 @@ +package cbt.uhvwireshapes + +// =========================================================== +// tetraschrabadic trinaquadium wire +// =========================================================== + +// unformatted wire because FUCK YOU! +def schrabidium_naquadah_4_3_alloy_wireunformatted = content.createItem('tetraschrabadic_trinaquadium_wireunformatted') +schrabidium_naquadah_4_3_alloy_wireunformatted.register() + +// single wire double wire +def alloy_4_sa_3_nq_wire_s_h = content.createItem('tetraschrabadic_trinaquadium_wire_s_h') +alloy_4_sa_3_nq_wire_s_h.register() + +def alloy_4_sa_3_nq_wire_s_v = content.createItem('tetraschrabadic_trinaquadium_wire_s_v') +alloy_4_sa_3_nq_wire_s_v.register() + +def alloy_4_sa_3_nq_wire_d_h = content.createItem('tetraschrabadic_trinaquadium_wire_d_h') +alloy_4_sa_3_nq_wire_d_h.register() + +def alloy_4_sa_3_nq_wire_d_v = content.createItem('tetraschrabadic_trinaquadium_wire_d_v') +alloy_4_sa_3_nq_wire_d_v.register() + +// four way all equal +def alloy_4_sa_3_nq_wire_4way_ae_s = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ae_s') +alloy_4_sa_3_nq_wire_4way_ae_s.register() + +def alloy_4_sa_3_nq_wire_4way_ae_d = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ae_d') +alloy_4_sa_3_nq_wire_4way_ae_d.register() + +// three way all equal +def alloy_4_sa_3_nq_wire_3way_ae_s_pos1 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1') +alloy_4_sa_3_nq_wire_3way_ae_s_pos1.register() + +def alloy_4_sa_3_nq_wire_3way_ae_s_pos2 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2') +alloy_4_sa_3_nq_wire_3way_ae_s_pos2.register() + +def alloy_4_sa_3_nq_wire_3way_ae_s_pos3 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3') +alloy_4_sa_3_nq_wire_3way_ae_s_pos3.register() + +def alloy_4_sa_3_nq_wire_3way_ae_s_pos4 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4') +alloy_4_sa_3_nq_wire_3way_ae_s_pos4.register() + +def alloy_4_sa_3_nq_wire_3way_ae_d_pos1 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_d_pos1') +alloy_4_sa_3_nq_wire_3way_ae_d_pos1.register() + +def alloy_4_sa_3_nq_wire_3way_ae_d_pos2 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_d_pos2') +alloy_4_sa_3_nq_wire_3way_ae_d_pos2.register() + +def alloy_4_sa_3_nq_wire_3way_ae_d_pos3 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_d_pos3') +alloy_4_sa_3_nq_wire_3way_ae_d_pos3.register() + +def alloy_4_sa_3_nq_wire_3way_ae_d_pos4 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_d_pos4') +alloy_4_sa_3_nq_wire_3way_ae_d_pos4.register() + +//corner all equal +def alloy_4_sa_3_nq_wire_corner_ae_s_pos1 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_s_pos1') +alloy_4_sa_3_nq_wire_corner_ae_s_pos1.register() + +def alloy_4_sa_3_nq_wire_corner_ae_s_pos2 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_s_pos2') +alloy_4_sa_3_nq_wire_corner_ae_s_pos2.register() + +def alloy_4_sa_3_nq_wire_corner_ae_s_pos3 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_s_pos3') +alloy_4_sa_3_nq_wire_corner_ae_s_pos3.register() + +def alloy_4_sa_3_nq_wire_corner_ae_s_pos4 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_s_pos4') +alloy_4_sa_3_nq_wire_corner_ae_s_pos4.register() + +def alloy_4_sa_3_nq_wire_corner_ae_d_pos1 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_d_pos1') +alloy_4_sa_3_nq_wire_corner_ae_d_pos1.register() + +def alloy_4_sa_3_nq_wire_corner_ae_d_pos2 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_d_pos2') +alloy_4_sa_3_nq_wire_corner_ae_d_pos2.register() + +def alloy_4_sa_3_nq_wire_corner_ae_d_pos3 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_d_pos3') +alloy_4_sa_3_nq_wire_corner_ae_d_pos3.register() + +def alloy_4_sa_3_nq_wire_corner_ae_d_pos4 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ae_d_pos4') +alloy_4_sa_3_nq_wire_corner_ae_d_pos4.register() + +//four way unequal - single double cross + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos1 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos1') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos1.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos2 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos2') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos2.register() + +//four way unequal - single double merge + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos1_1 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos1_1') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos1_1.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos1_2 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos1_2') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos1_2.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos1_3 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos1_3') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos1_3.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos2_1 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos2_1') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos2_1.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos2_2 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos2_2') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos2_2.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos2_3 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos2_3') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos2_3.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos3_1 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos3_1') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos3_1.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos3_2 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos3_2') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos3_2.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos3_3 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos3_3') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos3_3.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos4_1 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos4_1') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos4_1.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos4_2 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos4_2') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos4_2.register() + +def alloy_4_sa_3_nq_wire_4way_ue_sd_pos4_3 = content.createItem('tetraschrabadic_trinaquadium_wire_4way_ue_sd_pos4_3') +alloy_4_sa_3_nq_wire_4way_ue_sd_pos4_3.register() + +//three-way merge unequal + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_1 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1_1') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_1.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_2 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1_2') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_2.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_3 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1_3') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_3.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_4 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1_4') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_4.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_5 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1_5') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_5.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_6 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos1_6') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos1_6.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_1 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2_1') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_1.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_2 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2_2') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_2.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_3 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2_3') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_3.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_4 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2_4') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_4.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_5 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2_5') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_5.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_6 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos2_6') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos2_6.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_1 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3_1') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_1.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_2 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3_2') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_2.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_3 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3_3') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_3.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_4 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3_4') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_4.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_5 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3_5') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_5.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_6 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos3_6') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos3_6.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_1 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4_1') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_1.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_2 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4_2') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_2.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_3 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4_3') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_3.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_4 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4_4') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_4.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_5 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4_5') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_5.register() + +def alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_6 = content.createItem('tetraschrabadic_trinaquadium_wire_3way_ae_s_pos4_6') +alloy_4_sa_3_nq_wire_3way_ae_sd_pos4_6.register() + +// corner unequal +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos1_1 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos1_1') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos1_1.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos1_2 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos1_2') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos1_2.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos2_1 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos2_1') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos2_1.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos2_2 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos2_2') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos2_2.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos3_1 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos3_1') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos3_1.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos3_2 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos3_2') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos3_2.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos4_1 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos4_1') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos4_1.register() + +def alloy_4_sa_3_nq_wire_corner_ue_sd_pos4_2 = content.createItem('tetraschrabadic_trinaquadium_wire_corner_ue_sd_pos4_2') +alloy_4_sa_3_nq_wire_corner_ue_sd_pos4_2.register() + +// LOGIC GATES SECTION + +//4sa3nq logic gate - basic +def alloy_4_sa_3_nq_circuitpart_transistor1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_transistor1') +alloy_4_sa_3_nq_circuitpart_transistor1.register() + +def alloy_4_sa_3_nq_circuitpart_notgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_notgate') +alloy_4_sa_3_nq_circuitpart_notgate.register() + +def alloy_4_sa_3_nq_circuitpart_andgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_andgate') +alloy_4_sa_3_nq_circuitpart_andgate.register() + +def alloy_4_sa_3_nq_circuitpart_orgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_orgate') +alloy_4_sa_3_nq_circuitpart_orgate.register() + +def alloy_4_sa_3_nq_circuitpart_norgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_norgate') +alloy_4_sa_3_nq_circuitpart_norgate.register() + +def alloy_4_sa_3_nq_circuitpart_nandgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_nandgate') +alloy_4_sa_3_nq_circuitpart_nandgate.register() + +def alloy_4_sa_3_nq_circuitpart_xorgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_xorgate') +alloy_4_sa_3_nq_circuitpart_xorgate.register() + +def alloy_4_sa_3_nq_circuitpart_xnorgate = content.createItem('tetraschrabadic_trinaquadium_circuitpart_xnorgate') +alloy_4_sa_3_nq_circuitpart_xnorgate.register() + +def alloy_4_sa_3_nq_circuitpart_capacitor1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_capacitor1') +alloy_4_sa_3_nq_circuitpart_capacitor1.register() + +//4sa3nq logic gate circut operands parts +def alloy_4_sa_3_nq_circuitpart_halfadder1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_halfadder1') +alloy_4_sa_3_nq_circuitpart_halfadder1.register() + +def alloy_4_sa_3_nq_circuitpart_fulladder1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_fulladder1') +alloy_4_sa_3_nq_circuitpart_fulladder1.register() + +def alloy_4_sa_3_nq_circuitpart_halfsubtractor1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_halfsubtractor1') +alloy_4_sa_3_nq_circuitpart_halfsubtractor1.register() + +def alloy_4_sa_3_nq_circuitpart_fullsubtractor1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_fullsubtractor1') +alloy_4_sa_3_nq_circuitpart_fullsubtractor1.register() + +def alloy_4_sa_3_nq_circuitpart_binarymultiplicator1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_binarymultiplicator1') +alloy_4_sa_3_nq_circuitpart_binarymultiplicator1.register() + +def alloy_4_sa_3_nq_circuitpart_binarydivider1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_binarydivider1') +alloy_4_sa_3_nq_circuitpart_binarydivider1.register() + +def alloy_4_sa_3_nq_circuitpart_integratedaddsubtract1 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_integratedaddsubtract1') +alloy_4_sa_3_nq_circuitpart_integratedaddsubtract1.register() + +def alloy_4_sa_3_nq_circuitpart_integratedaddsubtract2 = content.createItem('tetraschrabadic_trinaquadium_circuitpart_integratedaddsubtract2') +alloy_4_sa_3_nq_circuitpart_integratedaddsubtract2.register() \ No newline at end of file diff --git a/index.toml b/index.toml index 557b5b7..d530d19 100644 --- a/index.toml +++ b/index.toml @@ -22,7 +22,7 @@ hash = "189b1af95d661151e054cea10c91b3d754e4de4d3fecfb074c1fb29476f7167b" [[files]] file = "README.md" -hash = "81648594cfe639ac439aa2959f3f63adf4313d96a615916433329ddb2cd6d890" +hash = "71f41b80cc9587a408f0eb58fd6ac994ab6e5d7265c647507efa576c2d4ec496" [[files]] file = "SECURITY.md" @@ -66,7 +66,7 @@ hash = "e7473f41de545cf5738cd5d25572446e564edf25056e6b3918fa4dc214bc7a78" [[files]] file = "config/AppliedEnergistics2/CustomRecipes.cfg" -hash = "77caefabf9fdfe920aebc0158b31dd1c29679a603d4a0bac6ea8c016974b01ae" +hash = "a00b08eea70d34ed5ebc58b1d2ca40328bdd3877ad99cf024f71b20e373b4bd6" [[files]] file = "config/AppliedEnergistics2/Facades.cfg" @@ -74,11 +74,11 @@ hash = "661cd844fe44c188c95368174e115681b69d63f5b6f62a676bb9331860599ebb" [[files]] file = "config/AppliedEnergistics2/VersionChecker.cfg" -hash = "dfdcec3e322c766667df97081772d85489a3230f24b247c2bbdf02dc52eead68" +hash = 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+file = "scripts/gregmeth/gregmeth_recipes.zs" +hash = "dcd166bba96bf59cd6b4b9e3fac92e8ab903dc12a28abe4ff2a44cfe2ae78faf" + +[[files]] +file = "scripts/materials/elements.zs" +hash = "38e88781dff36d6b68fa91a4418b3363dcc1c6fd5d6335ad0beffa6184301873" + +[[files]] +file = "scripts/materials/uhvmaterials.groovy" +hash = "8787564410b33acd186385acf1c119597e54bd346db949aa22c76376a7518af8" + +[[files]] +file = "scripts/misc/human_resources_multiblock.zs" +hash = "8bff9b713ade233f35a321e31f464d046b65b12c6398923ea58f94170d56988d" + +[[files]] +file = "scripts/misc/materials.zs" +hash = "a1c6daa918dfa5897de336354b58bbc6195dfdd1c150dbe480299e6042c03a8b" + [[files]] file = "scripts/misc/uhv.zs" hash = "461b96dea144f0b9dd57d91068410e8a9b90aaeb1b51df2c84fde33e5a6569fe" diff --git a/mods/animales.pw.toml b/mods/animales.pw.toml new file mode 100644 index 0000000..4eb5aa3 --- /dev/null +++ b/mods/animales.pw.toml @@ -0,0 +1,13 @@ +name = "Animales" +filename = "TFA_1.1.jar" +side = "both" + +[download] +hash-format = "sha1" +hash = "25efd98a708d80f728ac64b2d58921efd040bcb9" +mode = "metadata:curseforge" + +[update] +[update.curseforge] +file-id = 2627336 +project-id = 287755 diff --git a/mods/modularui.pw.toml b/mods/modularui.pw.toml new file mode 100644 index 0000000..c07e20a --- /dev/null +++ b/mods/modularui.pw.toml @@ -0,0 +1,13 @@ +name = "ModularUI" +filename = "modularui-2.1.0.jar" +side = "both" + +[download] +hash-format = "sha1" +hash = "7b556f56865d9bfa1e303c151746687076ea6f53" +mode = "metadata:curseforge" + +[update] +[update.curseforge] +file-id = 4692436 +project-id = 624243 diff --git a/mods/worldedit.pw.toml b/mods/worldedit.pw.toml new file mode 100644 index 0000000..8aac64b --- /dev/null +++ b/mods/worldedit.pw.toml @@ -0,0 +1,13 @@ +name = "WorldEdit" +filename = "worldedit-forge-mc1.12.2-6.1.10-dist.jar" +side = "both" + +[download] +hash-format = "sha1" +hash = "17314bdab33678478af060d2156338ee34db8a09" +mode = "metadata:curseforge" + +[update] +[update.curseforge] +file-id = 2941712 +project-id = 225608 diff --git a/pack.toml b/pack.toml index be9efc5..5a8d430 100644 --- a/pack.toml +++ b/pack.toml @@ -6,7 +6,7 @@ pack-format = "packwiz:1.1.0" [index] file = "index.toml" hash-format = "sha256" -hash = "f968963f05cb6c667eea05bc2d6280e65893aa9184502e264ff3a008fcd9806b" +hash = "c18dc2c6ffadf04b54633a1ad1d0798315e188273acbfd2927dbefcb8d74df65" [versions] forge = "14.23.5.2860" diff --git a/scripts/misc/human_resources_multiblock.zs b/scripts/misc/human_resources_multiblock.zs new file mode 100644 index 0000000..3c9cfaf --- /dev/null +++ b/scripts/misc/human_resources_multiblock.zs @@ -0,0 +1,15 @@ +// tile.cbt.ulv_station_mb_1.name +recipes.remove(); +mods.avaritia.ExtremeCrafting.addShaped("tile.cbt.ulv_station_mb_1.name", * 1, [[, , , , , , , , ], [, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ]]); + +// metaitem.circuit.lv.component.sus.name +recipes.remove(); +mods.avaritia.ExtremeCrafting.addShaped("metaitem.circuit.lv.component.sus.name", * 1, [[, , , , , , , , ], [, null, null, null, null, null, null, null, ],[, null, null, , , , , null, ],[, null, , , null, null, null, null, ],[, null, , , , , , null, ],[, null, , , , , , null, ],[, null, null, , null, , null, null, ],[, null, null, , null, , null, null, ],[, , , , , , , , ]]); + +// metaitem.circuit.lv.motherboard_plating.name +recipes.remove(); +recipes.addShaped( * 1, [[, , ], [, , ],[, , ]]); + +// tile.cbt.ulv_circuit_multiblock_provider.name +recipes.remove(); +mods.avaritia.ExtremeCrafting.addShaped("tile.cbt.ulv_circuit_multiblock_provider.name", * 1, [[, , , , , , , , ], [, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ],[, , , , , , , , ]]); \ No newline at end of file