diff --git a/sdk/include/platform/sunburst/platform-uart.hh b/sdk/include/platform/sunburst/platform-uart.hh
index 0f6d46d7..663957e1 100644
--- a/sdk/include/platform/sunburst/platform-uart.hh
+++ b/sdk/include/platform/sunburst/platform-uart.hh
@@ -13,22 +13,20 @@
  * Rendered register documentation is served at:
  * https://opentitan.org/book/hw/ip/uart/doc/registers.html
  */
-template<unsigned DefaultBaudRate = 115'200>
-class OpenTitanUart
+struct OpenTitanUart
 {
-	public:
 	/**
 	 * Interrupt State Register.
 	 */
-	uint32_t intrState;
+	uint32_t interruptState;
 	/**
 	 * Interrupt Enable Register.
 	 */
-	uint32_t intrEnable;
+	uint32_t interruptEnable;
 	/**
 	 * Interrupt Test Register.
 	 */
-	uint32_t intrTest;
+	uint32_t interruptTest;
 	/**
 	 * Alert Test Register (unused).
 	 */
@@ -36,7 +34,7 @@ class OpenTitanUart
 	/**
 	 * Control Register.
 	 */
-	uint32_t ctrl;
+	uint32_t control;
 	/**
 	 * Status Register.
 	 */
@@ -44,11 +42,11 @@ class OpenTitanUart
 	/**
 	 * UART Read Data.
 	 */
-	uint32_t rData;
+	uint32_t readData;
 	/**
 	 * UART Write Data.
 	 */
-	uint32_t wData;
+	uint32_t writeData;
 	/**
 	 * UART FIFO Control Register.
 	 */
@@ -58,38 +56,73 @@ class OpenTitanUart
 	 */
 	uint32_t fifoStatus;
 	/**
-	 * TX Pin Override Control.
+	 * Transmit Pin Override Control.
 	 *
-	 * Gives direct SW control over TX pin state.
+	 * Gives direct software control over the transmit pin state.
 	 */
-	uint32_t ovrd;
+	uint32_t override;
 	/**
 	 * UART Oversampled Values.
 	 */
-	uint32_t val;
+	uint32_t values;
 	/**
-	 * UART RX Timeout Control.
+	 * UART Receive Timeout Control.
 	 */
-	uint32_t timeoutCtrl;
+	uint32_t timeoutControl;
 
-	void init(unsigned baudRate = DefaultBaudRate) volatile
+	/// Control Register Fields
+	enum : uint32_t
 	{
-		// NCO = 2^20 * baud rate / cpu frequency
-		const uint32_t NCO =
+		/// Sets the BAUD clock rate from the numerically controlled oscillator.
+		ControlNco = 0xff << 16,
+		/// Set the number of character times the line must be low
+		/// which will be interpreted as a break.
+		ControlReceiveBreakLevel = 0b11 << 8,
+		/// When set, odd parity is used, otherwise even parity is used.
+		ControlParityOdd = 1 << 7,
+		/// Enable party on both transmit and receive lines.
+		ControlParityEnable = 1 << 6,
+		/// When set, incoming received bits are forwarded to the transmit line.
+		ControlLineLoopback = 1 << 5,
+		/// When set, outgoing transmitted bits are routed back the receiving
+		/// line.
+		ControlSystemLoopback = 1 << 4,
+		/// Enable the noise filter on the receiving line.
+		ControlNoiseFilter = 1 << 2,
+		/// Enable receiving bits.
+		ControlReceiveEnable = 1 << 1,
+		/// Enable transmitting bits.
+		ControlTransmitEnable = 1 << 0,
+	};
+
+	void init(unsigned baudRate = 115'200) volatile
+	{
+		// Nco = 2^20 * baud rate / cpu frequency
+		const uint32_t Nco =
 		  ((static_cast<uint64_t>(baudRate) << 20) / CPU_TIMER_HZ);
 		// Set the baud rate and enable transmit & receive
-		ctrl = (NCO << 16) | 0b11;
-	};
+		control = (Nco << 16) | ControlTransmitEnable | ControlReceiveEnable;
+	}
+
+	[[gnu::always_inline]] uint16_t transmit_fifo_level() volatile
+	{
+		return fifoStatus & 0xff;
+	}
+
+	[[gnu::always_inline]] uint16_t receive_fifo_level() volatile
+	{
+		return ((fifoStatus >> 16) & 0xff);
+	}
 
 	bool can_write() volatile
 	{
-		return (fifoStatus & 0xff) < 32;
-	};
+		return transmit_fifo_level() < 32;
+	}
 
 	bool can_read() volatile
 	{
-		return ((fifoStatus >> 16) & 0xff) > 0;
-	};
+		return receive_fifo_level() > 0;
+	}
 
 	/**
 	 * Write one byte, blocking until the byte is written.
@@ -97,7 +130,7 @@ class OpenTitanUart
 	void blocking_write(uint8_t byte) volatile
 	{
 		while (!can_write()) {}
-		wData = byte;
+		writeData = byte;
 	}
 
 	/**
@@ -106,11 +139,11 @@ class OpenTitanUart
 	uint8_t blocking_read() volatile
 	{
 		while (!can_read()) {}
-		return rData;
+		return readData;
 	}
 };
 
 #ifndef CHERIOT_PLATFORM_CUSTOM_UART
-using Uart = OpenTitanUart<>;
+using Uart = OpenTitanUart;
 static_assert(IsUart<Uart>);
 #endif